Remove usrp1 and usrp2 FPGA files. These are now hosted at:
authorJohnathan Corgan <jcorgan@corganenterprises.com>
Sun, 28 Feb 2010 20:47:43 +0000 (12:47 -0800)
committerJohnathan Corgan <jcorgan@corganenterprises.com>
Sun, 28 Feb 2010 20:47:43 +0000 (12:47 -0800)
commita2c00f5cff7407ff10fc6c812d06fefe52c0b6a3
tree77121ca27b951f9bd687dbba33f6a9383ac74d5a
parentdb29a2cfc18554ae0a3c55a4e13dc4cbfa86317f
Remove usrp1 and usrp2 FPGA files.  These are now hosted at:

git://ettus.sourcerepo.com/ettus/fpga.git

...under the 'usrp1' and 'usrp2' top-level directories.
842 files changed:
usrp/fpga/Makefile.am
usrp/fpga/Makefile.extra [deleted file]
usrp/fpga/TODO [deleted file]
usrp/fpga/gen_makefile_extra.py [deleted file]
usrp/fpga/inband_lib/chan_fifo_reader.v [deleted file]
usrp/fpga/inband_lib/channel_demux.v [deleted file]
usrp/fpga/inband_lib/channel_ram.v [deleted file]
usrp/fpga/inband_lib/cmd_reader.v [deleted file]
usrp/fpga/inband_lib/packet_builder.v [deleted file]
usrp/fpga/inband_lib/register_io.v [deleted file]
usrp/fpga/inband_lib/rx_buffer_inband.v [deleted file]
usrp/fpga/inband_lib/tx_buffer_inband.v [deleted file]
usrp/fpga/inband_lib/tx_packer.v [deleted file]
usrp/fpga/inband_lib/usb_packet_fifo.v [deleted file]
usrp/fpga/megacells/.gitignore [deleted file]
usrp/fpga/megacells/accum32.bsf [deleted file]
usrp/fpga/megacells/accum32.cmp [deleted file]
usrp/fpga/megacells/accum32.inc [deleted file]
usrp/fpga/megacells/accum32.v [deleted file]
usrp/fpga/megacells/accum32_bb.v [deleted file]
usrp/fpga/megacells/accum32_inst.v [deleted file]
usrp/fpga/megacells/add32.bsf [deleted file]
usrp/fpga/megacells/add32.cmp [deleted file]
usrp/fpga/megacells/add32.inc [deleted file]
usrp/fpga/megacells/add32.v [deleted file]
usrp/fpga/megacells/add32_bb.v [deleted file]
usrp/fpga/megacells/add32_inst.v [deleted file]
usrp/fpga/megacells/addsub16.bsf [deleted file]
usrp/fpga/megacells/addsub16.cmp [deleted file]
usrp/fpga/megacells/addsub16.inc [deleted file]
usrp/fpga/megacells/addsub16.v [deleted file]
usrp/fpga/megacells/addsub16_bb.v [deleted file]
usrp/fpga/megacells/addsub16_inst.v [deleted file]
usrp/fpga/megacells/bustri.bsf [deleted file]
usrp/fpga/megacells/bustri.cmp [deleted file]
usrp/fpga/megacells/bustri.inc [deleted file]
usrp/fpga/megacells/bustri.v [deleted file]
usrp/fpga/megacells/bustri_bb.v [deleted file]
usrp/fpga/megacells/bustri_inst.v [deleted file]
usrp/fpga/megacells/clk_doubler.v [deleted file]
usrp/fpga/megacells/clk_doubler_bb.v [deleted file]
usrp/fpga/megacells/dspclkpll.v [deleted file]
usrp/fpga/megacells/dspclkpll_bb.v [deleted file]
usrp/fpga/megacells/fifo_1kx16.bsf [deleted file]
usrp/fpga/megacells/fifo_1kx16.cmp [deleted file]
usrp/fpga/megacells/fifo_1kx16.inc [deleted file]
usrp/fpga/megacells/fifo_1kx16.v [deleted file]
usrp/fpga/megacells/fifo_1kx16_bb.v [deleted file]
usrp/fpga/megacells/fifo_1kx16_inst.v [deleted file]
usrp/fpga/megacells/fifo_2k.v [deleted file]
usrp/fpga/megacells/fifo_2k_bb.v [deleted file]
usrp/fpga/megacells/fifo_4k.v [deleted file]
usrp/fpga/megacells/fifo_4k_18.v [deleted file]
usrp/fpga/megacells/fifo_4k_bb.v [deleted file]
usrp/fpga/megacells/fifo_4kx16_dc.bsf [deleted file]
usrp/fpga/megacells/fifo_4kx16_dc.cmp [deleted file]
usrp/fpga/megacells/fifo_4kx16_dc.inc [deleted file]
usrp/fpga/megacells/fifo_4kx16_dc.v [deleted file]
usrp/fpga/megacells/fifo_4kx16_dc_bb.v [deleted file]
usrp/fpga/megacells/fifo_4kx16_dc_inst.v [deleted file]
usrp/fpga/megacells/mylpm_addsub.bsf [deleted file]
usrp/fpga/megacells/mylpm_addsub.cmp [deleted file]
usrp/fpga/megacells/mylpm_addsub.inc [deleted file]
usrp/fpga/megacells/mylpm_addsub.v [deleted file]
usrp/fpga/megacells/mylpm_addsub_bb.v [deleted file]
usrp/fpga/megacells/mylpm_addsub_inst.v [deleted file]
usrp/fpga/megacells/pll.v [deleted file]
usrp/fpga/megacells/pll_bb.v [deleted file]
usrp/fpga/megacells/pll_inst.v [deleted file]
usrp/fpga/megacells/sub32.bsf [deleted file]
usrp/fpga/megacells/sub32.cmp [deleted file]
usrp/fpga/megacells/sub32.inc [deleted file]
usrp/fpga/megacells/sub32.v [deleted file]
usrp/fpga/megacells/sub32_bb.v [deleted file]
usrp/fpga/megacells/sub32_inst.v [deleted file]
usrp/fpga/models/bustri.v [deleted file]
usrp/fpga/models/fifo.v [deleted file]
usrp/fpga/models/fifo_1c_1k.v [deleted file]
usrp/fpga/models/fifo_1c_2k.v [deleted file]
usrp/fpga/models/fifo_1c_4k.v [deleted file]
usrp/fpga/models/fifo_1k.v [deleted file]
usrp/fpga/models/fifo_2k.v [deleted file]
usrp/fpga/models/fifo_4k.v [deleted file]
usrp/fpga/models/fifo_4k_18.v [deleted file]
usrp/fpga/models/pll.v [deleted file]
usrp/fpga/models/ssram.v [deleted file]
usrp/fpga/sdr_lib/.gitignore [deleted file]
usrp/fpga/sdr_lib/adc_interface.v [deleted file]
usrp/fpga/sdr_lib/atr_delay.v [deleted file]
usrp/fpga/sdr_lib/bidir_reg.v [deleted file]
usrp/fpga/sdr_lib/cic_dec_shifter.v [deleted file]
usrp/fpga/sdr_lib/cic_decim.v [deleted file]
usrp/fpga/sdr_lib/cic_int_shifter.v [deleted file]
usrp/fpga/sdr_lib/cic_interp.v [deleted file]
usrp/fpga/sdr_lib/clk_divider.v [deleted file]
usrp/fpga/sdr_lib/cordic.v [deleted file]
usrp/fpga/sdr_lib/cordic_stage.v [deleted file]
usrp/fpga/sdr_lib/ddc.v [deleted file]
usrp/fpga/sdr_lib/dpram.v [deleted file]
usrp/fpga/sdr_lib/duc.v [deleted file]
usrp/fpga/sdr_lib/ext_fifo.v [deleted file]
usrp/fpga/sdr_lib/gen_cordic_consts.py [deleted file]
usrp/fpga/sdr_lib/gen_sync.v [deleted file]
usrp/fpga/sdr_lib/hb/acc.v [deleted file]
usrp/fpga/sdr_lib/hb/coeff_rom.v [deleted file]
usrp/fpga/sdr_lib/hb/halfband_decim.v [deleted file]
usrp/fpga/sdr_lib/hb/halfband_interp.v [deleted file]
usrp/fpga/sdr_lib/hb/hbd_tb/HBD [deleted file]
usrp/fpga/sdr_lib/hb/hbd_tb/really_golden [deleted file]
usrp/fpga/sdr_lib/hb/hbd_tb/regression [deleted file]
usrp/fpga/sdr_lib/hb/hbd_tb/run_hbd [deleted file]
usrp/fpga/sdr_lib/hb/hbd_tb/test_hbd.v [deleted file]
usrp/fpga/sdr_lib/hb/mac.v [deleted file]
usrp/fpga/sdr_lib/hb/mult.v [deleted file]
usrp/fpga/sdr_lib/hb/ram16_2port.v [deleted file]
usrp/fpga/sdr_lib/hb/ram16_2sum.v [deleted file]
usrp/fpga/sdr_lib/hb/ram32_2sum.v [deleted file]
usrp/fpga/sdr_lib/io_pins.v [deleted file]
usrp/fpga/sdr_lib/master_control.v [deleted file]
usrp/fpga/sdr_lib/master_control_multi.v [deleted file]
usrp/fpga/sdr_lib/phase_acc.v [deleted file]
usrp/fpga/sdr_lib/ram.v [deleted file]
usrp/fpga/sdr_lib/ram16.v [deleted file]
usrp/fpga/sdr_lib/ram32.v [deleted file]
usrp/fpga/sdr_lib/ram64.v [deleted file]
usrp/fpga/sdr_lib/rssi.v [deleted file]
usrp/fpga/sdr_lib/rx_buffer.v [deleted file]
usrp/fpga/sdr_lib/rx_chain.v [deleted file]
usrp/fpga/sdr_lib/rx_chain_dual.v [deleted file]
usrp/fpga/sdr_lib/rx_dcoffset.v [deleted file]
usrp/fpga/sdr_lib/serial_io.v [deleted file]
usrp/fpga/sdr_lib/setting_reg.v [deleted file]
usrp/fpga/sdr_lib/setting_reg_masked.v [deleted file]
usrp/fpga/sdr_lib/sign_extend.v [deleted file]
usrp/fpga/sdr_lib/strobe_gen.v [deleted file]
usrp/fpga/sdr_lib/tx_buffer.v [deleted file]
usrp/fpga/sdr_lib/tx_chain.v [deleted file]
usrp/fpga/sdr_lib/tx_chain_hb.v [deleted file]
usrp/fpga/tb/.gitignore [deleted file]
usrp/fpga/tb/cbus_tb.v [deleted file]
usrp/fpga/tb/cordic_tb.v [deleted file]
usrp/fpga/tb/decim_tb.v [deleted file]
usrp/fpga/tb/fullchip_tb.v [deleted file]
usrp/fpga/tb/interp_tb.v [deleted file]
usrp/fpga/tb/justinterp_tb.v [deleted file]
usrp/fpga/tb/makesine.pl [deleted file]
usrp/fpga/tb/run_cordic [deleted file]
usrp/fpga/tb/run_fullchip [deleted file]
usrp/fpga/tb/usrp_tasks.v [deleted file]
usrp/fpga/toplevel/include/common_config_1rxhb_1tx.vh [deleted file]
usrp/fpga/toplevel/include/common_config_2rx_0tx.vh [deleted file]
usrp/fpga/toplevel/include/common_config_2rxhb_0tx.vh [deleted file]
usrp/fpga/toplevel/include/common_config_2rxhb_2tx.vh [deleted file]
usrp/fpga/toplevel/include/common_config_4rx_0tx.vh [deleted file]
usrp/fpga/toplevel/include/common_config_bottom.vh [deleted file]
usrp/fpga/toplevel/mrfm/.gitignore [deleted file]
usrp/fpga/toplevel/mrfm/biquad_2stage.v [deleted file]
usrp/fpga/toplevel/mrfm/biquad_6stage.v [deleted file]
usrp/fpga/toplevel/mrfm/mrfm.csf [deleted file]
usrp/fpga/toplevel/mrfm/mrfm.esf [deleted file]
usrp/fpga/toplevel/mrfm/mrfm.psf [deleted file]
usrp/fpga/toplevel/mrfm/mrfm.py [deleted file]
usrp/fpga/toplevel/mrfm/mrfm.qpf [deleted file]
usrp/fpga/toplevel/mrfm/mrfm.qsf [deleted file]
usrp/fpga/toplevel/mrfm/mrfm.v [deleted file]
usrp/fpga/toplevel/mrfm/mrfm.vh [deleted file]
usrp/fpga/toplevel/mrfm/mrfm_compensator.v [deleted file]
usrp/fpga/toplevel/mrfm/mrfm_fft.py [deleted file]
usrp/fpga/toplevel/mrfm/mrfm_proc.v [deleted file]
usrp/fpga/toplevel/mrfm/shifter.v [deleted file]
usrp/fpga/toplevel/sizetest/.gitignore [deleted file]
usrp/fpga/toplevel/sizetest/sizetest.csf [deleted file]
usrp/fpga/toplevel/sizetest/sizetest.psf [deleted file]
usrp/fpga/toplevel/sizetest/sizetest.quartus [deleted file]
usrp/fpga/toplevel/sizetest/sizetest.ssf [deleted file]
usrp/fpga/toplevel/sizetest/sizetest.v [deleted file]
usrp/fpga/toplevel/usrp_inband_usb/.gitignore [deleted file]
usrp/fpga/toplevel/usrp_inband_usb/config.vh [deleted file]
usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.csf [deleted file]
usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.esf [deleted file]
usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.psf [deleted file]
usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qpf [deleted file]
usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qsf [deleted file]
usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v [deleted file]
usrp/fpga/toplevel/usrp_multi/.gitignore [deleted file]
usrp/fpga/toplevel/usrp_multi/config.vh [deleted file]
usrp/fpga/toplevel/usrp_multi/usrp_multi.csf [deleted file]
usrp/fpga/toplevel/usrp_multi/usrp_multi.esf [deleted file]
usrp/fpga/toplevel/usrp_multi/usrp_multi.psf [deleted file]
usrp/fpga/toplevel/usrp_multi/usrp_multi.qpf [deleted file]
usrp/fpga/toplevel/usrp_multi/usrp_multi.qsf [deleted file]
usrp/fpga/toplevel/usrp_multi/usrp_multi.v [deleted file]
usrp/fpga/toplevel/usrp_std/.gitignore [deleted file]
usrp/fpga/toplevel/usrp_std/config.vh [deleted file]
usrp/fpga/toplevel/usrp_std/usrp_std.csf [deleted file]
usrp/fpga/toplevel/usrp_std/usrp_std.esf [deleted file]
usrp/fpga/toplevel/usrp_std/usrp_std.psf [deleted file]
usrp/fpga/toplevel/usrp_std/usrp_std.qpf [deleted file]
usrp/fpga/toplevel/usrp_std/usrp_std.qsf [deleted file]
usrp/fpga/toplevel/usrp_std/usrp_std.v [deleted file]
usrp2/fpga/.gitignore [deleted file]
usrp2/fpga/boot_cpld/.gitignore [deleted file]
usrp2/fpga/boot_cpld/_impact.cmd [deleted file]
usrp2/fpga/boot_cpld/boot_cpld.ipf [deleted file]
usrp2/fpga/boot_cpld/boot_cpld.ise [deleted file]
usrp2/fpga/boot_cpld/boot_cpld.lfp [deleted file]
usrp2/fpga/boot_cpld/boot_cpld.ucf [deleted file]
usrp2/fpga/boot_cpld/boot_cpld.v [deleted file]
usrp2/fpga/control_lib/.gitignore [deleted file]
usrp2/fpga/control_lib/CRC16_D16.v [deleted file]
usrp2/fpga/control_lib/SYSCTRL.sav [deleted file]
usrp2/fpga/control_lib/WB_SIM.sav [deleted file]
usrp2/fpga/control_lib/atr_controller.v [deleted file]
usrp2/fpga/control_lib/bin2gray.v [deleted file]
usrp2/fpga/control_lib/bootrom.mem [deleted file]
usrp2/fpga/control_lib/clock_bootstrap_rom.v [deleted file]
usrp2/fpga/control_lib/clock_control.v [deleted file]
usrp2/fpga/control_lib/clock_control_tb.sav [deleted file]
usrp2/fpga/control_lib/clock_control_tb.v [deleted file]
usrp2/fpga/control_lib/cmdfile [deleted file]
usrp2/fpga/control_lib/dcache.v [deleted file]
usrp2/fpga/control_lib/decoder_3_8.v [deleted file]
usrp2/fpga/control_lib/dpram32.v [deleted file]
usrp2/fpga/control_lib/fifo_tb.v [deleted file]
usrp2/fpga/control_lib/gray2bin.v [deleted file]
usrp2/fpga/control_lib/gray_send.v [deleted file]
usrp2/fpga/control_lib/icache.v [deleted file]
usrp2/fpga/control_lib/longfifo.v [deleted file]
usrp2/fpga/control_lib/medfifo.v [deleted file]
usrp2/fpga/control_lib/mux4.v [deleted file]
usrp2/fpga/control_lib/mux8.v [deleted file]
usrp2/fpga/control_lib/mux_32_4.v [deleted file]
usrp2/fpga/control_lib/newfifo/.gitignore [deleted file]
usrp2/fpga/control_lib/newfifo/buffer_int.v [deleted file]
usrp2/fpga/control_lib/newfifo/buffer_int_tb.v [deleted file]
usrp2/fpga/control_lib/newfifo/buffer_pool.v [deleted file]
usrp2/fpga/control_lib/newfifo/buffer_pool_tb.v [deleted file]
usrp2/fpga/control_lib/newfifo/fifo19_to_fifo36.v [deleted file]
usrp2/fpga/control_lib/newfifo/fifo19_to_ll8.v [deleted file]
usrp2/fpga/control_lib/newfifo/fifo36_to_fifo18.v [deleted file]
usrp2/fpga/control_lib/newfifo/fifo36_to_fifo19.v [deleted file]
usrp2/fpga/control_lib/newfifo/fifo36_to_ll8.v [deleted file]
usrp2/fpga/control_lib/newfifo/fifo_2clock.v [deleted file]
usrp2/fpga/control_lib/newfifo/fifo_2clock_cascade.v [deleted file]
usrp2/fpga/control_lib/newfifo/fifo_cascade.v [deleted file]
usrp2/fpga/control_lib/newfifo/fifo_long.v [deleted file]
usrp2/fpga/control_lib/newfifo/fifo_new_tb.vcd [deleted file]
usrp2/fpga/control_lib/newfifo/fifo_short.v [deleted file]
usrp2/fpga/control_lib/newfifo/fifo_spec.txt [deleted file]
usrp2/fpga/control_lib/newfifo/fifo_tb.v [deleted file]
usrp2/fpga/control_lib/newfifo/ll8_shortfifo.v [deleted file]
usrp2/fpga/control_lib/newfifo/ll8_to_fifo19.v [deleted file]
usrp2/fpga/control_lib/newfifo/ll8_to_fifo36.v [deleted file]
usrp2/fpga/control_lib/nsgpio.v [deleted file]
usrp2/fpga/control_lib/oneshot_2clk.v [deleted file]
usrp2/fpga/control_lib/pic.v [deleted file]
usrp2/fpga/control_lib/priority_enc.v [deleted file]
usrp2/fpga/control_lib/ram_2port.v [deleted file]
usrp2/fpga/control_lib/ram_harv_cache.v [deleted file]
usrp2/fpga/control_lib/ram_loader.v [deleted file]
usrp2/fpga/control_lib/ram_wb_harvard.v [deleted file]
usrp2/fpga/control_lib/reset_sync.v [deleted file]
usrp2/fpga/control_lib/sd_spi.v [deleted file]
usrp2/fpga/control_lib/sd_spi_tb.v [deleted file]
usrp2/fpga/control_lib/sd_spi_wb.v [deleted file]
usrp2/fpga/control_lib/setting_reg.v [deleted file]
usrp2/fpga/control_lib/settings_bus.v [deleted file]
usrp2/fpga/control_lib/shortfifo.v [deleted file]
usrp2/fpga/control_lib/simple_uart.v [deleted file]
usrp2/fpga/control_lib/simple_uart_rx.v [deleted file]
usrp2/fpga/control_lib/simple_uart_tx.v [deleted file]
usrp2/fpga/control_lib/spi.v [deleted file]
usrp2/fpga/control_lib/srl.v [deleted file]
usrp2/fpga/control_lib/ss_rcvr.v [deleted file]
usrp2/fpga/control_lib/system_control.v [deleted file]
usrp2/fpga/control_lib/system_control_tb.v [deleted file]
usrp2/fpga/control_lib/traffic_cop.v [deleted file]
usrp2/fpga/control_lib/wb_1master.v [deleted file]
usrp2/fpga/control_lib/wb_bridge_16_32.v [deleted file]
usrp2/fpga/control_lib/wb_bus_writer.v [deleted file]
usrp2/fpga/control_lib/wb_output_pins32.v [deleted file]
usrp2/fpga/control_lib/wb_ram_block.v [deleted file]
usrp2/fpga/control_lib/wb_ram_dist.v [deleted file]
usrp2/fpga/control_lib/wb_readback_mux.v [deleted file]
usrp2/fpga/control_lib/wb_regfile_2clock.v [deleted file]
usrp2/fpga/control_lib/wb_semaphore.v [deleted file]
usrp2/fpga/control_lib/wb_sim.v [deleted file]
usrp2/fpga/coregen/.gitignore [deleted file]
usrp2/fpga/coregen/coregen.cgp [deleted file]
usrp2/fpga/coregen/fifo_generator_release_notes.txt [deleted file]
usrp2/fpga/coregen/fifo_generator_ug175.pdf [deleted file]
usrp2/fpga/coregen/fifo_xlnx_16x19_2clk.ngc [deleted file]
usrp2/fpga/coregen/fifo_xlnx_16x19_2clk.v [deleted file]
usrp2/fpga/coregen/fifo_xlnx_16x19_2clk.veo [deleted file]
usrp2/fpga/coregen/fifo_xlnx_16x19_2clk.xco [deleted file]
usrp2/fpga/coregen/fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.lso [deleted file]
usrp2/fpga/coregen/fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt [deleted file]
usrp2/fpga/coregen/fifo_xlnx_16x19_2clk_flist.txt [deleted file]
usrp2/fpga/coregen/fifo_xlnx_16x19_2clk_readme.txt [deleted file]
usrp2/fpga/coregen/fifo_xlnx_16x19_2clk_xmdf.tcl [deleted file]
usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk.asy [deleted file]
usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk.ngc [deleted file]
usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk.sym [deleted file]
usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk.v [deleted file]
usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk.veo [deleted file]
usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk.vhd [deleted file]
usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk.vho [deleted file]
usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk.xco [deleted file]
usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.lso [deleted file]
usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt [deleted file]
usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk_flist.txt [deleted file]
usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk_readme.txt [deleted file]
usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk_xmdf.tcl [deleted file]
usrp2/fpga/coregen/fifo_xlnx_512x36_2clk.asy [deleted file]
usrp2/fpga/coregen/fifo_xlnx_512x36_2clk.ngc [deleted file]
usrp2/fpga/coregen/fifo_xlnx_512x36_2clk.sym [deleted file]
usrp2/fpga/coregen/fifo_xlnx_512x36_2clk.v [deleted file]
usrp2/fpga/coregen/fifo_xlnx_512x36_2clk.veo [deleted file]
usrp2/fpga/coregen/fifo_xlnx_512x36_2clk.vhd [deleted file]
usrp2/fpga/coregen/fifo_xlnx_512x36_2clk.vho [deleted file]
usrp2/fpga/coregen/fifo_xlnx_512x36_2clk.xco [deleted file]
usrp2/fpga/coregen/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.lso [deleted file]
usrp2/fpga/coregen/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt [deleted file]
usrp2/fpga/coregen/fifo_xlnx_512x36_2clk_flist.txt [deleted file]
usrp2/fpga/coregen/fifo_xlnx_512x36_2clk_readme.txt [deleted file]
usrp2/fpga/coregen/fifo_xlnx_512x36_2clk_xmdf.tcl [deleted file]
usrp2/fpga/coregen/fifo_xlnx_64x36_2clk.ngc [deleted file]
usrp2/fpga/coregen/fifo_xlnx_64x36_2clk.v [deleted file]
usrp2/fpga/coregen/fifo_xlnx_64x36_2clk.veo [deleted file]
usrp2/fpga/coregen/fifo_xlnx_64x36_2clk.xco [deleted file]
usrp2/fpga/coregen/fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.lso [deleted file]
usrp2/fpga/coregen/fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt [deleted file]
usrp2/fpga/coregen/fifo_xlnx_64x36_2clk_flist.txt [deleted file]
usrp2/fpga/coregen/fifo_xlnx_64x36_2clk_readme.txt [deleted file]
usrp2/fpga/coregen/fifo_xlnx_64x36_2clk_xmdf.tcl [deleted file]
usrp2/fpga/extram/.gitignore [deleted file]
usrp2/fpga/extram/extram_interface.v [deleted file]
usrp2/fpga/extram/extram_wb.v [deleted file]
usrp2/fpga/extram/wb_zbt16_b.v [deleted file]
usrp2/fpga/models/BUFG.v [deleted file]
usrp2/fpga/models/CY7C1356C/cy1356.inp [deleted file]
usrp2/fpga/models/CY7C1356C/cy1356.v [deleted file]
usrp2/fpga/models/CY7C1356C/readme.txt [deleted file]
usrp2/fpga/models/CY7C1356C/testbench.v [deleted file]
usrp2/fpga/models/FIFO_GENERATOR_V4_3.v [deleted file]
usrp2/fpga/models/M24LC024B.v [deleted file]
usrp2/fpga/models/M24LC02B.v [deleted file]
usrp2/fpga/models/MULT18X18S.v [deleted file]
usrp2/fpga/models/RAMB16_S36_S36.v [deleted file]
usrp2/fpga/models/SRL16E.v [deleted file]
usrp2/fpga/models/SRLC16E.v [deleted file]
usrp2/fpga/models/adc_model.v [deleted file]
usrp2/fpga/models/cpld_model.v [deleted file]
usrp2/fpga/models/math_real.v [deleted file]
usrp2/fpga/models/miim_model.v [deleted file]
usrp2/fpga/models/phy_sim.v [deleted file]
usrp2/fpga/models/serdes_model.v [deleted file]
usrp2/fpga/models/uart_rx.v [deleted file]
usrp2/fpga/models/xlnx_glbl.v [deleted file]
usrp2/fpga/opencores/8b10b/.gitignore [deleted file]
usrp2/fpga/opencores/8b10b/8b10b_a.mem [deleted file]
usrp2/fpga/opencores/8b10b/README [deleted file]
usrp2/fpga/opencores/8b10b/decode_8b10b.v [deleted file]
usrp2/fpga/opencores/8b10b/encode_8b10b.v [deleted file]
usrp2/fpga/opencores/8b10b/validate_8b10b.v [deleted file]
usrp2/fpga/opencores/README [deleted file]
usrp2/fpga/opencores/aemb/CVS/.gitignore [deleted file]
usrp2/fpga/opencores/aemb/CVS/Entries [deleted file]
usrp2/fpga/opencores/aemb/CVS/Repository [deleted file]
usrp2/fpga/opencores/aemb/CVS/Root [deleted file]
usrp2/fpga/opencores/aemb/CVS/Template [deleted file]
usrp2/fpga/opencores/aemb/doc/CVS/Entries [deleted file]
usrp2/fpga/opencores/aemb/doc/CVS/Repository [deleted file]
usrp2/fpga/opencores/aemb/doc/CVS/Root [deleted file]
usrp2/fpga/opencores/aemb/doc/CVS/Template [deleted file]
usrp2/fpga/opencores/aemb/doc/aeMB_datasheet.pdf [deleted file]
usrp2/fpga/opencores/aemb/rtl/CVS/Entries [deleted file]
usrp2/fpga/opencores/aemb/rtl/CVS/Repository [deleted file]
usrp2/fpga/opencores/aemb/rtl/CVS/Root [deleted file]
usrp2/fpga/opencores/aemb/rtl/CVS/Template [deleted file]
usrp2/fpga/opencores/aemb/rtl/verilog/.gitignore [deleted file]
usrp2/fpga/opencores/aemb/rtl/verilog/CVS/Entries [deleted file]
usrp2/fpga/opencores/aemb/rtl/verilog/CVS/Repository [deleted file]
usrp2/fpga/opencores/aemb/rtl/verilog/CVS/Root [deleted file]
usrp2/fpga/opencores/aemb/rtl/verilog/CVS/Template [deleted file]
usrp2/fpga/opencores/aemb/rtl/verilog/aeMB_bpcu.v [deleted file]
usrp2/fpga/opencores/aemb/rtl/verilog/aeMB_core.v [deleted file]
usrp2/fpga/opencores/aemb/rtl/verilog/aeMB_core_BE.v [deleted file]
usrp2/fpga/opencores/aemb/rtl/verilog/aeMB_ctrl.v [deleted file]
usrp2/fpga/opencores/aemb/rtl/verilog/aeMB_edk32.v [deleted file]
usrp2/fpga/opencores/aemb/rtl/verilog/aeMB_ibuf.v [deleted file]
usrp2/fpga/opencores/aemb/rtl/verilog/aeMB_regf.v [deleted file]
usrp2/fpga/opencores/aemb/rtl/verilog/aeMB_sim.v [deleted file]
usrp2/fpga/opencores/aemb/rtl/verilog/aeMB_xecu.v [deleted file]
usrp2/fpga/opencores/aemb/sim/.gitignore [deleted file]
usrp2/fpga/opencores/aemb/sim/CODE_DEBUG.sav [deleted file]
usrp2/fpga/opencores/aemb/sim/CVS/Entries [deleted file]
usrp2/fpga/opencores/aemb/sim/CVS/Repository [deleted file]
usrp2/fpga/opencores/aemb/sim/CVS/Root [deleted file]
usrp2/fpga/opencores/aemb/sim/CVS/Template [deleted file]
usrp2/fpga/opencores/aemb/sim/cversim [deleted file]
usrp2/fpga/opencores/aemb/sim/iversim [deleted file]
usrp2/fpga/opencores/aemb/sim/verilog/CVS/Entries [deleted file]
usrp2/fpga/opencores/aemb/sim/verilog/CVS/Repository [deleted file]
usrp2/fpga/opencores/aemb/sim/verilog/CVS/Root [deleted file]
usrp2/fpga/opencores/aemb/sim/verilog/CVS/Template [deleted file]
usrp2/fpga/opencores/aemb/sim/verilog/aemb2.v [deleted file]
usrp2/fpga/opencores/aemb/sim/verilog/edk32.v [deleted file]
usrp2/fpga/opencores/aemb/sw/CVS/Entries [deleted file]
usrp2/fpga/opencores/aemb/sw/CVS/Repository [deleted file]
usrp2/fpga/opencores/aemb/sw/CVS/Root [deleted file]
usrp2/fpga/opencores/aemb/sw/CVS/Template [deleted file]
usrp2/fpga/opencores/aemb/sw/c/CVS/Entries [deleted file]
usrp2/fpga/opencores/aemb/sw/c/CVS/Repository [deleted file]
usrp2/fpga/opencores/aemb/sw/c/CVS/Root [deleted file]
usrp2/fpga/opencores/aemb/sw/c/CVS/Template [deleted file]
usrp2/fpga/opencores/aemb/sw/c/aeMB_testbench.c [deleted file]
usrp2/fpga/opencores/aemb/sw/c/endian-test.c [deleted file]
usrp2/fpga/opencores/aemb/sw/c/libaemb.h [deleted file]
usrp2/fpga/opencores/aemb/sw/gccrom [deleted file]
usrp2/fpga/opencores/i2c/CVS/Entries [deleted file]
usrp2/fpga/opencores/i2c/CVS/Repository [deleted file]
usrp2/fpga/opencores/i2c/CVS/Root [deleted file]
usrp2/fpga/opencores/i2c/CVS/Template [deleted file]
usrp2/fpga/opencores/i2c/bench/CVS/Entries [deleted file]
usrp2/fpga/opencores/i2c/bench/CVS/Repository [deleted file]
usrp2/fpga/opencores/i2c/bench/CVS/Root [deleted file]
usrp2/fpga/opencores/i2c/bench/CVS/Template [deleted file]
usrp2/fpga/opencores/i2c/bench/verilog/CVS/Entries [deleted file]
usrp2/fpga/opencores/i2c/bench/verilog/CVS/Repository [deleted file]
usrp2/fpga/opencores/i2c/bench/verilog/CVS/Root [deleted file]
usrp2/fpga/opencores/i2c/bench/verilog/CVS/Template [deleted file]
usrp2/fpga/opencores/i2c/bench/verilog/i2c_slave_model.v [deleted file]
usrp2/fpga/opencores/i2c/bench/verilog/spi_slave_model.v [deleted file]
usrp2/fpga/opencores/i2c/bench/verilog/tst_bench_top.v [deleted file]
usrp2/fpga/opencores/i2c/bench/verilog/wb_master_model.v [deleted file]
usrp2/fpga/opencores/i2c/doc/CVS/Entries [deleted file]
usrp2/fpga/opencores/i2c/doc/CVS/Repository [deleted file]
usrp2/fpga/opencores/i2c/doc/CVS/Root [deleted file]
usrp2/fpga/opencores/i2c/doc/CVS/Template [deleted file]
usrp2/fpga/opencores/i2c/doc/i2c_specs.pdf [deleted file]
usrp2/fpga/opencores/i2c/doc/src/CVS/Entries [deleted file]
usrp2/fpga/opencores/i2c/doc/src/CVS/Repository [deleted file]
usrp2/fpga/opencores/i2c/doc/src/CVS/Root [deleted file]
usrp2/fpga/opencores/i2c/doc/src/CVS/Template [deleted file]
usrp2/fpga/opencores/i2c/doc/src/I2C_specs.doc [deleted file]
usrp2/fpga/opencores/i2c/documentation/CVS/Entries [deleted file]
usrp2/fpga/opencores/i2c/documentation/CVS/Repository [deleted file]
usrp2/fpga/opencores/i2c/documentation/CVS/Root [deleted file]
usrp2/fpga/opencores/i2c/documentation/CVS/Template [deleted file]
usrp2/fpga/opencores/i2c/rtl/CVS/Entries [deleted file]
usrp2/fpga/opencores/i2c/rtl/CVS/Repository [deleted file]
usrp2/fpga/opencores/i2c/rtl/CVS/Root [deleted file]
usrp2/fpga/opencores/i2c/rtl/CVS/Template [deleted file]
usrp2/fpga/opencores/i2c/rtl/verilog/CVS/Entries [deleted file]
usrp2/fpga/opencores/i2c/rtl/verilog/CVS/Repository [deleted file]
usrp2/fpga/opencores/i2c/rtl/verilog/CVS/Root [deleted file]
usrp2/fpga/opencores/i2c/rtl/verilog/CVS/Template [deleted file]
usrp2/fpga/opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v [deleted file]
usrp2/fpga/opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v [deleted file]
usrp2/fpga/opencores/i2c/rtl/verilog/i2c_master_defines.v [deleted file]
usrp2/fpga/opencores/i2c/rtl/verilog/i2c_master_top.v [deleted file]
usrp2/fpga/opencores/i2c/rtl/verilog/timescale.v [deleted file]
usrp2/fpga/opencores/i2c/rtl/vhdl/CVS/Entries [deleted file]
usrp2/fpga/opencores/i2c/rtl/vhdl/CVS/Repository [deleted file]
usrp2/fpga/opencores/i2c/rtl/vhdl/CVS/Root [deleted file]
usrp2/fpga/opencores/i2c/rtl/vhdl/CVS/Template [deleted file]
usrp2/fpga/opencores/i2c/rtl/vhdl/I2C.VHD [deleted file]
usrp2/fpga/opencores/i2c/rtl/vhdl/i2c_master_bit_ctrl.vhd [deleted file]
usrp2/fpga/opencores/i2c/rtl/vhdl/i2c_master_byte_ctrl.vhd [deleted file]
usrp2/fpga/opencores/i2c/rtl/vhdl/i2c_master_top.vhd [deleted file]
usrp2/fpga/opencores/i2c/rtl/vhdl/readme [deleted file]
usrp2/fpga/opencores/i2c/rtl/vhdl/tst_ds1621.vhd [deleted file]
usrp2/fpga/opencores/i2c/sim/CVS/Entries [deleted file]
usrp2/fpga/opencores/i2c/sim/CVS/Repository [deleted file]
usrp2/fpga/opencores/i2c/sim/CVS/Root [deleted file]
usrp2/fpga/opencores/i2c/sim/CVS/Template [deleted file]
usrp2/fpga/opencores/i2c/sim/i2c_verilog/CVS/Entries [deleted file]
usrp2/fpga/opencores/i2c/sim/i2c_verilog/CVS/Repository [deleted file]
usrp2/fpga/opencores/i2c/sim/i2c_verilog/CVS/Root [deleted file]
usrp2/fpga/opencores/i2c/sim/i2c_verilog/CVS/Template [deleted file]
usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/CVS/Entries [deleted file]
usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/CVS/Repository [deleted file]
usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/CVS/Root [deleted file]
usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/CVS/Template [deleted file]
usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Entries [deleted file]
usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Repository [deleted file]
usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Root [deleted file]
usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Template [deleted file]
usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/bench.vcd [deleted file]
usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/ncverilog.key [deleted file]
usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/ncverilog.log [deleted file]
usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/run [deleted file]
usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Entries [deleted file]
usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Repository [deleted file]
usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Root [deleted file]
usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Template [deleted file]
usrp2/fpga/opencores/i2c/software/CVS/Entries [deleted file]
usrp2/fpga/opencores/i2c/software/CVS/Repository [deleted file]
usrp2/fpga/opencores/i2c/software/CVS/Root [deleted file]
usrp2/fpga/opencores/i2c/software/CVS/Template [deleted file]
usrp2/fpga/opencores/i2c/software/drivers/CVS/Entries [deleted file]
usrp2/fpga/opencores/i2c/software/drivers/CVS/Repository [deleted file]
usrp2/fpga/opencores/i2c/software/drivers/CVS/Root [deleted file]
usrp2/fpga/opencores/i2c/software/drivers/CVS/Template [deleted file]
usrp2/fpga/opencores/i2c/software/include/CVS/Entries [deleted file]
usrp2/fpga/opencores/i2c/software/include/CVS/Repository [deleted file]
usrp2/fpga/opencores/i2c/software/include/CVS/Root [deleted file]
usrp2/fpga/opencores/i2c/software/include/CVS/Template [deleted file]
usrp2/fpga/opencores/i2c/software/include/oc_i2c_master.h [deleted file]
usrp2/fpga/opencores/i2c/verilog/CVS/Entries [deleted file]
usrp2/fpga/opencores/i2c/verilog/CVS/Repository [deleted file]
usrp2/fpga/opencores/i2c/verilog/CVS/Root [deleted file]
usrp2/fpga/opencores/i2c/verilog/CVS/Template [deleted file]
usrp2/fpga/opencores/i2c/vhdl/CVS/Entries [deleted file]
usrp2/fpga/opencores/i2c/vhdl/CVS/Repository [deleted file]
usrp2/fpga/opencores/i2c/vhdl/CVS/Root [deleted file]
usrp2/fpga/opencores/i2c/vhdl/CVS/Template [deleted file]
usrp2/fpga/opencores/simple_gpio/CVS/Entries [deleted file]
usrp2/fpga/opencores/simple_gpio/CVS/Repository [deleted file]
usrp2/fpga/opencores/simple_gpio/CVS/Root [deleted file]
usrp2/fpga/opencores/simple_gpio/CVS/Template [deleted file]
usrp2/fpga/opencores/simple_gpio/rtl/CVS/Entries [deleted file]
usrp2/fpga/opencores/simple_gpio/rtl/CVS/Repository [deleted file]
usrp2/fpga/opencores/simple_gpio/rtl/CVS/Root [deleted file]
usrp2/fpga/opencores/simple_gpio/rtl/CVS/Template [deleted file]
usrp2/fpga/opencores/simple_gpio/rtl/simple_gpio.v [deleted file]
usrp2/fpga/opencores/simple_pic/CVS/Entries [deleted file]
usrp2/fpga/opencores/simple_pic/CVS/Repository [deleted file]
usrp2/fpga/opencores/simple_pic/CVS/Root [deleted file]
usrp2/fpga/opencores/simple_pic/CVS/Template [deleted file]
usrp2/fpga/opencores/simple_pic/rtl/CVS/Entries [deleted file]
usrp2/fpga/opencores/simple_pic/rtl/CVS/Repository [deleted file]
usrp2/fpga/opencores/simple_pic/rtl/CVS/Root [deleted file]
usrp2/fpga/opencores/simple_pic/rtl/CVS/Template [deleted file]
usrp2/fpga/opencores/simple_pic/rtl/simple_pic.v [deleted file]
usrp2/fpga/opencores/spi/CVS/Entries [deleted file]
usrp2/fpga/opencores/spi/CVS/Repository [deleted file]
usrp2/fpga/opencores/spi/CVS/Root [deleted file]
usrp2/fpga/opencores/spi/CVS/Template [deleted file]
usrp2/fpga/opencores/spi/bench/CVS/Entries [deleted file]
usrp2/fpga/opencores/spi/bench/CVS/Repository [deleted file]
usrp2/fpga/opencores/spi/bench/CVS/Root [deleted file]
usrp2/fpga/opencores/spi/bench/CVS/Template [deleted file]
usrp2/fpga/opencores/spi/bench/verilog/CVS/Entries [deleted file]
usrp2/fpga/opencores/spi/bench/verilog/CVS/Repository [deleted file]
usrp2/fpga/opencores/spi/bench/verilog/CVS/Root [deleted file]
usrp2/fpga/opencores/spi/bench/verilog/CVS/Template [deleted file]
usrp2/fpga/opencores/spi/bench/verilog/spi_slave_model.v [deleted file]
usrp2/fpga/opencores/spi/bench/verilog/tb_spi_top.v [deleted file]
usrp2/fpga/opencores/spi/bench/verilog/wb_master_model.v [deleted file]
usrp2/fpga/opencores/spi/doc/CVS/Entries [deleted file]
usrp2/fpga/opencores/spi/doc/CVS/Repository [deleted file]
usrp2/fpga/opencores/spi/doc/CVS/Root [deleted file]
usrp2/fpga/opencores/spi/doc/CVS/Template [deleted file]
usrp2/fpga/opencores/spi/doc/spi.pdf [deleted file]
usrp2/fpga/opencores/spi/doc/src/CVS/Entries [deleted file]
usrp2/fpga/opencores/spi/doc/src/CVS/Repository [deleted file]
usrp2/fpga/opencores/spi/doc/src/CVS/Root [deleted file]
usrp2/fpga/opencores/spi/doc/src/CVS/Template [deleted file]
usrp2/fpga/opencores/spi/doc/src/spi.doc [deleted file]
usrp2/fpga/opencores/spi/rtl/CVS/Entries [deleted file]
usrp2/fpga/opencores/spi/rtl/CVS/Repository [deleted file]
usrp2/fpga/opencores/spi/rtl/CVS/Root [deleted file]
usrp2/fpga/opencores/spi/rtl/CVS/Template [deleted file]
usrp2/fpga/opencores/spi/rtl/verilog/CVS/Entries [deleted file]
usrp2/fpga/opencores/spi/rtl/verilog/CVS/Repository [deleted file]
usrp2/fpga/opencores/spi/rtl/verilog/CVS/Root [deleted file]
usrp2/fpga/opencores/spi/rtl/verilog/CVS/Template [deleted file]
usrp2/fpga/opencores/spi/rtl/verilog/spi_clgen.v [deleted file]
usrp2/fpga/opencores/spi/rtl/verilog/spi_defines.v [deleted file]
usrp2/fpga/opencores/spi/rtl/verilog/spi_shift.v [deleted file]
usrp2/fpga/opencores/spi/rtl/verilog/spi_top.v [deleted file]
usrp2/fpga/opencores/spi/rtl/verilog/timescale.v [deleted file]
usrp2/fpga/opencores/spi/sim/CVS/Entries [deleted file]
usrp2/fpga/opencores/spi/sim/CVS/Repository [deleted file]
usrp2/fpga/opencores/spi/sim/CVS/Root [deleted file]
usrp2/fpga/opencores/spi/sim/CVS/Template [deleted file]
usrp2/fpga/opencores/spi/sim/rtl_sim/CVS/Entries [deleted file]
usrp2/fpga/opencores/spi/sim/rtl_sim/CVS/Repository [deleted file]
usrp2/fpga/opencores/spi/sim/rtl_sim/CVS/Root [deleted file]
usrp2/fpga/opencores/spi/sim/rtl_sim/CVS/Template [deleted file]
usrp2/fpga/opencores/spi/sim/rtl_sim/run/CVS/Entries [deleted file]
usrp2/fpga/opencores/spi/sim/rtl_sim/run/CVS/Repository [deleted file]
usrp2/fpga/opencores/spi/sim/rtl_sim/run/CVS/Root [deleted file]
usrp2/fpga/opencores/spi/sim/rtl_sim/run/CVS/Template [deleted file]
usrp2/fpga/opencores/spi/sim/rtl_sim/run/rtl.fl [deleted file]
usrp2/fpga/opencores/spi/sim/rtl_sim/run/run_sim [deleted file]
usrp2/fpga/opencores/spi/sim/rtl_sim/run/sim.fl [deleted file]
usrp2/fpga/opencores/spi/sim/run/CVS/Entries [deleted file]
usrp2/fpga/opencores/spi/sim/run/CVS/Repository [deleted file]
usrp2/fpga/opencores/spi/sim/run/CVS/Root [deleted file]
usrp2/fpga/opencores/spi/sim/run/CVS/Template [deleted file]
usrp2/fpga/opencores/spi_boot/COMPILE_LIST [deleted file]
usrp2/fpga/opencores/spi_boot/COPYING [deleted file]
usrp2/fpga/opencores/spi_boot/CVS/Entries [deleted file]
usrp2/fpga/opencores/spi_boot/CVS/Repository [deleted file]
usrp2/fpga/opencores/spi_boot/CVS/Root [deleted file]
usrp2/fpga/opencores/spi_boot/CVS/Template [deleted file]
usrp2/fpga/opencores/spi_boot/KNOWN_BUGS [deleted file]
usrp2/fpga/opencores/spi_boot/README [deleted file]
usrp2/fpga/opencores/spi_boot/bench/CVS/Entries [deleted file]
usrp2/fpga/opencores/spi_boot/bench/CVS/Repository [deleted file]
usrp2/fpga/opencores/spi_boot/bench/CVS/Root [deleted file]
usrp2/fpga/opencores/spi_boot/bench/CVS/Template [deleted file]
usrp2/fpga/opencores/spi_boot/bench/vhdl/CVS/Entries [deleted file]
usrp2/fpga/opencores/spi_boot/bench/vhdl/CVS/Repository [deleted file]
usrp2/fpga/opencores/spi_boot/bench/vhdl/CVS/Root [deleted file]
usrp2/fpga/opencores/spi_boot/bench/vhdl/CVS/Template [deleted file]
usrp2/fpga/opencores/spi_boot/bench/vhdl/card-c.vhd [deleted file]
usrp2/fpga/opencores/spi_boot/bench/vhdl/card.vhd [deleted file]
usrp2/fpga/opencores/spi_boot/bench/vhdl/tb-c.vhd [deleted file]
usrp2/fpga/opencores/spi_boot/bench/vhdl/tb.vhd [deleted file]
usrp2/fpga/opencores/spi_boot/bench/vhdl/tb_elem-full-c.vhd [deleted file]
usrp2/fpga/opencores/spi_boot/bench/vhdl/tb_elem-minimal-c.vhd [deleted file]
usrp2/fpga/opencores/spi_boot/bench/vhdl/tb_elem-mmc-c.vhd [deleted file]
usrp2/fpga/opencores/spi_boot/bench/vhdl/tb_elem-sd-c.vhd [deleted file]
usrp2/fpga/opencores/spi_boot/bench/vhdl/tb_elem.vhd [deleted file]
usrp2/fpga/opencores/spi_boot/bench/vhdl/tb_pack-p.vhd [deleted file]
usrp2/fpga/opencores/spi_boot/bench/vhdl/tb_rl-c.vhd [deleted file]
usrp2/fpga/opencores/spi_boot/bench/vhdl/tb_rl.vhd [deleted file]
usrp2/fpga/opencores/spi_boot/doc/CVS/Entries [deleted file]
usrp2/fpga/opencores/spi_boot/doc/CVS/Repository [deleted file]
usrp2/fpga/opencores/spi_boot/doc/CVS/Root [deleted file]
usrp2/fpga/opencores/spi_boot/doc/CVS/Template [deleted file]
usrp2/fpga/opencores/spi_boot/doc/spi_boot.pdf [deleted file]
usrp2/fpga/opencores/spi_boot/doc/spi_boot_schematic.pdf [deleted file]
usrp2/fpga/opencores/spi_boot/doc/src/CVS/Entries [deleted file]
usrp2/fpga/opencores/spi_boot/doc/src/CVS/Repository [deleted file]
usrp2/fpga/opencores/spi_boot/doc/src/CVS/Root [deleted file]
usrp2/fpga/opencores/spi_boot/doc/src/CVS/Template [deleted file]
usrp2/fpga/opencores/spi_boot/doc/src/architecture.eps [deleted file]
usrp2/fpga/opencores/spi_boot/doc/src/architecture.fig [deleted file]
usrp2/fpga/opencores/spi_boot/doc/src/initialization.eps [deleted file]
usrp2/fpga/opencores/spi_boot/doc/src/initialization.fig [deleted file]
usrp2/fpga/opencores/spi_boot/doc/src/memory_organization.eps [deleted file]
usrp2/fpga/opencores/spi_boot/doc/src/memory_organization.fig [deleted file]
usrp2/fpga/opencores/spi_boot/doc/src/spi_boot.sxw [deleted file]
usrp2/fpga/opencores/spi_boot/doc/src/transfer.eps [deleted file]
usrp2/fpga/opencores/spi_boot/doc/src/transfer.fig [deleted file]
usrp2/fpga/opencores/spi_boot/rtl/CVS/Entries [deleted file]
usrp2/fpga/opencores/spi_boot/rtl/CVS/Repository [deleted file]
usrp2/fpga/opencores/spi_boot/rtl/CVS/Root [deleted file]
usrp2/fpga/opencores/spi_boot/rtl/CVS/Template [deleted file]
usrp2/fpga/opencores/spi_boot/rtl/vhdl/CVS/Entries [deleted file]
usrp2/fpga/opencores/spi_boot/rtl/vhdl/CVS/Repository [deleted file]
usrp2/fpga/opencores/spi_boot/rtl/vhdl/CVS/Root [deleted file]
usrp2/fpga/opencores/spi_boot/rtl/vhdl/CVS/Template [deleted file]
usrp2/fpga/opencores/spi_boot/rtl/vhdl/chip-e.vhd [deleted file]
usrp2/fpga/opencores/spi_boot/rtl/vhdl/chip-full-a.vhd [deleted file]
usrp2/fpga/opencores/spi_boot/rtl/vhdl/chip-full-c.vhd [deleted file]
usrp2/fpga/opencores/spi_boot/rtl/vhdl/chip-minimal-a.vhd [deleted file]
usrp2/fpga/opencores/spi_boot/rtl/vhdl/chip-minimal-c.vhd [deleted file]
usrp2/fpga/opencores/spi_boot/rtl/vhdl/chip-mmc-a.vhd [deleted file]
usrp2/fpga/opencores/spi_boot/rtl/vhdl/chip-mmc-c.vhd [deleted file]
usrp2/fpga/opencores/spi_boot/rtl/vhdl/chip-sd-a.vhd [deleted file]
usrp2/fpga/opencores/spi_boot/rtl/vhdl/chip-sd-c.vhd [deleted file]
usrp2/fpga/opencores/spi_boot/rtl/vhdl/sample/CVS/Entries [deleted file]
usrp2/fpga/opencores/spi_boot/rtl/vhdl/sample/CVS/Repository [deleted file]
usrp2/fpga/opencores/spi_boot/rtl/vhdl/sample/CVS/Root [deleted file]
usrp2/fpga/opencores/spi_boot/rtl/vhdl/sample/CVS/Template [deleted file]
usrp2/fpga/opencores/spi_boot/rtl/vhdl/sample/ram_loader-c.vhd [deleted file]
usrp2/fpga/opencores/spi_boot/rtl/vhdl/sample/ram_loader.vhd [deleted file]
usrp2/fpga/opencores/spi_boot/rtl/vhdl/spi_boot-c.vhd [deleted file]
usrp2/fpga/opencores/spi_boot/rtl/vhdl/spi_boot.vhd [deleted file]
usrp2/fpga/opencores/spi_boot/rtl/vhdl/spi_boot_pack-p.vhd [deleted file]
usrp2/fpga/opencores/spi_boot/rtl/vhdl/spi_counter-c.vhd [deleted file]
usrp2/fpga/opencores/spi_boot/rtl/vhdl/spi_counter.vhd [deleted file]
usrp2/fpga/opencores/spi_boot/sim/CVS/Entries [deleted file]
usrp2/fpga/opencores/spi_boot/sim/CVS/Repository [deleted file]
usrp2/fpga/opencores/spi_boot/sim/CVS/Root [deleted file]
usrp2/fpga/opencores/spi_boot/sim/CVS/Template [deleted file]
usrp2/fpga/opencores/spi_boot/sim/rtl_sim/CVS/Entries [deleted file]
usrp2/fpga/opencores/spi_boot/sim/rtl_sim/CVS/Repository [deleted file]
usrp2/fpga/opencores/spi_boot/sim/rtl_sim/CVS/Root [deleted file]
usrp2/fpga/opencores/spi_boot/sim/rtl_sim/CVS/Template [deleted file]
usrp2/fpga/opencores/spi_boot/sim/rtl_sim/Makefile [deleted file]
usrp2/fpga/opencores/spi_boot/sw/CVS/Entries [deleted file]
usrp2/fpga/opencores/spi_boot/sw/CVS/Repository [deleted file]
usrp2/fpga/opencores/spi_boot/sw/CVS/Root [deleted file]
usrp2/fpga/opencores/spi_boot/sw/CVS/Template [deleted file]
usrp2/fpga/opencores/spi_boot/sw/misc/CVS/Entries [deleted file]
usrp2/fpga/opencores/spi_boot/sw/misc/CVS/Repository [deleted file]
usrp2/fpga/opencores/spi_boot/sw/misc/CVS/Root [deleted file]
usrp2/fpga/opencores/spi_boot/sw/misc/CVS/Template [deleted file]
usrp2/fpga/opencores/spi_boot/sw/misc/bit_reverse.c [deleted file]
usrp2/fpga/opencores/wb_zbt/CVS/Entries [deleted file]
usrp2/fpga/opencores/wb_zbt/CVS/Repository [deleted file]
usrp2/fpga/opencores/wb_zbt/CVS/Root [deleted file]
usrp2/fpga/opencores/wb_zbt/CVS/Template [deleted file]
usrp2/fpga/opencores/wb_zbt/wb_zbt.v [deleted file]
usrp2/fpga/sdr_lib/.gitignore [deleted file]
usrp2/fpga/sdr_lib/HB.sav [deleted file]
usrp2/fpga/sdr_lib/SMALL_HB.sav [deleted file]
usrp2/fpga/sdr_lib/acc.v [deleted file]
usrp2/fpga/sdr_lib/add2.v [deleted file]
usrp2/fpga/sdr_lib/add2_and_round.v [deleted file]
usrp2/fpga/sdr_lib/add2_and_round_reg.v [deleted file]
usrp2/fpga/sdr_lib/add2_reg.v [deleted file]
usrp2/fpga/sdr_lib/cic_dec_shifter.v [deleted file]
usrp2/fpga/sdr_lib/cic_decim.v [deleted file]
usrp2/fpga/sdr_lib/cic_int_shifter.v [deleted file]
usrp2/fpga/sdr_lib/cic_interp.v [deleted file]
usrp2/fpga/sdr_lib/cic_strober.v [deleted file]
usrp2/fpga/sdr_lib/clip.v [deleted file]
usrp2/fpga/sdr_lib/clip_and_round.v [deleted file]
usrp2/fpga/sdr_lib/clip_and_round_reg.v [deleted file]
usrp2/fpga/sdr_lib/clip_reg.v [deleted file]
usrp2/fpga/sdr_lib/cordic.v [deleted file]
usrp2/fpga/sdr_lib/cordic_stage.v [deleted file]
usrp2/fpga/sdr_lib/cordic_z24.v [deleted file]
usrp2/fpga/sdr_lib/ddc.v [deleted file]
usrp2/fpga/sdr_lib/dsp_core_rx.v [deleted file]
usrp2/fpga/sdr_lib/dsp_core_tx.v [deleted file]
usrp2/fpga/sdr_lib/duc.v [deleted file]
usrp2/fpga/sdr_lib/dummy_rx.v [deleted file]
usrp2/fpga/sdr_lib/gen_cordic_consts.py [deleted file]
usrp2/fpga/sdr_lib/halfband_ideal.v [deleted file]
usrp2/fpga/sdr_lib/halfband_tb.v [deleted file]
usrp2/fpga/sdr_lib/hb/acc.v [deleted file]
usrp2/fpga/sdr_lib/hb/coeff_ram.v [deleted file]
usrp2/fpga/sdr_lib/hb/coeff_rom.v [deleted file]
usrp2/fpga/sdr_lib/hb/halfband_decim.v [deleted file]
usrp2/fpga/sdr_lib/hb/halfband_interp.v [deleted file]
usrp2/fpga/sdr_lib/hb/hbd_tb/HBD [deleted file]
usrp2/fpga/sdr_lib/hb/hbd_tb/really_golden [deleted file]
usrp2/fpga/sdr_lib/hb/hbd_tb/regression [deleted file]
usrp2/fpga/sdr_lib/hb/hbd_tb/run_hbd [deleted file]
usrp2/fpga/sdr_lib/hb/hbd_tb/test_hbd.v [deleted file]
usrp2/fpga/sdr_lib/hb/mac.v [deleted file]
usrp2/fpga/sdr_lib/hb/mult.v [deleted file]
usrp2/fpga/sdr_lib/hb/ram16_2port.v [deleted file]
usrp2/fpga/sdr_lib/hb/ram16_2sum.v [deleted file]
usrp2/fpga/sdr_lib/hb/ram32_2sum.v [deleted file]
usrp2/fpga/sdr_lib/hb_dec.v [deleted file]
usrp2/fpga/sdr_lib/hb_dec_tb.v [deleted file]
usrp2/fpga/sdr_lib/hb_interp.v [deleted file]
usrp2/fpga/sdr_lib/hb_interp_tb.v [deleted file]
usrp2/fpga/sdr_lib/hb_tb.v [deleted file]
usrp2/fpga/sdr_lib/input.dat [deleted file]
usrp2/fpga/sdr_lib/integrate.v [deleted file]
usrp2/fpga/sdr_lib/med_hb_int.v [deleted file]
usrp2/fpga/sdr_lib/output.dat [deleted file]
usrp2/fpga/sdr_lib/round.v [deleted file]
usrp2/fpga/sdr_lib/round_reg.v [deleted file]
usrp2/fpga/sdr_lib/rssi.v [deleted file]
usrp2/fpga/sdr_lib/rx_control.v [deleted file]
usrp2/fpga/sdr_lib/rx_dcoffset.v [deleted file]
usrp2/fpga/sdr_lib/rx_dcoffset_tb.v [deleted file]
usrp2/fpga/sdr_lib/sign_extend.v [deleted file]
usrp2/fpga/sdr_lib/small_hb_dec.v [deleted file]
usrp2/fpga/sdr_lib/small_hb_dec_tb.v [deleted file]
usrp2/fpga/sdr_lib/small_hb_int.v [deleted file]
usrp2/fpga/sdr_lib/small_hb_int_tb.v [deleted file]
usrp2/fpga/sdr_lib/tx_control.v [deleted file]
usrp2/fpga/serdes/serdes.v [deleted file]
usrp2/fpga/serdes/serdes_fc_rx.v [deleted file]
usrp2/fpga/serdes/serdes_fc_tx.v [deleted file]
usrp2/fpga/serdes/serdes_rx.v [deleted file]
usrp2/fpga/serdes/serdes_tb.v [deleted file]
usrp2/fpga/serdes/serdes_tx.v [deleted file]
usrp2/fpga/simple_gemac/.gitignore [deleted file]
usrp2/fpga/simple_gemac/address_filter.v [deleted file]
usrp2/fpga/simple_gemac/crc.v [deleted file]
usrp2/fpga/simple_gemac/delay_line.v [deleted file]
usrp2/fpga/simple_gemac/eth_tasks.v [deleted file]
usrp2/fpga/simple_gemac/eth_tasks_f36.v [deleted file]
usrp2/fpga/simple_gemac/flow_ctrl_rx.v [deleted file]
usrp2/fpga/simple_gemac/flow_ctrl_tx.v [deleted file]
usrp2/fpga/simple_gemac/ll8_shortfifo.v [deleted file]
usrp2/fpga/simple_gemac/ll8_to_txmac.v [deleted file]
usrp2/fpga/simple_gemac/miim/eth_clockgen.v [deleted file]
usrp2/fpga/simple_gemac/miim/eth_miim.v [deleted file]
usrp2/fpga/simple_gemac/miim/eth_outputcontrol.v [deleted file]
usrp2/fpga/simple_gemac/miim/eth_shiftreg.v [deleted file]
usrp2/fpga/simple_gemac/rxmac_to_ll8.v [deleted file]
usrp2/fpga/simple_gemac/simple_gemac.v [deleted file]
usrp2/fpga/simple_gemac/simple_gemac_rx.v [deleted file]
usrp2/fpga/simple_gemac/simple_gemac_tb.v [deleted file]
usrp2/fpga/simple_gemac/simple_gemac_tx.v [deleted file]
usrp2/fpga/simple_gemac/simple_gemac_wb.v [deleted file]
usrp2/fpga/simple_gemac/simple_gemac_wrapper.build [deleted file]
usrp2/fpga/simple_gemac/simple_gemac_wrapper.v [deleted file]
usrp2/fpga/simple_gemac/simple_gemac_wrapper_f36_tb.v [deleted file]
usrp2/fpga/simple_gemac/simple_gemac_wrapper_tb.v [deleted file]
usrp2/fpga/simple_gemac/test_packet.mem [deleted file]
usrp2/fpga/testbench/.gitignore [deleted file]
usrp2/fpga/testbench/BOOTSTRAP.sav [deleted file]
usrp2/fpga/testbench/Makefile [deleted file]
usrp2/fpga/testbench/PAUSE.sav [deleted file]
usrp2/fpga/testbench/README [deleted file]
usrp2/fpga/testbench/SERDES.sav [deleted file]
usrp2/fpga/testbench/U2_SIM.sav [deleted file]
usrp2/fpga/testbench/cmdfile [deleted file]
usrp2/fpga/timing/.gitignore [deleted file]
usrp2/fpga/timing/time_64bit.v [deleted file]
usrp2/fpga/timing/time_receiver.v [deleted file]
usrp2/fpga/timing/time_sender.v [deleted file]
usrp2/fpga/timing/time_sync.v [deleted file]
usrp2/fpga/timing/time_transfer_tb.v [deleted file]
usrp2/fpga/timing/timer.v [deleted file]
usrp2/fpga/top/.gitignore [deleted file]
usrp2/fpga/top/eth_test/.gitignore [deleted file]
usrp2/fpga/top/eth_test/eth_sim_top.v [deleted file]
usrp2/fpga/top/eth_test/eth_tb.v [deleted file]
usrp2/fpga/top/single_u2_sim/single_u2_sim.v [deleted file]
usrp2/fpga/top/tcl/ise_helper.tcl [deleted file]
usrp2/fpga/top/u2_core/.gitignore [deleted file]
usrp2/fpga/top/u2_core/u2_core.v [deleted file]
usrp2/fpga/top/u2_rev1/.gitignore [deleted file]
usrp2/fpga/top/u2_rev1/Makefile [deleted file]
usrp2/fpga/top/u2_rev1/u2_fpga.ise [deleted file]
usrp2/fpga/top/u2_rev1/u2_fpga.ucf [deleted file]
usrp2/fpga/top/u2_rev1/u2_fpga_top.prj [deleted file]
usrp2/fpga/top/u2_rev1/u2_fpga_top.v [deleted file]
usrp2/fpga/top/u2_rev2/.gitignore [deleted file]
usrp2/fpga/top/u2_rev2/Makefile [deleted file]
usrp2/fpga/top/u2_rev2/u2_rev2.ucf [deleted file]
usrp2/fpga/top/u2_rev2/u2_rev2.v [deleted file]
usrp2/fpga/top/u2_rev3/.gitignore [deleted file]
usrp2/fpga/top/u2_rev3/Makefile [deleted file]
usrp2/fpga/top/u2_rev3/u2_rev3.ucf [deleted file]
usrp2/fpga/top/u2_rev3/u2_rev3.v [deleted file]
usrp2/fpga/top/u2_rev3_2rx_iad/Makefile [deleted file]
usrp2/fpga/top/u2_rev3_2rx_iad/README [deleted file]
usrp2/fpga/top/u2_rev3_2rx_iad/cmdfile [deleted file]
usrp2/fpga/top/u2_rev3_2rx_iad/dsp_core_rx.v [deleted file]
usrp2/fpga/top/u2_rev3_2rx_iad/dsp_core_tb.sav [deleted file]
usrp2/fpga/top/u2_rev3_2rx_iad/dsp_core_tb.v [deleted file]
usrp2/fpga/top/u2_rev3_2rx_iad/impulse.v [deleted file]
usrp2/fpga/top/u2_rev3_2rx_iad/u2_core.v [deleted file]
usrp2/fpga/top/u2_rev3_2rx_iad/wave.sh [deleted file]
usrp2/fpga/top/u2_rev3_iad/.gitignore [deleted file]
usrp2/fpga/top/u2_rev3_iad/Makefile [deleted file]
usrp2/fpga/top/u2_rev3_iad/cmdfile [deleted file]
usrp2/fpga/top/u2_rev3_iad/dsp_core_rx.v [deleted file]
usrp2/fpga/top/u2_rev3_iad/dsp_core_tb.sav [deleted file]
usrp2/fpga/top/u2_rev3_iad/dsp_core_tb.v [deleted file]
usrp2/fpga/top/u2_rev3_iad/impulse.v [deleted file]
usrp2/fpga/top/u2_rev3_iad/wave.sh [deleted file]
usrp2/fpga/top/u2plus/u2plus.ucf [deleted file]
usrp2/fpga/top/u2plus/u2plus.v [deleted file]