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updated wiki url
[debian/gnuradio]
/
usrp2
/
fpga
/
sdr_lib
/
add2_and_round.v
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module add2_and_round
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#(parameter WIDTH=16)
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(input [WIDTH-1:0] in1,
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input [WIDTH-1:0] in2,
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output [WIDTH-1:0] sum);
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wire [WIDTH:0] sum_int = {in1[WIDTH-1],in1} + {in2[WIDTH-1],in2};
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assign sum = sum_int[WIDTH:1] + (sum_int[WIDTH] & sum_int[0]);
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endmodule // add2_and_round