1 // Model of FIFO in Altera
3 module fifo( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
4 rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
7 parameter depth = 1024;
8 parameter addr_bits = 10;
10 //`define rd_req 0; // Set this to 0 for rd_ack, 1 for rd_req
12 input [width-1:0] data;
21 output reg [addr_bits-1:0] rdusedw;
24 output reg [addr_bits-1:0] wrusedw;
26 reg [width-1:0] mem [0:depth-1];
27 reg [addr_bits-1:0] rdptr;
28 reg [addr_bits-1:0] wrptr;
42 for(i=0;i<depth;i=i+1)
46 always @(posedge wrclk)
50 mem[wrptr] <= #1 data;
53 always @(posedge rdclk)
64 assign q = mem[rdptr];
68 always @(posedge wrclk)
69 wrusedw <= #1 wrptr - rdptr;
71 always @(posedge rdclk)
72 rdusedw <= #1 wrptr - rdptr;
74 assign wrempty = (wrusedw == 0);
75 assign wrfull = (wrusedw == depth-1);
77 assign rdempty = (rdusedw == 0);
78 assign rdfull = (rdusedw == depth-1);