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   1
   2 module srl
   3   #(parameter WIDTH=18)
   4     (input clk,
   5      input write,
   6      input [WIDTH-1:0] in,
   7      input [3:0] addr,
   8      output [WIDTH-1:0] out);
   9
  10    genvar               i;
  11    generate
  12       for (i=0;i<WIDTH;i=i+1)
  13         begin : gen_srl
  14            SRL16E
  15              srl16e(.Q(out[i]),
  16                     .A0(addr[0]),.A1(addr[1]),.A2(addr[2]),.A3(addr[3]),
  17                     .CE(write),.CLK(clk),.D(in[i]));
  18         end
  19    endgenerate
  20
  21 endmodule // srl