-#define XT_PC_REG_NUM_BASE (176)
-#define XT_SW_BREAKPOINTS_MAX_NUM 32
-
-const struct xtensa_reg_desc xtensa_regs[XT_NUM_REGS] = {
- { "pc", XT_PC_REG_NUM_BASE /*+XT_DEBUGLEVEL*/, XT_REG_SPECIAL, 0 }, /* actually epc[debuglevel] */
- { "ar0", 0x00, XT_REG_GENERAL, 0 },
- { "ar1", 0x01, XT_REG_GENERAL, 0 },
- { "ar2", 0x02, XT_REG_GENERAL, 0 },
- { "ar3", 0x03, XT_REG_GENERAL, 0 },
- { "ar4", 0x04, XT_REG_GENERAL, 0 },
- { "ar5", 0x05, XT_REG_GENERAL, 0 },
- { "ar6", 0x06, XT_REG_GENERAL, 0 },
- { "ar7", 0x07, XT_REG_GENERAL, 0 },
- { "ar8", 0x08, XT_REG_GENERAL, 0 },
- { "ar9", 0x09, XT_REG_GENERAL, 0 },
- { "ar10", 0x0A, XT_REG_GENERAL, 0 },
- { "ar11", 0x0B, XT_REG_GENERAL, 0 },
- { "ar12", 0x0C, XT_REG_GENERAL, 0 },
- { "ar13", 0x0D, XT_REG_GENERAL, 0 },
- { "ar14", 0x0E, XT_REG_GENERAL, 0 },
- { "ar15", 0x0F, XT_REG_GENERAL, 0 },
- { "ar16", 0x10, XT_REG_GENERAL, 0 },
- { "ar17", 0x11, XT_REG_GENERAL, 0 },
- { "ar18", 0x12, XT_REG_GENERAL, 0 },
- { "ar19", 0x13, XT_REG_GENERAL, 0 },
- { "ar20", 0x14, XT_REG_GENERAL, 0 },
- { "ar21", 0x15, XT_REG_GENERAL, 0 },
- { "ar22", 0x16, XT_REG_GENERAL, 0 },
- { "ar23", 0x17, XT_REG_GENERAL, 0 },
- { "ar24", 0x18, XT_REG_GENERAL, 0 },
- { "ar25", 0x19, XT_REG_GENERAL, 0 },
- { "ar26", 0x1A, XT_REG_GENERAL, 0 },
- { "ar27", 0x1B, XT_REG_GENERAL, 0 },
- { "ar28", 0x1C, XT_REG_GENERAL, 0 },
- { "ar29", 0x1D, XT_REG_GENERAL, 0 },
- { "ar30", 0x1E, XT_REG_GENERAL, 0 },
- { "ar31", 0x1F, XT_REG_GENERAL, 0 },
- { "ar32", 0x20, XT_REG_GENERAL, 0 },
- { "ar33", 0x21, XT_REG_GENERAL, 0 },
- { "ar34", 0x22, XT_REG_GENERAL, 0 },
- { "ar35", 0x23, XT_REG_GENERAL, 0 },
- { "ar36", 0x24, XT_REG_GENERAL, 0 },
- { "ar37", 0x25, XT_REG_GENERAL, 0 },
- { "ar38", 0x26, XT_REG_GENERAL, 0 },
- { "ar39", 0x27, XT_REG_GENERAL, 0 },
- { "ar40", 0x28, XT_REG_GENERAL, 0 },
- { "ar41", 0x29, XT_REG_GENERAL, 0 },
- { "ar42", 0x2A, XT_REG_GENERAL, 0 },
- { "ar43", 0x2B, XT_REG_GENERAL, 0 },
- { "ar44", 0x2C, XT_REG_GENERAL, 0 },
- { "ar45", 0x2D, XT_REG_GENERAL, 0 },
- { "ar46", 0x2E, XT_REG_GENERAL, 0 },
- { "ar47", 0x2F, XT_REG_GENERAL, 0 },
- { "ar48", 0x30, XT_REG_GENERAL, 0 },
- { "ar49", 0x31, XT_REG_GENERAL, 0 },
- { "ar50", 0x32, XT_REG_GENERAL, 0 },
- { "ar51", 0x33, XT_REG_GENERAL, 0 },
- { "ar52", 0x34, XT_REG_GENERAL, 0 },
- { "ar53", 0x35, XT_REG_GENERAL, 0 },
- { "ar54", 0x36, XT_REG_GENERAL, 0 },
- { "ar55", 0x37, XT_REG_GENERAL, 0 },
- { "ar56", 0x38, XT_REG_GENERAL, 0 },
- { "ar57", 0x39, XT_REG_GENERAL, 0 },
- { "ar58", 0x3A, XT_REG_GENERAL, 0 },
- { "ar59", 0x3B, XT_REG_GENERAL, 0 },
- { "ar60", 0x3C, XT_REG_GENERAL, 0 },
- { "ar61", 0x3D, XT_REG_GENERAL, 0 },
- { "ar62", 0x3E, XT_REG_GENERAL, 0 },
- { "ar63", 0x3F, XT_REG_GENERAL, 0 },
- { "lbeg", 0x00, XT_REG_SPECIAL, 0 },
- { "lend", 0x01, XT_REG_SPECIAL, 0 },
- { "lcount", 0x02, XT_REG_SPECIAL, 0 },
- { "sar", 0x03, XT_REG_SPECIAL, 0 },
- { "windowbase", 0x48, XT_REG_SPECIAL, 0 },
- { "windowstart", 0x49, XT_REG_SPECIAL, 0 },
- { "configid0", 0xB0, XT_REG_SPECIAL, 0 },
- { "configid1", 0xD0, XT_REG_SPECIAL, 0 },
- { "ps", 0xC6, XT_REG_SPECIAL, 0 }, /* actually EPS[debuglevel] */
- { "threadptr", 0xE7, XT_REG_USER, 0 },
- { "br", 0x04, XT_REG_SPECIAL, 0 },
- { "scompare1", 0x0C, XT_REG_SPECIAL, 0 },
- { "acclo", 0x10, XT_REG_SPECIAL, 0 },
- { "acchi", 0x11, XT_REG_SPECIAL, 0 },
- { "m0", 0x20, XT_REG_SPECIAL, 0 },
- { "m1", 0x21, XT_REG_SPECIAL, 0 },
- { "m2", 0x22, XT_REG_SPECIAL, 0 },
- { "m3", 0x23, XT_REG_SPECIAL, 0 },
- { "f0", 0x00, XT_REG_FR, XT_REGF_COPROC0 },
- { "f1", 0x01, XT_REG_FR, XT_REGF_COPROC0 },
- { "f2", 0x02, XT_REG_FR, XT_REGF_COPROC0 },
- { "f3", 0x03, XT_REG_FR, XT_REGF_COPROC0 },
- { "f4", 0x04, XT_REG_FR, XT_REGF_COPROC0 },
- { "f5", 0x05, XT_REG_FR, XT_REGF_COPROC0 },
- { "f6", 0x06, XT_REG_FR, XT_REGF_COPROC0 },
- { "f7", 0x07, XT_REG_FR, XT_REGF_COPROC0 },
- { "f8", 0x08, XT_REG_FR, XT_REGF_COPROC0 },
- { "f9", 0x09, XT_REG_FR, XT_REGF_COPROC0 },
- { "f10", 0x0A, XT_REG_FR, XT_REGF_COPROC0 },
- { "f11", 0x0B, XT_REG_FR, XT_REGF_COPROC0 },
- { "f12", 0x0C, XT_REG_FR, XT_REGF_COPROC0 },
- { "f13", 0x0D, XT_REG_FR, XT_REGF_COPROC0 },
- { "f14", 0x0E, XT_REG_FR, XT_REGF_COPROC0 },
- { "f15", 0x0F, XT_REG_FR, XT_REGF_COPROC0 },
- { "fcr", 0xE8, XT_REG_USER, XT_REGF_COPROC0 },
- { "fsr", 0xE9, XT_REG_USER, XT_REGF_COPROC0 },
- { "mmid", 0x59, XT_REG_SPECIAL, XT_REGF_NOREAD },
- { "ibreakenable", 0x60, XT_REG_SPECIAL, 0 },
- { "memctl", 0x61, XT_REG_SPECIAL, 0 },
- { "atomctl", 0x63, XT_REG_SPECIAL, 0 },
- { "ibreaka0", 0x80, XT_REG_SPECIAL, 0 },
- { "ibreaka1", 0x81, XT_REG_SPECIAL, 0 },
- { "dbreaka0", 0x90, XT_REG_SPECIAL, 0 },
- { "dbreaka1", 0x91, XT_REG_SPECIAL, 0 },
- { "dbreakc0", 0xA0, XT_REG_SPECIAL, 0 },
- { "dbreakc1", 0xA1, XT_REG_SPECIAL, 0 },
- { "epc1", 0xB1, XT_REG_SPECIAL, 0 },
- { "epc2", 0xB2, XT_REG_SPECIAL, 0 },
- { "epc3", 0xB3, XT_REG_SPECIAL, 0 },
- { "epc4", 0xB4, XT_REG_SPECIAL, 0 },
- { "epc5", 0xB5, XT_REG_SPECIAL, 0 },
- { "epc6", 0xB6, XT_REG_SPECIAL, 0 },
- { "epc7", 0xB7, XT_REG_SPECIAL, 0 },
- { "depc", 0xC0, XT_REG_SPECIAL, 0 },
- { "eps2", 0xC2, XT_REG_SPECIAL, 0 },
- { "eps3", 0xC3, XT_REG_SPECIAL, 0 },
- { "eps4", 0xC4, XT_REG_SPECIAL, 0 },
- { "eps5", 0xC5, XT_REG_SPECIAL, 0 },
- { "eps6", 0xC6, XT_REG_SPECIAL, 0 },
- { "eps7", 0xC7, XT_REG_SPECIAL, 0 },
- { "excsave1", 0xD1, XT_REG_SPECIAL, 0 },
- { "excsave2", 0xD2, XT_REG_SPECIAL, 0 },
- { "excsave3", 0xD3, XT_REG_SPECIAL, 0 },
- { "excsave4", 0xD4, XT_REG_SPECIAL, 0 },
- { "excsave5", 0xD5, XT_REG_SPECIAL, 0 },
- { "excsave6", 0xD6, XT_REG_SPECIAL, 0 },
- { "excsave7", 0xD7, XT_REG_SPECIAL, 0 },
- { "cpenable", 0xE0, XT_REG_SPECIAL, 0 },
- { "interrupt", 0xE2, XT_REG_SPECIAL, 0 },
- { "intset", 0xE2, XT_REG_SPECIAL, XT_REGF_NOREAD },
- { "intclear", 0xE3, XT_REG_SPECIAL, XT_REGF_NOREAD },
- { "intenable", 0xE4, XT_REG_SPECIAL, 0 },
- { "vecbase", 0xE7, XT_REG_SPECIAL, 0 },
- { "exccause", 0xE8, XT_REG_SPECIAL, 0 },
- { "debugcause", 0xE9, XT_REG_SPECIAL, 0 },
- { "ccount", 0xEA, XT_REG_SPECIAL, 0 },
- { "prid", 0xEB, XT_REG_SPECIAL, 0 },
- { "icount", 0xEC, XT_REG_SPECIAL, 0 },
- { "icountlevel", 0xED, XT_REG_SPECIAL, 0 },
- { "excvaddr", 0xEE, XT_REG_SPECIAL, 0 },
- { "ccompare0", 0xF0, XT_REG_SPECIAL, 0 },
- { "ccompare1", 0xF1, XT_REG_SPECIAL, 0 },
- { "ccompare2", 0xF2, XT_REG_SPECIAL, 0 },
- { "misc0", 0xF4, XT_REG_SPECIAL, 0 },
- { "misc1", 0xF5, XT_REG_SPECIAL, 0 },
- { "misc2", 0xF6, XT_REG_SPECIAL, 0 },
- { "misc3", 0xF7, XT_REG_SPECIAL, 0 },
- { "litbase", 0x05, XT_REG_SPECIAL, 0 },
- { "ptevaddr", 0x53, XT_REG_SPECIAL, 0 },
- { "rasid", 0x5A, XT_REG_SPECIAL, 0 },
- { "itlbcfg", 0x5B, XT_REG_SPECIAL, 0 },
- { "dtlbcfg", 0x5C, XT_REG_SPECIAL, 0 },
- { "mepc", 0x6A, XT_REG_SPECIAL, 0 },
- { "meps", 0x6B, XT_REG_SPECIAL, 0 },
- { "mesave", 0x6C, XT_REG_SPECIAL, 0 },
- { "mesr", 0x6D, XT_REG_SPECIAL, 0 },
- { "mecr", 0x6E, XT_REG_SPECIAL, 0 },
- { "mevaddr", 0x6F, XT_REG_SPECIAL, 0 },
- { "a0", XT_REG_IDX_AR0, XT_REG_RELGEN, 0 }, /* WARNING: For these registers, regnum points to the */
- { "a1", XT_REG_IDX_AR1, XT_REG_RELGEN, 0 }, /* index of the corresponding ARxregisters, NOT to */
- { "a2", XT_REG_IDX_AR2, XT_REG_RELGEN, 0 }, /* the processor register number! */
- { "a3", XT_REG_IDX_AR3, XT_REG_RELGEN, 0 },
- { "a4", XT_REG_IDX_AR4, XT_REG_RELGEN, 0 },
- { "a5", XT_REG_IDX_AR5, XT_REG_RELGEN, 0 },
- { "a6", XT_REG_IDX_AR6, XT_REG_RELGEN, 0 },
- { "a7", XT_REG_IDX_AR7, XT_REG_RELGEN, 0 },
- { "a8", XT_REG_IDX_AR8, XT_REG_RELGEN, 0 },
- { "a9", XT_REG_IDX_AR9, XT_REG_RELGEN, 0 },
- { "a10", XT_REG_IDX_AR10, XT_REG_RELGEN, 0 },
- { "a11", XT_REG_IDX_AR11, XT_REG_RELGEN, 0 },
- { "a12", XT_REG_IDX_AR12, XT_REG_RELGEN, 0 },
- { "a13", XT_REG_IDX_AR13, XT_REG_RELGEN, 0 },
- { "a14", XT_REG_IDX_AR14, XT_REG_RELGEN, 0 },
- { "a15", XT_REG_IDX_AR15, XT_REG_RELGEN, 0 },
-
- { "pwrctl", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD },
- { "pwrstat", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD },
- { "eristat", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD },
- { "cs_itctrl", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD },
- { "cs_claimset", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD },
- { "cs_claimclr", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD },
- { "cs_lockaccess", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD },
- { "cs_lockstatus", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD },
- { "cs_authstatus", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD },
- { "fault_info", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD },
- { "trax_id", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD },
- { "trax_ctrl", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD },
- { "trax_stat", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD },
- { "trax_data", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD },
- { "trax_addr", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD },
- { "trax_pctrigger", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD },
- { "trax_pcmatch", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD },
- { "trax_delay", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD },
- { "trax_memstart", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD },
- { "trax_memend", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD },
- { "pmg", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD },
- { "pmoc", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD },
- { "pm0", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD },
- { "pm1", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD },
- { "pmctrl0", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD },
- { "pmctrl1", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD },
- { "pmstat0", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD },
- { "pmstat1", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD },
- { "ocd_id", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD },
- { "ocd_dcrclr", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD },
- { "ocd_dcrset", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD },
- { "ocd_dsr", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD },
- { "ddr", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD },
+#define XT_PS_REG_NUM_BASE (0xc0U) /* (EPS2 - 2), for adding DBGLEVEL */
+#define XT_PC_REG_NUM_BASE (0xb0U) /* (EPC1 - 1), for adding DBGLEVEL */
+#define XT_PC_REG_NUM_VIRTUAL (0xffU) /* Marker for computing PC (EPC[DBGLEVEL) */
+#define XT_PC_DBREG_NUM_BASE (0x20U) /* External (i.e., GDB) access */
+
+#define XT_SW_BREAKPOINTS_MAX_NUM 32
+#define XT_HW_IBREAK_MAX_NUM 2
+#define XT_HW_DBREAK_MAX_NUM 2
+
+struct xtensa_reg_desc xtensa_regs[XT_NUM_REGS] = {
+ XT_MK_REG_DESC("pc", XT_PC_REG_NUM_VIRTUAL, XT_REG_SPECIAL, 0),
+ XT_MK_REG_DESC("ar0", 0x00, XT_REG_GENERAL, 0),
+ XT_MK_REG_DESC("ar1", 0x01, XT_REG_GENERAL, 0),
+ XT_MK_REG_DESC("ar2", 0x02, XT_REG_GENERAL, 0),
+ XT_MK_REG_DESC("ar3", 0x03, XT_REG_GENERAL, 0),
+ XT_MK_REG_DESC("ar4", 0x04, XT_REG_GENERAL, 0),
+ XT_MK_REG_DESC("ar5", 0x05, XT_REG_GENERAL, 0),
+ XT_MK_REG_DESC("ar6", 0x06, XT_REG_GENERAL, 0),
+ XT_MK_REG_DESC("ar7", 0x07, XT_REG_GENERAL, 0),
+ XT_MK_REG_DESC("ar8", 0x08, XT_REG_GENERAL, 0),
+ XT_MK_REG_DESC("ar9", 0x09, XT_REG_GENERAL, 0),
+ XT_MK_REG_DESC("ar10", 0x0A, XT_REG_GENERAL, 0),
+ XT_MK_REG_DESC("ar11", 0x0B, XT_REG_GENERAL, 0),
+ XT_MK_REG_DESC("ar12", 0x0C, XT_REG_GENERAL, 0),
+ XT_MK_REG_DESC("ar13", 0x0D, XT_REG_GENERAL, 0),
+ XT_MK_REG_DESC("ar14", 0x0E, XT_REG_GENERAL, 0),
+ XT_MK_REG_DESC("ar15", 0x0F, XT_REG_GENERAL, 0),
+ XT_MK_REG_DESC("ar16", 0x10, XT_REG_GENERAL, 0),
+ XT_MK_REG_DESC("ar17", 0x11, XT_REG_GENERAL, 0),
+ XT_MK_REG_DESC("ar18", 0x12, XT_REG_GENERAL, 0),
+ XT_MK_REG_DESC("ar19", 0x13, XT_REG_GENERAL, 0),
+ XT_MK_REG_DESC("ar20", 0x14, XT_REG_GENERAL, 0),
+ XT_MK_REG_DESC("ar21", 0x15, XT_REG_GENERAL, 0),
+ XT_MK_REG_DESC("ar22", 0x16, XT_REG_GENERAL, 0),
+ XT_MK_REG_DESC("ar23", 0x17, XT_REG_GENERAL, 0),
+ XT_MK_REG_DESC("ar24", 0x18, XT_REG_GENERAL, 0),
+ XT_MK_REG_DESC("ar25", 0x19, XT_REG_GENERAL, 0),
+ XT_MK_REG_DESC("ar26", 0x1A, XT_REG_GENERAL, 0),
+ XT_MK_REG_DESC("ar27", 0x1B, XT_REG_GENERAL, 0),
+ XT_MK_REG_DESC("ar28", 0x1C, XT_REG_GENERAL, 0),
+ XT_MK_REG_DESC("ar29", 0x1D, XT_REG_GENERAL, 0),
+ XT_MK_REG_DESC("ar30", 0x1E, XT_REG_GENERAL, 0),
+ XT_MK_REG_DESC("ar31", 0x1F, XT_REG_GENERAL, 0),
+ XT_MK_REG_DESC("ar32", 0x20, XT_REG_GENERAL, 0),
+ XT_MK_REG_DESC("ar33", 0x21, XT_REG_GENERAL, 0),
+ XT_MK_REG_DESC("ar34", 0x22, XT_REG_GENERAL, 0),
+ XT_MK_REG_DESC("ar35", 0x23, XT_REG_GENERAL, 0),
+ XT_MK_REG_DESC("ar36", 0x24, XT_REG_GENERAL, 0),
+ XT_MK_REG_DESC("ar37", 0x25, XT_REG_GENERAL, 0),
+ XT_MK_REG_DESC("ar38", 0x26, XT_REG_GENERAL, 0),
+ XT_MK_REG_DESC("ar39", 0x27, XT_REG_GENERAL, 0),
+ XT_MK_REG_DESC("ar40", 0x28, XT_REG_GENERAL, 0),
+ XT_MK_REG_DESC("ar41", 0x29, XT_REG_GENERAL, 0),
+ XT_MK_REG_DESC("ar42", 0x2A, XT_REG_GENERAL, 0),
+ XT_MK_REG_DESC("ar43", 0x2B, XT_REG_GENERAL, 0),
+ XT_MK_REG_DESC("ar44", 0x2C, XT_REG_GENERAL, 0),
+ XT_MK_REG_DESC("ar45", 0x2D, XT_REG_GENERAL, 0),
+ XT_MK_REG_DESC("ar46", 0x2E, XT_REG_GENERAL, 0),
+ XT_MK_REG_DESC("ar47", 0x2F, XT_REG_GENERAL, 0),
+ XT_MK_REG_DESC("ar48", 0x30, XT_REG_GENERAL, 0),
+ XT_MK_REG_DESC("ar49", 0x31, XT_REG_GENERAL, 0),
+ XT_MK_REG_DESC("ar50", 0x32, XT_REG_GENERAL, 0),
+ XT_MK_REG_DESC("ar51", 0x33, XT_REG_GENERAL, 0),
+ XT_MK_REG_DESC("ar52", 0x34, XT_REG_GENERAL, 0),
+ XT_MK_REG_DESC("ar53", 0x35, XT_REG_GENERAL, 0),
+ XT_MK_REG_DESC("ar54", 0x36, XT_REG_GENERAL, 0),
+ XT_MK_REG_DESC("ar55", 0x37, XT_REG_GENERAL, 0),
+ XT_MK_REG_DESC("ar56", 0x38, XT_REG_GENERAL, 0),
+ XT_MK_REG_DESC("ar57", 0x39, XT_REG_GENERAL, 0),
+ XT_MK_REG_DESC("ar58", 0x3A, XT_REG_GENERAL, 0),
+ XT_MK_REG_DESC("ar59", 0x3B, XT_REG_GENERAL, 0),
+ XT_MK_REG_DESC("ar60", 0x3C, XT_REG_GENERAL, 0),
+ XT_MK_REG_DESC("ar61", 0x3D, XT_REG_GENERAL, 0),
+ XT_MK_REG_DESC("ar62", 0x3E, XT_REG_GENERAL, 0),
+ XT_MK_REG_DESC("ar63", 0x3F, XT_REG_GENERAL, 0),
+ XT_MK_REG_DESC("windowbase", 0x48, XT_REG_SPECIAL, 0),
+ XT_MK_REG_DESC("windowstart", 0x49, XT_REG_SPECIAL, 0),
+ XT_MK_REG_DESC("ps", 0xE6, XT_REG_SPECIAL, 0), /* PS (not mapped through EPS[]) */
+ XT_MK_REG_DESC("ibreakenable", 0x60, XT_REG_SPECIAL, 0),
+ XT_MK_REG_DESC("ddr", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD),
+ XT_MK_REG_DESC("ibreaka0", 0x80, XT_REG_SPECIAL, 0),
+ XT_MK_REG_DESC("ibreaka1", 0x81, XT_REG_SPECIAL, 0),
+ XT_MK_REG_DESC("dbreaka0", 0x90, XT_REG_SPECIAL, 0),
+ XT_MK_REG_DESC("dbreaka1", 0x91, XT_REG_SPECIAL, 0),
+ XT_MK_REG_DESC("dbreakc0", 0xA0, XT_REG_SPECIAL, 0),
+ XT_MK_REG_DESC("dbreakc1", 0xA1, XT_REG_SPECIAL, 0),
+ XT_MK_REG_DESC("cpenable", 0xE0, XT_REG_SPECIAL, 0),
+ XT_MK_REG_DESC("exccause", 0xE8, XT_REG_SPECIAL, 0),
+ XT_MK_REG_DESC("debugcause", 0xE9, XT_REG_SPECIAL, 0),
+ XT_MK_REG_DESC("icount", 0xEC, XT_REG_SPECIAL, 0),
+ XT_MK_REG_DESC("icountlevel", 0xED, XT_REG_SPECIAL, 0),
+
+ /* WARNING: For these registers, regnum points to the
+ * index of the corresponding ARx registers, NOT to
+ * the processor register number! */
+ XT_MK_REG_DESC("a0", XT_REG_IDX_AR0, XT_REG_RELGEN, 0),
+ XT_MK_REG_DESC("a1", XT_REG_IDX_AR1, XT_REG_RELGEN, 0),
+ XT_MK_REG_DESC("a2", XT_REG_IDX_AR2, XT_REG_RELGEN, 0),
+ XT_MK_REG_DESC("a3", XT_REG_IDX_AR3, XT_REG_RELGEN, 0),
+ XT_MK_REG_DESC("a4", XT_REG_IDX_AR4, XT_REG_RELGEN, 0),
+ XT_MK_REG_DESC("a5", XT_REG_IDX_AR5, XT_REG_RELGEN, 0),
+ XT_MK_REG_DESC("a6", XT_REG_IDX_AR6, XT_REG_RELGEN, 0),
+ XT_MK_REG_DESC("a7", XT_REG_IDX_AR7, XT_REG_RELGEN, 0),
+ XT_MK_REG_DESC("a8", XT_REG_IDX_AR8, XT_REG_RELGEN, 0),
+ XT_MK_REG_DESC("a9", XT_REG_IDX_AR9, XT_REG_RELGEN, 0),
+ XT_MK_REG_DESC("a10", XT_REG_IDX_AR10, XT_REG_RELGEN, 0),
+ XT_MK_REG_DESC("a11", XT_REG_IDX_AR11, XT_REG_RELGEN, 0),
+ XT_MK_REG_DESC("a12", XT_REG_IDX_AR12, XT_REG_RELGEN, 0),
+ XT_MK_REG_DESC("a13", XT_REG_IDX_AR13, XT_REG_RELGEN, 0),
+ XT_MK_REG_DESC("a14", XT_REG_IDX_AR14, XT_REG_RELGEN, 0),
+ XT_MK_REG_DESC("a15", XT_REG_IDX_AR15, XT_REG_RELGEN, 0),