1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 /***************************************************************************
4 * Generic Xtensa target API for OpenOCD *
5 * Copyright (C) 2016-2019 Espressif Systems Ltd. *
6 * Author: Angus Gratton gus@projectgus.com *
7 ***************************************************************************/
9 #ifndef OPENOCD_TARGET_XTENSA_REGS_H
10 #define OPENOCD_TARGET_XTENSA_REGS_H
84 XT_REG_IDX_WINDOWBASE,
85 XT_REG_IDX_WINDOWSTART,
117 XT_REG_IDX_IBREAKENABLE,
148 XT_REG_IDX_INTERRUPT,
151 XT_REG_IDX_INTENABLE,
154 XT_REG_IDX_DEBUGCAUSE,
158 XT_REG_IDX_ICOUNTLEVEL,
160 XT_REG_IDX_CCOMPARE0,
161 XT_REG_IDX_CCOMPARE1,
162 XT_REG_IDX_CCOMPARE2,
197 XT_REG_IDX_CS_ITCTRL,
198 XT_REG_IDX_CS_CLAIMSET,
199 XT_REG_IDX_CS_CLAIMCLR,
200 XT_REG_IDX_CS_LOCKACCESS,
201 XT_REG_IDX_CS_LOCKSTATUS,
202 XT_REG_IDX_CS_AUTHSTATUS,
203 XT_REG_IDX_FAULT_INFO,
205 XT_REG_IDX_TRAX_CTRL,
206 XT_REG_IDX_TRAX_STAT,
207 XT_REG_IDX_TRAX_DATA,
208 XT_REG_IDX_TRAX_ADDR,
209 XT_REG_IDX_TRAX_PCTRIGGER,
210 XT_REG_IDX_TRAX_PCMATCH,
211 XT_REG_IDX_TRAX_DELAY,
212 XT_REG_IDX_TRAX_MEMSTART,
213 XT_REG_IDX_TRAX_MEMEND,
223 XT_REG_IDX_OCD_DCRCLR,
224 XT_REG_IDX_OCD_DCRSET,
228 /* chip-specific user registers go after ISA-defined ones */
229 XT_USR_REG_START = XT_NUM_REGS
232 typedef uint32_t xtensa_reg_val_t;
234 enum xtensa_reg_type {
235 XT_REG_GENERAL = 0, /* General-purpose register; part of the windowed register set */
236 XT_REG_USER = 1, /* User register, needs RUR to read */
237 XT_REG_SPECIAL = 2, /* Special register, needs RSR to read */
238 XT_REG_DEBUG = 3, /* Register used for the debug interface. Don't mess with this. */
239 XT_REG_RELGEN = 4, /* Relative general address. Points to the absolute addresses plus the window
241 XT_REG_FR = 5, /* Floating-point register */
244 enum xtensa_reg_flags {
245 XT_REGF_NOREAD = 0x01, /* Register is write-only */
246 XT_REGF_COPROC0 = 0x02 /* Can't be read if coproc0 isn't enabled */
249 struct xtensa_reg_desc {
251 unsigned int reg_num; /* ISA register num (meaning depends on register type) */
252 enum xtensa_reg_type type;
253 enum xtensa_reg_flags flags;
256 struct xtensa_user_reg_desc {
258 /* ISA register num (meaning depends on register type) */
259 unsigned int reg_num;
260 enum xtensa_reg_flags flags;
262 const struct reg_arch_type *type;
265 extern const struct xtensa_reg_desc xtensa_regs[XT_NUM_REGS];
267 #endif /* OPENOCD_TARGET_XTENSA_REGS_H */