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   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 /***************************************************************************
   4  *   Generic Xtensa target API for OpenOCD                                 *
   5  *   Copyright (C) 2020-2022 Cadence Design Systems, Inc.                  *
   6  *   Copyright (C) 2016-2019 Espressif Systems Ltd.                        *
   7  *   Author: Angus Gratton gus@projectgus.com                              *
   8  ***************************************************************************/
   9
  10 #ifndef OPENOCD_TARGET_XTENSA_REGS_H
  11 #define OPENOCD_TARGET_XTENSA_REGS_H
  12
  13 struct reg_arch_type;
  14
  15 enum xtensa_reg_id {
  16         XT_REG_IDX_PC = 0,
  17         XT_REG_IDX_AR0,
  18         XT_REG_IDX_ARFIRST = XT_REG_IDX_AR0,
  19         XT_REG_IDX_AR1,
  20         XT_REG_IDX_AR2,
  21         XT_REG_IDX_AR3,
  22         XT_REG_IDX_AR4,
  23         XT_REG_IDX_AR5,
  24         XT_REG_IDX_AR6,
  25         XT_REG_IDX_AR7,
  26         XT_REG_IDX_AR8,
  27         XT_REG_IDX_AR9,
  28         XT_REG_IDX_AR10,
  29         XT_REG_IDX_AR11,
  30         XT_REG_IDX_AR12,
  31         XT_REG_IDX_AR13,
  32         XT_REG_IDX_AR14,
  33         XT_REG_IDX_AR15,
  34         XT_REG_IDX_ARLAST = 64, /* Max 64 ARs */
  35         XT_REG_IDX_WINDOWBASE,
  36         XT_REG_IDX_WINDOWSTART,
  37         XT_REG_IDX_PS,
  38         XT_REG_IDX_IBREAKENABLE,
  39         XT_REG_IDX_DDR,
  40         XT_REG_IDX_IBREAKA0,
  41         XT_REG_IDX_IBREAKA1,
  42         XT_REG_IDX_DBREAKA0,
  43         XT_REG_IDX_DBREAKA1,
  44         XT_REG_IDX_DBREAKC0,
  45         XT_REG_IDX_DBREAKC1,
  46         XT_REG_IDX_CPENABLE,
  47         XT_REG_IDX_EXCCAUSE,
  48         XT_REG_IDX_DEBUGCAUSE,
  49         XT_REG_IDX_ICOUNT,
  50         XT_REG_IDX_ICOUNTLEVEL,
  51         XT_REG_IDX_A0,
  52         XT_REG_IDX_A1,
  53         XT_REG_IDX_A2,
  54         XT_REG_IDX_A3,
  55         XT_REG_IDX_A4,
  56         XT_REG_IDX_A5,
  57         XT_REG_IDX_A6,
  58         XT_REG_IDX_A7,
  59         XT_REG_IDX_A8,
  60         XT_REG_IDX_A9,
  61         XT_REG_IDX_A10,
  62         XT_REG_IDX_A11,
  63         XT_REG_IDX_A12,
  64         XT_REG_IDX_A13,
  65         XT_REG_IDX_A14,
  66         XT_REG_IDX_A15,
  67         XT_NUM_REGS
  68 };
  69
  70 typedef uint32_t xtensa_reg_val_t;
  71
  72 #define XT_NUM_A_REGS   16
  73
  74 enum xtensa_reg_type {
  75         XT_REG_GENERAL = 0,             /* General-purpose register; part of the windowed register set */
  76         XT_REG_USER = 1,                /* User register, needs RUR to read */
  77         XT_REG_SPECIAL = 2,             /* Special register, needs RSR to read */
  78         XT_REG_DEBUG = 3,               /* Register used for the debug interface. Don't mess with this. */
  79         XT_REG_RELGEN = 4,              /* Relative general address. Points to the absolute addresses plus the window
  80                                          * index */
  81         XT_REG_FR = 5,                  /* Floating-point register */
  82         XT_REG_TIE = 6,                 /* TIE (custom) register */
  83         XT_REG_OTHER = 7,               /* Other (typically legacy) register */
  84         XT_REG_TYPE_NUM,
  85
  86         /* enum names must be one of the above types + _VAL or _MASK */
  87         XT_REG_GENERAL_MASK             = 0xFFC0,
  88         XT_REG_GENERAL_VAL              = 0x0100,
  89         XT_REG_USER_MASK                = 0xFF00,
  90         XT_REG_USER_VAL                 = 0x0300,
  91         XT_REG_SPECIAL_MASK             = 0xFF00,
  92         XT_REG_SPECIAL_VAL              = 0x0200,
  93         XT_REG_DEBUG_MASK               = 0xFF00,
  94         XT_REG_DEBUG_VAL                = 0x0200,
  95         XT_REG_RELGEN_MASK              = 0xFFE0,
  96         XT_REG_RELGEN_VAL               = 0x0000,
  97         XT_REG_FR_MASK                  = 0xFFF0,
  98         XT_REG_FR_VAL                   = 0x0030,
  99         XT_REG_TIE_MASK                 = 0xF000,
 100         XT_REG_TIE_VAL                  = 0xF000,       /* unused */
 101         XT_REG_OTHER_MASK               = 0xFFFF,
 102         XT_REG_OTHER_VAL                = 0xF000,       /* unused */
 103
 104         XT_REG_INDEX_MASK               = 0x00FF
 105 };
 106
 107 enum xtensa_reg_flags {
 108         XT_REGF_NOREAD = 0x01,  /* Register is write-only */
 109         XT_REGF_COPROC0 = 0x02, /* Can't be read if coproc0 isn't enabled */
 110         XT_REGF_MASK = 0x03
 111 };
 112
 113 struct xtensa_reg_desc {
 114         const char *name;
 115         bool exist;
 116         unsigned int reg_num;                   /* ISA register num (meaning depends on register type) */
 117         unsigned int dbreg_num;                 /* Debugger-visible register num (reg type encoded) */
 118         enum xtensa_reg_type type;
 119         enum xtensa_reg_flags flags;
 120 };
 121
 122 #define _XT_MK_DBREGN(reg_num, reg_type)                                        \
 123         ((reg_type ## _VAL) | (reg_num))
 124
 125 #define _XT_MK_DBREGN_MASK(reg_num, reg_mask)                           \
 126         ((reg_mask) | (reg_num))
 127
 128 #define XT_MK_REG_DESC(n, r, t, f)                                                      \
 129         { .name = (n), .exist = false, .reg_num = (r),                  \
 130           .dbreg_num = _XT_MK_DBREGN(r, t), .type = (t),                \
 131           .flags = (f) }
 132
 133 extern struct xtensa_reg_desc xtensa_regs[XT_NUM_REGS];
 134
 135 #endif  /* OPENOCD_TARGET_XTENSA_REGS_H */