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   1 /*
   2  * Copyright © 2018 Keith Packard <keithp@keithp.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful, but
  10  * WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  12  * General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along
  15  * with this program; if not, write to the Free Software Foundation, Inc.,
  16  * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  17  */
  18
  19 #include "ao.h"
  20 #include <ao_task.h>
  21
  22 #ifndef HAS_TICK
  23 #define HAS_TICK 1
  24 #endif
  25
  26 #if HAS_TICK || defined(AO_TIMER_HOOK)
  27
  28 #if HAS_TICK
  29 volatile AO_TICK_TYPE ao_tick_count;
  30
  31 AO_TICK_TYPE
  32 ao_time(void)
  33 {
  34         return ao_tick_count;
  35 }
  36 #endif
  37
  38 #if AO_DATA_ALL
  39 volatile uint8_t        ao_data_interval = 1;
  40 volatile uint8_t        ao_data_count;
  41 #endif
  42
  43 void stm_systick_isr(void)
  44 {
  45         ao_validate_cur_stack();
  46         if (stm_systick.csr & (1 << STM_SYSTICK_CSR_COUNTFLAG)) {
  47 #if HAS_TICK
  48                 ++ao_tick_count;
  49 #endif
  50                 ao_task_check_alarm();
  51 #if AO_DATA_ALL
  52                 if (++ao_data_count == ao_data_interval && ao_data_interval) {
  53                         ao_data_count = 0;
  54 #if HAS_FAKE_FLIGHT
  55                         if (ao_fake_flight_active)
  56                                 ao_fake_flight_poll();
  57                         else
  58 #endif
  59                                 ao_adc_poll();
  60 #if (AO_DATA_ALL & ~(AO_DATA_ADC))
  61                         ao_wakeup((void *) &ao_data_count);
  62 #endif
  63                 }
  64 #endif
  65 #ifdef AO_TIMER_HOOK
  66                 AO_TIMER_HOOK;
  67 #endif
  68         }
  69 }
  70
  71 #if HAS_ADC
  72 void
  73 ao_timer_set_adc_interval(uint8_t interval)
  74 {
  75         ao_arch_critical(
  76                 ao_data_interval = interval;
  77                 ao_data_count = 0;
  78                 );
  79 }
  80 #endif
  81
  82 #define SYSTICK_RELOAD ((AO_SYSTICK / 8) / 100 - 1)
  83
  84 void
  85 ao_timer_init(void)
  86 {
  87         stm_systick.rvr = SYSTICK_RELOAD;
  88         stm_systick.cvr = 0;
  89         stm_systick.csr = ((1 << STM_SYSTICK_CSR_ENABLE) |
  90                            (1 << STM_SYSTICK_CSR_TICKINT) |
  91                            (STM_SYSTICK_CSR_CLKSOURCE_AHB_8 << STM_SYSTICK_CSR_CLKSOURCE));
  92         stm_scb.shpr3 |= AO_STM_NVIC_CLOCK_PRIORITY << 24;
  93 }
  94
  95 #endif
  96
  97 void
  98 ao_clock_init(void)
  99 {
 100         uint32_t        cfgr;
 101         uint32_t        pllcfgr;
 102
 103         /* Switch to HSI while messing about */
 104         stm_rcc.cr |= (1 << STM_RCC_CR_HSION);
 105         while (!(stm_rcc.cr & (1 << STM_RCC_CR_HSIRDY)))
 106                 ao_arch_nop();
 107
 108         stm_rcc.cfgr = (stm_rcc.cfgr & ~(STM_RCC_CFGR_SW_MASK << STM_RCC_CFGR_SW)) |
 109                 (STM_RCC_CFGR_SW_HSI << STM_RCC_CFGR_SW);
 110
 111         /* wait for system to switch to HSI */
 112         while ((stm_rcc.cfgr & (STM_RCC_CFGR_SWS_MASK << STM_RCC_CFGR_SWS)) !=
 113                (STM_RCC_CFGR_SWS_HSI << STM_RCC_CFGR_SWS))
 114                 ao_arch_nop();
 115
 116         /* reset everything but the HSI selection and status */
 117         stm_rcc.cfgr &= (uint32_t)0x0000000f;
 118
 119         /* reset everything but HSI */
 120         stm_rcc.cr &= 0x0000ffff;
 121
 122         /* Disable and clear all interrupts */
 123         stm_rcc.cir = 0xffff0000;
 124
 125 #if AO_HSE
 126 #if AO_HSE_BYPASS
 127         stm_rcc.cr |= (1 << STM_RCC_CR_HSEBYP);
 128 #else
 129         stm_rcc.cr &= ~(1 << STM_RCC_CR_HSEBYP);
 130 #endif
 131         /* Enable HSE clock */
 132         stm_rcc.cr |= (1 << STM_RCC_CR_HSEON);
 133         while (!(stm_rcc.cr & (1 << STM_RCC_CR_HSERDY)))
 134                 asm("nop");
 135
 136 #endif
 137
 138         /* Set flash latency to tolerate SYSCLK */
 139
 140 #define FLASH_LATENCY   ((AO_SYSCLK - 1) / 25000000)
 141
 142         /* Enable icache, dcache and prefetch. Set latency */
 143         stm_flash.acr = ((1 << STM_FLASH_ACR_DCEN) |
 144                          (1 << STM_FLASH_ACR_ICEN) |
 145                          (1 << STM_FLASH_ACR_PRFTEN) |
 146                          (FLASH_LATENCY << STM_FLASH_ACR_LATENCY));
 147
 148         /* Enable power interface clock */
 149         stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_PWREN);
 150
 151 #if AO_SYSCLK <= 64000000
 152 #define VOS_SCALE_MODE  STM_PWR_CR_VOS_SCALE_MODE_1
 153 #elif AO_SYSCLK <= 84000000
 154 #define VOS_SCALE_MODE  STM_PWR_CR_VOS_SCALE_MODE_2
 155 #else
 156 #define VOS_SCALE_MODE  STM_PWR_CR_VOS_SCALE_MODE_1
 157 #endif
 158
 159         /* Set voltage scale mode */
 160         stm_pwr.cr = ((stm_pwr.cr & ~(STM_PWR_CR_VOS_SCALE_MODE_MASK)) |
 161                       (VOS_SCALE_MODE << STM_PWR_CR_VOS));
 162
 163         /* HCLK */
 164         cfgr = stm_rcc.cfgr;
 165         cfgr &= ~(STM_RCC_CFGR_HPRE_MASK << STM_RCC_CFGR_HPRE);
 166         cfgr |= (AO_RCC_CFGR_HPRE_DIV << STM_RCC_CFGR_HPRE);
 167         stm_rcc.cfgr = cfgr;
 168
 169         /* APB1 Prescaler = AO_APB1_PRESCALER */
 170         cfgr = stm_rcc.cfgr;
 171         cfgr &= ~(STM_RCC_CFGR_PPRE1_MASK << STM_RCC_CFGR_PPRE1);
 172         cfgr |= (AO_RCC_CFGR_PPRE1_DIV << STM_RCC_CFGR_PPRE1);
 173         stm_rcc.cfgr = cfgr;
 174
 175         /* APB2 Prescaler = AO_APB2_PRESCALER */
 176         cfgr = stm_rcc.cfgr;
 177         cfgr &= ~(STM_RCC_CFGR_PPRE2_MASK << STM_RCC_CFGR_PPRE2);
 178         cfgr |= (AO_RCC_CFGR_PPRE2_DIV << STM_RCC_CFGR_PPRE2);
 179         stm_rcc.cfgr = cfgr;
 180
 181         /* Clock configuration register DCKCFGR2; mostly make sure USB
 182          * gets clocked from PLL_Q
 183          */
 184         stm_rcc.dckcfgr2 = ((STM_RCC_DCKCFGR2_LPTIMER1SEL_APB << STM_RCC_DCKCFGR2_LPTIMER1SEL) |
 185                             (STM_RCC_DCKCFGR2_SDIOSEL_CK_48MHZ << STM_RCC_DCKCFGR2_SDIOSEL) |
 186                             (STM_RCC_DCKCFGR2_CK48MSEL_PLL_Q << STM_RCC_DCKCFGR2_CK48MSEL) |
 187                             (STM_RCC_DCKCFGR2_I2CFMP1SEL_APB << STM_RCC_DCKCFGR2_I2CFMP1SEL));
 188
 189         /* Disable the PLL */
 190         stm_rcc.cr &= ~(1 << STM_RCC_CR_PLLON);
 191         while (stm_rcc.cr & (1 << STM_RCC_CR_PLLRDY))
 192                 asm("nop");
 193
 194         /* PLL1VCO */
 195         pllcfgr = stm_rcc.pllcfgr;
 196         pllcfgr &= ~(STM_RCC_PLLCFGR_PLLM_MASK << STM_RCC_PLLCFGR_PLLM);
 197         pllcfgr &= ~(STM_RCC_PLLCFGR_PLLN_MASK << STM_RCC_PLLCFGR_PLLN);
 198         pllcfgr &= ~(STM_RCC_PLLCFGR_PLLP_MASK << STM_RCC_PLLCFGR_PLLP);
 199         pllcfgr &= ~(STM_RCC_PLLCFGR_PLLQ_MASK << STM_RCC_PLLCFGR_PLLQ);
 200         pllcfgr &= ~(STM_RCC_PLLCFGR_PLLR_MASK << STM_RCC_PLLCFGR_PLLR);
 201
 202         pllcfgr |= (AO_PLL_M << STM_RCC_PLLCFGR_PLLM);
 203         pllcfgr |= (AO_PLL1_N << STM_RCC_PLLCFGR_PLLN);
 204 #if AO_PLL1_P == 2
 205 #define AO_RCC_PLLCFGR_PLLP     STM_RCC_PLLCFGR_PLLP_DIV_2
 206 #endif
 207 #if AO_PLL1_P == 4
 208 #define AO_RCC_PLLCFGR_PLLP     STM_RCC_PLLCFGR_PLLP_DIV_4
 209 #endif
 210 #if AO_PLL1_P == 6
 211 #define AO_RCC_PLLCFGR_PLLP     STM_RCC_PLLCFGR_PLLP_DIV_6
 212 #endif
 213 #if AO_PLL1_P == 8
 214 #define AO_RCC_PLLCFGR_PLLP     STM_RCC_PLLCFGR_PLLP_DIV_8
 215 #endif
 216         pllcfgr |= (AO_RCC_PLLCFGR_PLLP << STM_RCC_PLLCFGR_PLLP);
 217         pllcfgr |= (AO_PLL1_Q << STM_RCC_PLLCFGR_PLLQ);
 218         pllcfgr |= (AO_PLL1_R << STM_RCC_PLLCFGR_PLLR);
 219         /* PLL source */
 220         pllcfgr &= ~(1 << STM_RCC_PLLCFGR_PLLSRC);
 221 #if AO_HSI
 222         pllcfgr |= (STM_RCC_PLLCFGR_PLLSRC_HSI << STM_RCC_PLLCFGR_PLLSRC);
 223 #endif
 224 #if AO_HSE
 225         pllcfgr |= (STM_RCC_PLLCFGR_PLLSRC_HSE << STM_RCC_PLLCFGR_PLLSRC);
 226 #endif
 227         stm_rcc.pllcfgr = pllcfgr;
 228
 229         /* Enable the PLL and wait for it */
 230         stm_rcc.cr |= (1 << STM_RCC_CR_PLLON);
 231         while (!(stm_rcc.cr & (1 << STM_RCC_CR_PLLRDY)))
 232                 asm("nop");
 233
 234         /* Switch to the PLL for the system clock */
 235
 236         cfgr = stm_rcc.cfgr;
 237         cfgr &= ~(STM_RCC_CFGR_SW_MASK << STM_RCC_CFGR_SW);
 238         cfgr |= (STM_RCC_CFGR_SW_PLL << STM_RCC_CFGR_SW);
 239         stm_rcc.cfgr = cfgr;
 240         for (;;) {
 241                 uint32_t        c, part, mask, val;
 242
 243                 c = stm_rcc.cfgr;
 244                 mask = (STM_RCC_CFGR_SWS_MASK << STM_RCC_CFGR_SWS);
 245                 val = (STM_RCC_CFGR_SWS_PLL << STM_RCC_CFGR_SWS);
 246                 part = c & mask;
 247                 if (part == val)
 248                         break;
 249         }
 250
 251 #if AO_HSE
 252         /* Disable HSI clock */
 253         stm_rcc.cr &= ~(1 << STM_RCC_CR_HSION);
 254 #endif
 255
 256         /* Clear reset flags */
 257         stm_rcc.csr |= (1 << STM_RCC_CSR_RMVF);
 258
 259 #if DEBUG_THE_CLOCK
 260         /* Output PLL clock on PA8 and SYCLK on PC9 for measurments */
 261
 262         ao_enable_port(&stm_gpioa);
 263         stm_afr_set(&stm_gpioa, 8, STM_AFR_AF0);
 264         stm_moder_set(&stm_gpioa, 8, STM_MODER_ALTERNATE);
 265         stm_ospeedr_set(&stm_gpioa, 8, STM_OSPEEDR_HIGH);
 266
 267         ao_enable_port(&stm_gpioc);
 268         stm_afr_set(&stm_gpioc, 9, STM_AFR_AF0);
 269         stm_moder_set(&stm_gpioc, 9, STM_MODER_ALTERNATE);
 270         stm_ospeedr_set(&stm_gpioc, 9, STM_OSPEEDR_HIGH);
 271
 272         cfgr = stm_rcc.cfgr;
 273         cfgr &= 0x001fffff;
 274         cfgr |= ((0 << STM_RCC_CFGR_MCO2) |
 275                  (6 << STM_RCC_CFGR_MCO2PRE) |
 276                  (6 << STM_RCC_CFGR_MCO1PRE) |
 277                  (2 << STM_RCC_CFGR_MCO1));
 278         stm_rcc.cfgr = cfgr;
 279 #endif
 280 }