remove Altera-licensed files to achieve DFSG compliance

diff --git a/cleanup-script.sh b/cleanup-script.sh
new file mode 100755 (executable)
index 0000000..3351554
--- /dev/null
+++ b/cleanup-script.sh
@@ -0,0 +1,9 @@
+#!/bin/sh
+#
+#      clean upstream source to achieve DFSG compliance
+#      Copyright 2009 by Bdale Garbee.  GPL v2 or any later version.
+#
+
+git rm -f `find . -name \*.qpf ; find . -name \*.qsf`
+
+exit 0

diff --git a/gr-gpio/src/fpga/top/usrp_gpio.qpf b/gr-gpio/src/fpga/top/usrp_gpio.qpf
deleted file mode 100644 (file)
index 7eb8da9..0000000
--- a/gr-gpio/src/fpga/top/usrp_gpio.qpf
+++ /dev/null
@@ -1,29 +0,0 @@
-# Copyright (C) 1991-2004 Altera Corporation
-# Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
-# support information,  device programming or simulation file,  and any other
-# associated  documentation or information  provided by  Altera  or a partner
-# under  Altera's   Megafunction   Partnership   Program  may  be  used  only
-# to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
-# other  use  of such  megafunction  design,  netlist,  support  information,
-# device programming or simulation file,  or any other  related documentation
-# or information  is prohibited  for  any  other purpose,  including, but not
-# limited to  modification,  reverse engineering,  de-compiling, or use  with
-# any other  silicon devices,  unless such use is  explicitly  licensed under
-# a separate agreement with  Altera  or a megafunction partner.  Title to the
-# intellectual property,  including patents,  copyrights,  trademarks,  trade
-# secrets,  or maskworks,  embodied in any such megafunction design, netlist,
-# support  information,  device programming or simulation file,  or any other
-# related documentation or information provided by  Altera  or a megafunction
-# partner, remains with Altera, the megafunction partner, or their respective
-# licensors. No other licenses, including any licenses needed under any third
-# party's intellectual property, are provided herein.
-
-
-
-QUARTUS_VERSION = "4.0"
-DATE = "17:10:11  December 20, 2004"
-
-
-# Active Revisions
-
-PROJECT_REVISION = "usrp_gpio"

diff --git a/gr-gpio/src/fpga/top/usrp_gpio.qsf b/gr-gpio/src/fpga/top/usrp_gpio.qsf
deleted file mode 100644 (file)
index cfdcd55..0000000
--- a/gr-gpio/src/fpga/top/usrp_gpio.qsf
+++ /dev/null
@@ -1,412 +0,0 @@
-# Copyright (C) 1991-2005 Altera Corporation\r
-# Your use of Altera Corporation's design tools, logic functions \r
-# and other software and tools, and its AMPP partner logic       \r
-# functions, and any output files any of the foregoing           \r
-# (including device programming or simulation files), and any    \r
-# associated documentation or information are expressly subject  \r
-# to the terms and conditions of the Altera Program License      \r
-# Subscription Agreement, Altera MegaCore Function License       \r
-# Agreement, or other applicable license agreement, including,   \r
-# without limitation, that your use is for the sole purpose of   \r
-# programming logic devices manufactured by Altera and sold by   \r
-# Altera or its authorized distributors.  Please refer to the    \r
-# applicable agreement for further details.\r
-\r
-\r
-# The default values for assignments are stored in the file\r
-#              usrp_gpio_assignment_defaults.qdf\r
-# If this file doesn't exist, and for assignments not listed, see file\r
-#              assignment_defaults.qdf\r
-\r
-# Altera recommends that you do not modify this file. This\r
-# file is updated automatically by the Quartus II software\r
-# and any changes you make may be lost or overwritten.\r
-\r
-\r
-# Project-Wide Assignments\r
-# ========================\r
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 3.0\r
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:14:04  JULY 13, 2003"\r
-set_global_assignment -name LAST_QUARTUS_VERSION "7.1 SP1"\r
-\r
-# Pin & Location Assignments\r
-# ==========================\r
-set_global_assignment -name RESERVE_PIN "AS INPUT TRI-STATED"\r
-set_location_assignment PIN_29 -to SCLK\r
-set_location_assignment PIN_117 -to SDI\r
-set_location_assignment PIN_28 -to usbclk\r
-set_location_assignment PIN_107 -to usbctl[0]\r
-set_location_assignment PIN_106 -to usbctl[1]\r
-set_location_assignment PIN_105 -to usbctl[2]\r
-set_location_assignment PIN_100 -to usbdata[0]\r
-set_location_assignment PIN_84 -to usbdata[10]\r
-set_location_assignment PIN_83 -to usbdata[11]\r
-set_location_assignment PIN_82 -to usbdata[12]\r
-set_location_assignment PIN_79 -to usbdata[13]\r
-set_location_assignment PIN_78 -to usbdata[14]\r
-set_location_assignment PIN_77 -to usbdata[15]\r
-set_location_assignment PIN_99 -to usbdata[1]\r
-set_location_assignment PIN_98 -to usbdata[2]\r
-set_location_assignment PIN_95 -to usbdata[3]\r
-set_location_assignment PIN_94 -to usbdata[4]\r
-set_location_assignment PIN_93 -to usbdata[5]\r
-set_location_assignment PIN_88 -to usbdata[6]\r
-set_location_assignment PIN_87 -to usbdata[7]\r
-set_location_assignment PIN_86 -to usbdata[8]\r
-set_location_assignment PIN_85 -to usbdata[9]\r
-set_location_assignment PIN_104 -to usbrdy[0]\r
-set_location_assignment PIN_101 -to usbrdy[1]\r
-set_location_assignment PIN_76 -to FX2_1\r
-set_location_assignment PIN_75 -to FX2_2\r
-set_location_assignment PIN_74 -to FX2_3\r
-set_location_assignment PIN_116 -to io_rx_a[0]\r
-set_location_assignment PIN_115 -to io_rx_a[1]\r
-set_location_assignment PIN_114 -to io_rx_a[2]\r
-set_location_assignment PIN_113 -to io_rx_a[3]\r
-set_location_assignment PIN_108 -to io_rx_a[4]\r
-set_location_assignment PIN_195 -to io_rx_a[5]\r
-set_location_assignment PIN_196 -to io_rx_a[6]\r
-set_location_assignment PIN_197 -to io_rx_a[7]\r
-set_location_assignment PIN_200 -to io_rx_a[8]\r
-set_location_assignment PIN_201 -to io_rx_a[9]\r
-set_location_assignment PIN_202 -to io_rx_a[10]\r
-set_location_assignment PIN_203 -to io_rx_a[11]\r
-set_location_assignment PIN_206 -to io_rx_a[12]\r
-set_location_assignment PIN_207 -to io_rx_a[13]\r
-set_location_assignment PIN_208 -to io_rx_a[14]\r
-set_location_assignment PIN_214 -to io_rx_b[0]\r
-set_location_assignment PIN_215 -to io_rx_b[1]\r
-set_location_assignment PIN_216 -to io_rx_b[2]\r
-set_location_assignment PIN_217 -to io_rx_b[3]\r
-set_location_assignment PIN_218 -to io_rx_b[4]\r
-set_location_assignment PIN_219 -to io_rx_b[5]\r
-set_location_assignment PIN_222 -to io_rx_b[6]\r
-set_location_assignment PIN_223 -to io_rx_b[7]\r
-set_location_assignment PIN_224 -to io_rx_b[8]\r
-set_location_assignment PIN_225 -to io_rx_b[9]\r
-set_location_assignment PIN_226 -to io_rx_b[10]\r
-set_location_assignment PIN_227 -to io_rx_b[11]\r
-set_location_assignment PIN_228 -to io_rx_b[12]\r
-set_location_assignment PIN_233 -to io_rx_b[13]\r
-set_location_assignment PIN_234 -to io_rx_b[14]\r
-set_location_assignment PIN_175 -to io_tx_a[0]\r
-set_location_assignment PIN_176 -to io_tx_a[1]\r
-set_location_assignment PIN_177 -to io_tx_a[2]\r
-set_location_assignment PIN_178 -to io_tx_a[3]\r
-set_location_assignment PIN_179 -to io_tx_a[4]\r
-set_location_assignment PIN_180 -to io_tx_a[5]\r
-set_location_assignment PIN_181 -to io_tx_a[6]\r
-set_location_assignment PIN_182 -to io_tx_a[7]\r
-set_location_assignment PIN_183 -to io_tx_a[8]\r
-set_location_assignment PIN_184 -to io_tx_a[9]\r
-set_location_assignment PIN_185 -to io_tx_a[10]\r
-set_location_assignment PIN_186 -to io_tx_a[11]\r
-set_location_assignment PIN_187 -to io_tx_a[12]\r
-set_location_assignment PIN_188 -to io_tx_a[13]\r
-set_location_assignment PIN_193 -to io_tx_a[14]\r
-set_location_assignment PIN_73 -to io_tx_b[0]\r
-set_location_assignment PIN_68 -to io_tx_b[1]\r
-set_location_assignment PIN_67 -to io_tx_b[2]\r
-set_location_assignment PIN_66 -to io_tx_b[3]\r
-set_location_assignment PIN_65 -to io_tx_b[4]\r
-set_location_assignment PIN_64 -to io_tx_b[5]\r
-set_location_assignment PIN_63 -to io_tx_b[6]\r
-set_location_assignment PIN_62 -to io_tx_b[7]\r
-set_location_assignment PIN_61 -to io_tx_b[8]\r
-set_location_assignment PIN_60 -to io_tx_b[9]\r
-set_location_assignment PIN_59 -to io_tx_b[10]\r
-set_location_assignment PIN_58 -to io_tx_b[11]\r
-set_location_assignment PIN_57 -to io_tx_b[12]\r
-set_location_assignment PIN_56 -to io_tx_b[13]\r
-set_location_assignment PIN_55 -to io_tx_b[14]\r
-set_location_assignment PIN_152 -to master_clk\r
-set_location_assignment PIN_144 -to rx_a_a[0]\r
-set_location_assignment PIN_143 -to rx_a_a[1]\r
-set_location_assignment PIN_141 -to rx_a_a[2]\r
-set_location_assignment PIN_140 -to rx_a_a[3]\r
-set_location_assignment PIN_139 -to rx_a_a[4]\r
-set_location_assignment PIN_138 -to rx_a_a[5]\r
-set_location_assignment PIN_137 -to rx_a_a[6]\r
-set_location_assignment PIN_136 -to rx_a_a[7]\r
-set_location_assignment PIN_135 -to rx_a_a[8]\r
-set_location_assignment PIN_134 -to rx_a_a[9]\r
-set_location_assignment PIN_133 -to rx_a_a[10]\r
-set_location_assignment PIN_132 -to rx_a_a[11]\r
-set_location_assignment PIN_23 -to rx_a_b[0]\r
-set_location_assignment PIN_21 -to rx_a_b[1]\r
-set_location_assignment PIN_20 -to rx_a_b[2]\r
-set_location_assignment PIN_19 -to rx_a_b[3]\r
-set_location_assignment PIN_18 -to rx_a_b[4]\r
-set_location_assignment PIN_17 -to rx_a_b[5]\r
-set_location_assignment PIN_16 -to rx_a_b[6]\r
-set_location_assignment PIN_15 -to rx_a_b[7]\r
-set_location_assignment PIN_14 -to rx_a_b[8]\r
-set_location_assignment PIN_13 -to rx_a_b[9]\r
-set_location_assignment PIN_12 -to rx_a_b[10]\r
-set_location_assignment PIN_11 -to rx_a_b[11]\r
-set_location_assignment PIN_131 -to rx_b_a[0]\r
-set_location_assignment PIN_128 -to rx_b_a[1]\r
-set_location_assignment PIN_127 -to rx_b_a[2]\r
-set_location_assignment PIN_126 -to rx_b_a[3]\r
-set_location_assignment PIN_125 -to rx_b_a[4]\r
-set_location_assignment PIN_124 -to rx_b_a[5]\r
-set_location_assignment PIN_123 -to rx_b_a[6]\r
-set_location_assignment PIN_122 -to rx_b_a[7]\r
-set_location_assignment PIN_121 -to rx_b_a[8]\r
-set_location_assignment PIN_120 -to rx_b_a[9]\r
-set_location_assignment PIN_119 -to rx_b_a[10]\r
-set_location_assignment PIN_118 -to rx_b_a[11]\r
-set_location_assignment PIN_8 -to rx_b_b[0]\r
-set_location_assignment PIN_7 -to rx_b_b[1]\r
-set_location_assignment PIN_6 -to rx_b_b[2]\r
-set_location_assignment PIN_5 -to rx_b_b[3]\r
-set_location_assignment PIN_4 -to rx_b_b[4]\r
-set_location_assignment PIN_3 -to rx_b_b[5]\r
-set_location_assignment PIN_2 -to rx_b_b[6]\r
-set_location_assignment PIN_240 -to rx_b_b[7]\r
-set_location_assignment PIN_239 -to rx_b_b[8]\r
-set_location_assignment PIN_238 -to rx_b_b[9]\r
-set_location_assignment PIN_237 -to rx_b_b[10]\r
-set_location_assignment PIN_236 -to rx_b_b[11]\r
-set_location_assignment PIN_156 -to SDO\r
-set_location_assignment PIN_153 -to SEN_FPGA\r
-set_location_assignment PIN_159 -to tx_a[0]\r
-set_location_assignment PIN_160 -to tx_a[1]\r
-set_location_assignment PIN_161 -to tx_a[2]\r
-set_location_assignment PIN_162 -to tx_a[3]\r
-set_location_assignment PIN_163 -to tx_a[4]\r
-set_location_assignment PIN_164 -to tx_a[5]\r
-set_location_assignment PIN_165 -to tx_a[6]\r
-set_location_assignment PIN_166 -to tx_a[7]\r
-set_location_assignment PIN_167 -to tx_a[8]\r
-set_location_assignment PIN_168 -to tx_a[9]\r
-set_location_assignment PIN_169 -to tx_a[10]\r
-set_location_assignment PIN_170 -to tx_a[11]\r
-set_location_assignment PIN_173 -to tx_a[12]\r
-set_location_assignment PIN_174 -to tx_a[13]\r
-set_location_assignment PIN_38 -to tx_b[0]\r
-set_location_assignment PIN_39 -to tx_b[1]\r
-set_location_assignment PIN_41 -to tx_b[2]\r
-set_location_assignment PIN_42 -to tx_b[3]\r
-set_location_assignment PIN_43 -to tx_b[4]\r
-set_location_assignment PIN_44 -to tx_b[5]\r
-set_location_assignment PIN_45 -to tx_b[6]\r
-set_location_assignment PIN_46 -to tx_b[7]\r
-set_location_assignment PIN_47 -to tx_b[8]\r
-set_location_assignment PIN_48 -to tx_b[9]\r
-set_location_assignment PIN_49 -to tx_b[10]\r
-set_location_assignment PIN_50 -to tx_b[11]\r
-set_location_assignment PIN_53 -to tx_b[12]\r
-set_location_assignment PIN_54 -to tx_b[13]\r
-set_location_assignment PIN_158 -to TXSYNC_A\r
-set_location_assignment PIN_37 -to TXSYNC_B\r
-set_location_assignment PIN_235 -to io_rx_b[15]\r
-set_location_assignment PIN_24 -to io_tx_b[15]\r
-set_location_assignment PIN_213 -to io_rx_a[15]\r
-set_location_assignment PIN_194 -to io_tx_a[15]\r
-set_location_assignment PIN_1 -to MYSTERY_SIGNAL\r
-\r
-# Timing Assignments\r
-# ==================\r
-set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF\r
-\r
-# Analysis & Synthesis Assignments\r
-# ================================\r
-set_global_assignment -name SAVE_DISK_SPACE OFF\r
-set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP"\r
-set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240\r
-set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"\r
-set_global_assignment -name FAMILY Cyclone\r
-set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE BALANCED\r
-set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED\r
-set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED\r
-set_global_assignment -name TOP_LEVEL_ENTITY usrp_gpio\r
-set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF\r
-set_global_assignment -name USER_LIBRARIES "e:\\usrp\\fpga\\megacells"\r
-set_global_assignment -name AUTO_ENABLE_SMART_COMPILE ON\r
-\r
-# Fitter Assignments\r
-# ==================\r
-set_global_assignment -name DEVICE EP1C12Q240C8\r
-set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "PASSIVE SERIAL"\r
-set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"\r
-set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF\r
-set_global_assignment -name OPTIMIZE_TIMING "NORMAL COMPILATION"\r
-set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF\r
-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF\r
-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF\r
-set_global_assignment -name IO_PLACEMENT_OPTIMIZATION OFF\r
-set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL\r
-set_global_assignment -name INC_PLC_MODE OFF\r
-set_global_assignment -name ROUTING_BACK_ANNOTATION_MODE OFF\r
-set_instance_assignment -name IO_STANDARD LVTTL -to usbdata[12]\r
-set_global_assignment -name STRATIX_DEVICE_IO_STANDARD LVTTL\r
-set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1\r
-\r
-# Timing Analysis Assignments\r
-# ===========================\r
-set_global_assignment -name MAX_SCC_SIZE 50\r
-\r
-# EDA Netlist Writer Assignments\r
-# ==============================\r
-set_global_assignment -name EDA_SIMULATION_TOOL "<None>"\r
-set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<NONE>"\r
-set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<NONE>"\r
-set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<NONE>"\r
-set_global_assignment -name EDA_RESYNTHESIS_TOOL "<NONE>"\r
-\r
-# Assembler Assignments\r
-# =====================\r
-set_global_assignment -name USE_CONFIGURATION_DEVICE OFF\r
-set_global_assignment -name GENERATE_RBF_FILE ON\r
-set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"\r
-set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF\r
-\r
-# Simulator Assignments\r
-# =====================\r
-set_global_assignment -name START_TIME "0 ns"\r
-set_global_assignment -name GLITCH_INTERVAL "1 ns"\r
-\r
-# Design Assistant Assignments\r
-# ============================\r
-set_global_assignment -name DRC_REPORT_TOP_FANOUT OFF\r
-set_global_assignment -name DRC_REPORT_FANOUT_EXCEEDING OFF\r
-set_global_assignment -name ASSG_CAT OFF\r
-set_global_assignment -name ASSG_RULE_MISSING_FMAX OFF\r
-set_global_assignment -name ASSG_RULE_MISSING_TIMING OFF\r
-set_global_assignment -name NONSYNCHSTRUCT_RULE_ASYN_RAM OFF\r
-set_global_assignment -name CLK_CAT OFF\r
-set_global_assignment -name CLK_RULE_COMB_CLOCK OFF\r
-set_global_assignment -name CLK_RULE_INV_CLOCK OFF\r
-set_global_assignment -name CLK_RULE_GATING_SCHEME OFF\r
-set_global_assignment -name CLK_RULE_INPINS_CLKNET OFF\r
-set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES OFF\r
-set_global_assignment -name CLK_RULE_MIX_EDGES OFF\r
-set_global_assignment -name RESET_CAT OFF\r
-set_global_assignment -name RESET_RULE_INPINS_RESETNET OFF\r
-set_global_assignment -name RESET_RULE_UNSYNCH_EXRESET OFF\r
-set_global_assignment -name RESET_RULE_IMSYNCH_EXRESET OFF\r
-set_global_assignment -name RESET_RULE_COMB_ASYNCH_RESET OFF\r
-set_global_assignment -name RESET_RULE_UNSYNCH_ASYNCH_DOMAIN OFF\r
-set_global_assignment -name RESET_RULE_IMSYNCH_ASYNCH_DOMAIN OFF\r
-set_global_assignment -name TIMING_CAT OFF\r
-set_global_assignment -name TIMING_RULE_SHIFT_REG OFF\r
-set_global_assignment -name TIMING_RULE_COIN_CLKEDGE OFF\r
-set_global_assignment -name NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE OFF\r
-set_global_assignment -name NONSYNCHSTRUCT_CAT OFF\r
-set_global_assignment -name NONSYNCHSTRUCT_RULE_COMBLOOP OFF\r
-set_global_assignment -name NONSYNCHSTRUCT_RULE_REG_LOOP OFF\r
-set_global_assignment -name NONSYNCHSTRUCT_RULE_DELAY_CHAIN OFF\r
-set_global_assignment -name NONSYNCHSTRUCT_RULE_RIPPLE_CLK OFF\r
-set_global_assignment -name NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN OFF\r
-set_global_assignment -name NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR OFF\r
-set_global_assignment -name NONSYNCHSTRUCT_RULE_SRLATCH OFF\r
-set_global_assignment -name NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED OFF\r
-set_global_assignment -name SIGNALRACE_CAT OFF\r
-set_global_assignment -name ACLK_CAT OFF\r
-set_global_assignment -name ACLK_RULE_NO_SZER_ACLK_DOMAIN OFF\r
-set_global_assignment -name ACLK_RULE_SZER_BTW_ACLK_DOMAIN OFF\r
-set_global_assignment -name ACLK_RULE_IMSZER_ADOMAIN OFF\r
-set_global_assignment -name HCPY_CAT OFF\r
-set_global_assignment -name HCPY_VREF_PINS OFF\r
-\r
-# SignalTap II Assignments\r
-# ========================\r
-set_global_assignment -name HUB_ENTITY_NAME SLD_HUB\r
-set_global_assignment -name HUB_INSTANCE_NAME SLD_HUB_INST\r
-set_global_assignment -name ENABLE_SIGNALTAP OFF\r
-\r
-# LogicLock Region Assignments\r
-# ============================\r
-set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT OFF\r
-\r
-# -----------------\r
-# start CLOCK(SCLK)\r
-\r
-       # Timing Assignments\r
-       # ==================\r
-set_global_assignment -name DUTY_CYCLE 50 -section_id SCLK\r
-set_global_assignment -name FMAX_REQUIREMENT "1 MHz" -section_id SCLK\r
-set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id SCLK\r
-\r
-# end CLOCK(SCLK)\r
-# ---------------\r
-\r
-# -----------------------\r
-# start CLOCK(master_clk)\r
-\r
-       # Timing Assignments\r
-       # ==================\r
-set_global_assignment -name DUTY_CYCLE 50 -section_id master_clk\r
-set_global_assignment -name FMAX_REQUIREMENT "64 MHz" -section_id master_clk\r
-set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id master_clk\r
-\r
-# end CLOCK(master_clk)\r
-# ---------------------\r
-\r
-# -------------------\r
-# start CLOCK(usbclk)\r
-\r
-       # Timing Assignments\r
-       # ==================\r
-set_global_assignment -name DUTY_CYCLE 50 -section_id usbclk\r
-set_global_assignment -name FMAX_REQUIREMENT "48 MHz" -section_id usbclk\r
-set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id usbclk\r
-\r
-# end CLOCK(usbclk)\r
-# -----------------\r
-\r
-# ----------------------\r
-# start ENTITY(usrp_gpio)\r
-\r
-       # Timing Assignments\r
-       # ==================\r
-set_instance_assignment -name CLOCK_SETTINGS SCLK -to SCLK\r
-set_instance_assignment -name CLOCK_SETTINGS usbclk -to usbclk\r
-set_instance_assignment -name CLOCK_SETTINGS master_clk -to master_clk\r
-\r
-# end ENTITY(usrp_gpio)\r
-# --------------------\r
-\r
-set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top\r
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top\r
-set_global_assignment -name VERILOG_FILE usrp_gpio.v\r
-set_global_assignment -name VERILOG_FILE ../lib/gpio_input.v\r
-set_global_assignment -name VERILOG_FILE ../lib/io_pins.v\r
-set_global_assignment -name VERILOG_FILE ../lib/rx_chain_dig.v\r
-set_global_assignment -name VERILOG_FILE ../lib/tx_chain_dig.v\r
-set_global_assignment -name VERILOG_FILE ../lib/integrator.v\r
-set_global_assignment -name VERILOG_FILE ../lib/integ_shifter.v\r
-set_global_assignment -name VERILOG_FILE ../lib/rx_chain.v\r
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/atr_delay.v\r
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/cic_dec_shifter.v\r
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/rssi.v\r
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/ram16.v\r
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/megacells/fifo_4k.v\r
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/megacells/bustri.v\r
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/megacells/fifo_4k_18.v\r
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/hb/acc.v\r
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/hb/mult.v\r
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/hb/ram16_2sum.v\r
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/hb/coeff_rom.v\r
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/hb/halfband_decim.v\r
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/hb/mac.v\r
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/tx_chain.v\r
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/rx_dcoffset.v\r
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/adc_interface.v\r
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/setting_reg.v\r
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/bidir_reg.v\r
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/cic_int_shifter.v\r
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/gen_sync.v\r
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/master_control.v\r
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/rx_buffer.v\r
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/tx_buffer.v\r
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/phase_acc.v\r
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/cic_interp.v\r
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/cic_decim.v\r
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/cordic_stage.v\r
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/cordic.v\r
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/clk_divider.v\r
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/serial_io.v\r
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/strobe_gen.v\r
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/sign_extend.v
\ No newline at end of file

diff --git a/gr-radar-mono/src/fpga/top/usrp_radar_mono.qpf b/gr-radar-mono/src/fpga/top/usrp_radar_mono.qpf
deleted file mode 100644 (file)
index d85239e..0000000
--- a/gr-radar-mono/src/fpga/top/usrp_radar_mono.qpf
+++ /dev/null
@@ -1,29 +0,0 @@
-# Copyright (C) 1991-2004 Altera Corporation
-# Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
-# support information,  device programming or simulation file,  and any other
-# associated  documentation or information  provided by  Altera  or a partner
-# under  Altera's   Megafunction   Partnership   Program  may  be  used  only
-# to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
-# other  use  of such  megafunction  design,  netlist,  support  information,
-# device programming or simulation file,  or any other  related documentation
-# or information  is prohibited  for  any  other purpose,  including, but not
-# limited to  modification,  reverse engineering,  de-compiling, or use  with
-# any other  silicon devices,  unless such use is  explicitly  licensed under
-# a separate agreement with  Altera  or a megafunction partner.  Title to the
-# intellectual property,  including patents,  copyrights,  trademarks,  trade
-# secrets,  or maskworks,  embodied in any such megafunction design, netlist,
-# support  information,  device programming or simulation file,  or any other
-# related documentation or information provided by  Altera  or a megafunction
-# partner, remains with Altera, the megafunction partner, or their respective
-# licensors. No other licenses, including any licenses needed under any third
-# party's intellectual property, are provided herein.
-
-
-
-QUARTUS_VERSION = "4.0"
-DATE = "17:10:11  December 20, 2004"
-
-
-# Active Revisions
-
-PROJECT_REVISION = "usrp_radar_mono"

diff --git a/gr-radar-mono/src/fpga/top/usrp_radar_mono.qsf b/gr-radar-mono/src/fpga/top/usrp_radar_mono.qsf
deleted file mode 100644 (file)
index 9b13989..0000000
--- a/gr-radar-mono/src/fpga/top/usrp_radar_mono.qsf
+++ /dev/null
@@ -1,402 +0,0 @@
-# Copyright (C) 1991-2007 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Altera Program License 
-# Subscription Agreement, Altera MegaCore Function License 
-# Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by 
-# Altera or its authorized distributors.  Please refer to the 
-# applicable agreement for further details.
-
-
-# The default values for assignments are stored in the file
-#              usrp_radar_mono_assignment_defaults.qdf
-# If this file doesn't exist, and for assignments not listed, see file
-#              assignment_defaults.qdf
-
-# Altera recommends that you do not modify this file. This
-# file is updated automatically by the Quartus II software
-# and any changes you make may be lost or overwritten.
-
-
-
-# Project-Wide Assignments
-# ========================
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 3.0
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:14:04  JULY 13, 2003"
-set_global_assignment -name LAST_QUARTUS_VERSION "7.1 SP1"
-set_global_assignment -name MESSAGE_SUPPRESSION_RULE_FILE usrp_radar_mono.srf
-
-# Pin & Location Assignments
-# ==========================
-set_global_assignment -name RESERVE_PIN "AS INPUT TRI-STATED"
-set_location_assignment PIN_29 -to SCLK
-set_location_assignment PIN_117 -to SDI
-set_location_assignment PIN_28 -to usbclk
-set_location_assignment PIN_107 -to usbctl[0]
-set_location_assignment PIN_106 -to usbctl[1]
-set_location_assignment PIN_105 -to usbctl[2]
-set_location_assignment PIN_100 -to usbdata[0]
-set_location_assignment PIN_84 -to usbdata[10]
-set_location_assignment PIN_83 -to usbdata[11]
-set_location_assignment PIN_82 -to usbdata[12]
-set_location_assignment PIN_79 -to usbdata[13]
-set_location_assignment PIN_78 -to usbdata[14]
-set_location_assignment PIN_77 -to usbdata[15]
-set_location_assignment PIN_99 -to usbdata[1]
-set_location_assignment PIN_98 -to usbdata[2]
-set_location_assignment PIN_95 -to usbdata[3]
-set_location_assignment PIN_94 -to usbdata[4]
-set_location_assignment PIN_93 -to usbdata[5]
-set_location_assignment PIN_88 -to usbdata[6]
-set_location_assignment PIN_87 -to usbdata[7]
-set_location_assignment PIN_86 -to usbdata[8]
-set_location_assignment PIN_85 -to usbdata[9]
-set_location_assignment PIN_104 -to usbrdy[0]
-set_location_assignment PIN_101 -to usbrdy[1]
-set_location_assignment PIN_76 -to FX2_1
-set_location_assignment PIN_75 -to FX2_2
-set_location_assignment PIN_74 -to FX2_3
-set_location_assignment PIN_116 -to io_rx_a[0]
-set_location_assignment PIN_115 -to io_rx_a[1]
-set_location_assignment PIN_114 -to io_rx_a[2]
-set_location_assignment PIN_113 -to io_rx_a[3]
-set_location_assignment PIN_108 -to io_rx_a[4]
-set_location_assignment PIN_195 -to io_rx_a[5]
-set_location_assignment PIN_196 -to io_rx_a[6]
-set_location_assignment PIN_197 -to io_rx_a[7]
-set_location_assignment PIN_200 -to io_rx_a[8]
-set_location_assignment PIN_201 -to io_rx_a[9]
-set_location_assignment PIN_202 -to io_rx_a[10]
-set_location_assignment PIN_203 -to io_rx_a[11]
-set_location_assignment PIN_206 -to io_rx_a[12]
-set_location_assignment PIN_207 -to io_rx_a[13]
-set_location_assignment PIN_208 -to io_rx_a[14]
-set_location_assignment PIN_214 -to io_rx_b[0]
-set_location_assignment PIN_215 -to io_rx_b[1]
-set_location_assignment PIN_216 -to io_rx_b[2]
-set_location_assignment PIN_217 -to io_rx_b[3]
-set_location_assignment PIN_218 -to io_rx_b[4]
-set_location_assignment PIN_219 -to io_rx_b[5]
-set_location_assignment PIN_222 -to io_rx_b[6]
-set_location_assignment PIN_223 -to io_rx_b[7]
-set_location_assignment PIN_224 -to io_rx_b[8]
-set_location_assignment PIN_225 -to io_rx_b[9]
-set_location_assignment PIN_226 -to io_rx_b[10]
-set_location_assignment PIN_227 -to io_rx_b[11]
-set_location_assignment PIN_228 -to io_rx_b[12]
-set_location_assignment PIN_233 -to io_rx_b[13]
-set_location_assignment PIN_234 -to io_rx_b[14]
-set_location_assignment PIN_175 -to io_tx_a[0]
-set_location_assignment PIN_176 -to io_tx_a[1]
-set_location_assignment PIN_177 -to io_tx_a[2]
-set_location_assignment PIN_178 -to io_tx_a[3]
-set_location_assignment PIN_179 -to io_tx_a[4]
-set_location_assignment PIN_180 -to io_tx_a[5]
-set_location_assignment PIN_181 -to io_tx_a[6]
-set_location_assignment PIN_182 -to io_tx_a[7]
-set_location_assignment PIN_183 -to io_tx_a[8]
-set_location_assignment PIN_184 -to io_tx_a[9]
-set_location_assignment PIN_185 -to io_tx_a[10]
-set_location_assignment PIN_186 -to io_tx_a[11]
-set_location_assignment PIN_187 -to io_tx_a[12]
-set_location_assignment PIN_188 -to io_tx_a[13]
-set_location_assignment PIN_193 -to io_tx_a[14]
-set_location_assignment PIN_73 -to io_tx_b[0]
-set_location_assignment PIN_68 -to io_tx_b[1]
-set_location_assignment PIN_67 -to io_tx_b[2]
-set_location_assignment PIN_66 -to io_tx_b[3]
-set_location_assignment PIN_65 -to io_tx_b[4]
-set_location_assignment PIN_64 -to io_tx_b[5]
-set_location_assignment PIN_63 -to io_tx_b[6]
-set_location_assignment PIN_62 -to io_tx_b[7]
-set_location_assignment PIN_61 -to io_tx_b[8]
-set_location_assignment PIN_60 -to io_tx_b[9]
-set_location_assignment PIN_59 -to io_tx_b[10]
-set_location_assignment PIN_58 -to io_tx_b[11]
-set_location_assignment PIN_57 -to io_tx_b[12]
-set_location_assignment PIN_56 -to io_tx_b[13]
-set_location_assignment PIN_55 -to io_tx_b[14]
-set_location_assignment PIN_152 -to master_clk
-set_location_assignment PIN_144 -to rx_a_a[0]
-set_location_assignment PIN_143 -to rx_a_a[1]
-set_location_assignment PIN_141 -to rx_a_a[2]
-set_location_assignment PIN_140 -to rx_a_a[3]
-set_location_assignment PIN_139 -to rx_a_a[4]
-set_location_assignment PIN_138 -to rx_a_a[5]
-set_location_assignment PIN_137 -to rx_a_a[6]
-set_location_assignment PIN_136 -to rx_a_a[7]
-set_location_assignment PIN_135 -to rx_a_a[8]
-set_location_assignment PIN_134 -to rx_a_a[9]
-set_location_assignment PIN_133 -to rx_a_a[10]
-set_location_assignment PIN_132 -to rx_a_a[11]
-set_location_assignment PIN_23 -to rx_a_b[0]
-set_location_assignment PIN_21 -to rx_a_b[1]
-set_location_assignment PIN_20 -to rx_a_b[2]
-set_location_assignment PIN_19 -to rx_a_b[3]
-set_location_assignment PIN_18 -to rx_a_b[4]
-set_location_assignment PIN_17 -to rx_a_b[5]
-set_location_assignment PIN_16 -to rx_a_b[6]
-set_location_assignment PIN_15 -to rx_a_b[7]
-set_location_assignment PIN_14 -to rx_a_b[8]
-set_location_assignment PIN_13 -to rx_a_b[9]
-set_location_assignment PIN_12 -to rx_a_b[10]
-set_location_assignment PIN_11 -to rx_a_b[11]
-set_location_assignment PIN_131 -to rx_b_a[0]
-set_location_assignment PIN_128 -to rx_b_a[1]
-set_location_assignment PIN_127 -to rx_b_a[2]
-set_location_assignment PIN_126 -to rx_b_a[3]
-set_location_assignment PIN_125 -to rx_b_a[4]
-set_location_assignment PIN_124 -to rx_b_a[5]
-set_location_assignment PIN_123 -to rx_b_a[6]
-set_location_assignment PIN_122 -to rx_b_a[7]
-set_location_assignment PIN_121 -to rx_b_a[8]
-set_location_assignment PIN_120 -to rx_b_a[9]
-set_location_assignment PIN_119 -to rx_b_a[10]
-set_location_assignment PIN_118 -to rx_b_a[11]
-set_location_assignment PIN_8 -to rx_b_b[0]
-set_location_assignment PIN_7 -to rx_b_b[1]
-set_location_assignment PIN_6 -to rx_b_b[2]
-set_location_assignment PIN_5 -to rx_b_b[3]
-set_location_assignment PIN_4 -to rx_b_b[4]
-set_location_assignment PIN_3 -to rx_b_b[5]
-set_location_assignment PIN_2 -to rx_b_b[6]
-set_location_assignment PIN_240 -to rx_b_b[7]
-set_location_assignment PIN_239 -to rx_b_b[8]
-set_location_assignment PIN_238 -to rx_b_b[9]
-set_location_assignment PIN_237 -to rx_b_b[10]
-set_location_assignment PIN_236 -to rx_b_b[11]
-set_location_assignment PIN_156 -to SDO
-set_location_assignment PIN_153 -to SEN_FPGA
-set_location_assignment PIN_159 -to tx_a[0]
-set_location_assignment PIN_160 -to tx_a[1]
-set_location_assignment PIN_161 -to tx_a[2]
-set_location_assignment PIN_162 -to tx_a[3]
-set_location_assignment PIN_163 -to tx_a[4]
-set_location_assignment PIN_164 -to tx_a[5]
-set_location_assignment PIN_165 -to tx_a[6]
-set_location_assignment PIN_166 -to tx_a[7]
-set_location_assignment PIN_167 -to tx_a[8]
-set_location_assignment PIN_168 -to tx_a[9]
-set_location_assignment PIN_169 -to tx_a[10]
-set_location_assignment PIN_170 -to tx_a[11]
-set_location_assignment PIN_173 -to tx_a[12]
-set_location_assignment PIN_174 -to tx_a[13]
-set_location_assignment PIN_38 -to tx_b[0]
-set_location_assignment PIN_39 -to tx_b[1]
-set_location_assignment PIN_41 -to tx_b[2]
-set_location_assignment PIN_42 -to tx_b[3]
-set_location_assignment PIN_43 -to tx_b[4]
-set_location_assignment PIN_44 -to tx_b[5]
-set_location_assignment PIN_45 -to tx_b[6]
-set_location_assignment PIN_46 -to tx_b[7]
-set_location_assignment PIN_47 -to tx_b[8]
-set_location_assignment PIN_48 -to tx_b[9]
-set_location_assignment PIN_49 -to tx_b[10]
-set_location_assignment PIN_50 -to tx_b[11]
-set_location_assignment PIN_53 -to tx_b[12]
-set_location_assignment PIN_54 -to tx_b[13]
-set_location_assignment PIN_158 -to TXSYNC_A
-set_location_assignment PIN_37 -to TXSYNC_B
-set_location_assignment PIN_235 -to io_rx_b[15]
-set_location_assignment PIN_24 -to io_tx_b[15]
-set_location_assignment PIN_213 -to io_rx_a[15]
-set_location_assignment PIN_194 -to io_tx_a[15]
-set_location_assignment PIN_1 -to MYSTERY_SIGNAL
-
-# Classic Timing Assignments
-# ==========================
-set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF
-set_global_assignment -name MAX_SCC_SIZE 50
-
-# Analysis & Synthesis Assignments
-# ================================
-set_global_assignment -name SAVE_DISK_SPACE OFF
-set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP"
-set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240
-set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
-set_global_assignment -name FAMILY Cyclone
-set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE BALANCED
-set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED
-set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED
-set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
-set_global_assignment -name USER_LIBRARIES "h:\\gnuradio\\trunk\\usrp\\fpga\\megacells"
-set_global_assignment -name AUTO_ENABLE_SMART_COMPILE ON
-set_global_assignment -name TOP_LEVEL_ENTITY usrp_radar_mono
-
-# Fitter Assignments
-# ==================
-set_global_assignment -name DEVICE EP1C12Q240C8
-set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "PASSIVE SERIAL"
-set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
-set_global_assignment -name OPTIMIZE_TIMING "NORMAL COMPILATION"
-set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF
-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF
-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
-set_global_assignment -name IO_PLACEMENT_OPTIMIZATION ON
-set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL
-set_global_assignment -name INC_PLC_MODE OFF
-set_global_assignment -name ROUTING_BACK_ANNOTATION_MODE OFF
-set_instance_assignment -name IO_STANDARD LVTTL -to usbdata[12]
-set_global_assignment -name STRATIX_DEVICE_IO_STANDARD LVTTL
-set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
-
-# EDA Netlist Writer Assignments
-# ==============================
-set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
-set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<NONE>"
-set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<NONE>"
-set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<NONE>"
-set_global_assignment -name EDA_RESYNTHESIS_TOOL "<NONE>"
-
-# Assembler Assignments
-# =====================
-set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
-set_global_assignment -name GENERATE_RBF_FILE ON
-set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
-set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF
-
-# Simulator Assignments
-# =====================
-set_global_assignment -name START_TIME "0 ns"
-set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE
-
-# Design Assistant Assignments
-# ============================
-set_global_assignment -name DRC_REPORT_TOP_FANOUT OFF
-set_global_assignment -name DRC_REPORT_FANOUT_EXCEEDING OFF
-set_global_assignment -name ASSG_CAT OFF
-set_global_assignment -name ASSG_RULE_MISSING_FMAX OFF
-set_global_assignment -name ASSG_RULE_MISSING_TIMING OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_ASYN_RAM OFF
-set_global_assignment -name CLK_CAT OFF
-set_global_assignment -name CLK_RULE_COMB_CLOCK OFF
-set_global_assignment -name CLK_RULE_INV_CLOCK OFF
-set_global_assignment -name CLK_RULE_GATING_SCHEME OFF
-set_global_assignment -name CLK_RULE_INPINS_CLKNET OFF
-set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES OFF
-set_global_assignment -name CLK_RULE_MIX_EDGES OFF
-set_global_assignment -name RESET_CAT OFF
-set_global_assignment -name RESET_RULE_INPINS_RESETNET OFF
-set_global_assignment -name RESET_RULE_UNSYNCH_EXRESET OFF
-set_global_assignment -name RESET_RULE_IMSYNCH_EXRESET OFF
-set_global_assignment -name RESET_RULE_COMB_ASYNCH_RESET OFF
-set_global_assignment -name RESET_RULE_UNSYNCH_ASYNCH_DOMAIN OFF
-set_global_assignment -name RESET_RULE_IMSYNCH_ASYNCH_DOMAIN OFF
-set_global_assignment -name TIMING_CAT OFF
-set_global_assignment -name TIMING_RULE_SHIFT_REG OFF
-set_global_assignment -name TIMING_RULE_COIN_CLKEDGE OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE OFF
-set_global_assignment -name NONSYNCHSTRUCT_CAT OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_COMBLOOP OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_REG_LOOP OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_DELAY_CHAIN OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_RIPPLE_CLK OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_SRLATCH OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED OFF
-set_global_assignment -name SIGNALRACE_CAT OFF
-set_global_assignment -name ACLK_CAT OFF
-set_global_assignment -name ACLK_RULE_NO_SZER_ACLK_DOMAIN OFF
-set_global_assignment -name ACLK_RULE_SZER_BTW_ACLK_DOMAIN OFF
-set_global_assignment -name ACLK_RULE_IMSZER_ADOMAIN OFF
-set_global_assignment -name HCPY_CAT OFF
-set_global_assignment -name HCPY_VREF_PINS OFF
-set_global_assignment -name ENABLE_DA_RULE "C101, C102, C103, C104, C105, C106, R101, R102, R103, R104, R105, T101, T102, A101, A102, A103, A104, A105, A106, A107, A108, A109, A110, S101, S102, D101, D102, D103, H102"
-set_global_assignment -name DISABLE_DA_RULE H101
-
-# SignalTap II Assignments
-# ========================
-set_global_assignment -name HUB_ENTITY_NAME SLD_HUB
-set_global_assignment -name HUB_INSTANCE_NAME SLD_HUB_INST
-set_global_assignment -name ENABLE_SIGNALTAP OFF
-
-# LogicLock Region Assignments
-# ============================
-set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT OFF
-
-# start CLOCK(SCLK)
-# -----------------
-
-       # Classic Timing Assignments
-       # ==========================
-set_global_assignment -name DUTY_CYCLE 50 -section_id SCLK
-set_global_assignment -name FMAX_REQUIREMENT "1 MHz" -section_id SCLK
-
-# end CLOCK(SCLK)
-# ---------------
-
-# start CLOCK(master_clk)
-# -----------------------
-
-       # Classic Timing Assignments
-       # ==========================
-set_global_assignment -name DUTY_CYCLE 50 -section_id master_clk
-set_global_assignment -name FMAX_REQUIREMENT "64 MHz" -section_id master_clk
-
-# end CLOCK(master_clk)
-# ---------------------
-
-# start CLOCK(usbclk)
-# -------------------
-
-       # Classic Timing Assignments
-       # ==========================
-set_global_assignment -name DUTY_CYCLE 50 -section_id usbclk
-set_global_assignment -name FMAX_REQUIREMENT "48 MHz" -section_id usbclk
-
-# end CLOCK(usbclk)
-# -----------------
-
-# -----------------------------
-# start ENTITY(usrp_radar_mono)
-
-       # Classic Timing Assignments
-       # ==========================
-set_instance_assignment -name CLOCK_SETTINGS SCLK -to SCLK
-set_instance_assignment -name CLOCK_SETTINGS usbclk -to usbclk
-set_instance_assignment -name CLOCK_SETTINGS master_clk -to master_clk
-
-       # start DESIGN_PARTITION(Top)
-       # ---------------------------
-
-               # Incremental Compilation Assignments
-               # ===================================
-set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-
-       # end DESIGN_PARTITION(Top)
-       # -------------------------
-
-# end ENTITY(usrp_radar_mono)
-# ---------------------------
-set_global_assignment -name VERILOG_FILE usrp_radar_mono.v
-set_global_assignment -name VERILOG_FILE dacpll.v
-set_global_assignment -name VERILOG_FILE ../lib/cordic_nco.v
-set_global_assignment -name VERILOG_FILE ../lib/dac_interface.v
-set_global_assignment -name VERILOG_FILE ../lib/fifo32_2k.v
-set_global_assignment -name VERILOG_FILE ../lib/radar_control.v
-set_global_assignment -name VERILOG_FILE ../lib/radar_rx.v
-set_global_assignment -name VERILOG_FILE ../lib/radar_tx.v
-set_global_assignment -name VERILOG_FILE ../lib/radar.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/adc_interface.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/atr_delay.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/bidir_reg.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/clk_divider.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/cordic_stage.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/cordic.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/gen_sync.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/io_pins.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/master_control.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/rssi.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/rx_buffer.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/rx_dcoffset.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/serial_io.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/setting_reg.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/strobe_gen.v
\ No newline at end of file

diff --git a/gr-sounder/src/fpga/top/usrp_sounder.qpf b/gr-sounder/src/fpga/top/usrp_sounder.qpf
deleted file mode 100644 (file)
index aa75e96..0000000
--- a/gr-sounder/src/fpga/top/usrp_sounder.qpf
+++ /dev/null
@@ -1,29 +0,0 @@
-# Copyright (C) 1991-2004 Altera Corporation
-# Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
-# support information,  device programming or simulation file,  and any other
-# associated  documentation or information  provided by  Altera  or a partner
-# under  Altera's   Megafunction   Partnership   Program  may  be  used  only
-# to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
-# other  use  of such  megafunction  design,  netlist,  support  information,
-# device programming or simulation file,  or any other  related documentation
-# or information  is prohibited  for  any  other purpose,  including, but not
-# limited to  modification,  reverse engineering,  de-compiling, or use  with
-# any other  silicon devices,  unless such use is  explicitly  licensed under
-# a separate agreement with  Altera  or a megafunction partner.  Title to the
-# intellectual property,  including patents,  copyrights,  trademarks,  trade
-# secrets,  or maskworks,  embodied in any such megafunction design, netlist,
-# support  information,  device programming or simulation file,  or any other
-# related documentation or information provided by  Altera  or a megafunction
-# partner, remains with Altera, the megafunction partner, or their respective
-# licensors. No other licenses, including any licenses needed under any third
-# party's intellectual property, are provided herein.
-
-
-
-QUARTUS_VERSION = "7.0"
-DATE = "09:00:00  April 17, 2007"
-
-
-# Active Revisions
-
-PROJECT_REVISION = "usrp_sounder"

diff --git a/usrp/fpga/toplevel/mrfm/mrfm.qpf b/usrp/fpga/toplevel/mrfm/mrfm.qpf
deleted file mode 100644 (file)
index 9591408..0000000
--- a/usrp/fpga/toplevel/mrfm/mrfm.qpf
+++ /dev/null
@@ -1,29 +0,0 @@
-# Copyright (C) 1991-2004 Altera Corporation
-# Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
-# support information,  device programming or simulation file,  and any other
-# associated  documentation or information  provided by  Altera  or a partner
-# under  Altera's   Megafunction   Partnership   Program  may  be  used  only
-# to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
-# other  use  of such  megafunction  design,  netlist,  support  information,
-# device programming or simulation file,  or any other  related documentation
-# or information  is prohibited  for  any  other purpose,  including, but not
-# limited to  modification,  reverse engineering,  de-compiling, or use  with
-# any other  silicon devices,  unless such use is  explicitly  licensed under
-# a separate agreement with  Altera  or a megafunction partner.  Title to the
-# intellectual property,  including patents,  copyrights,  trademarks,  trade
-# secrets,  or maskworks,  embodied in any such megafunction design, netlist,
-# support  information,  device programming or simulation file,  or any other
-# related documentation or information provided by  Altera  or a megafunction
-# partner, remains with Altera, the megafunction partner, or their respective
-# licensors. No other licenses, including any licenses needed under any third
-# party's intellectual property, are provided herein.
-
-
-
-QUARTUS_VERSION = "4.0"
-DATE = "17:10:11  December 20, 2004"
-
-
-# Active Revisions
-
-PROJECT_REVISION = "mrfm"

diff --git a/usrp/fpga/toplevel/mrfm/mrfm.qsf b/usrp/fpga/toplevel/mrfm/mrfm.qsf
deleted file mode 100644 (file)
index ba1ae02..0000000
--- a/usrp/fpga/toplevel/mrfm/mrfm.qsf
+++ /dev/null
@@ -1,411 +0,0 @@
-# Copyright (C) 1991-2005 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic       
-# functions, and any output files any of the foregoing           
-# (including device programming or simulation files), and any    
-# associated documentation or information are expressly subject  
-# to the terms and conditions of the Altera Program License      
-# Subscription Agreement, Altera MegaCore Function License       
-# Agreement, or other applicable license agreement, including,   
-# without limitation, that your use is for the sole purpose of   
-# programming logic devices manufactured by Altera and sold by   
-# Altera or its authorized distributors.  Please refer to the    
-# applicable agreement for further details.
-
-
-# The default values for assignments are stored in the file
-#              mrfm_assignment_defaults.qdf
-# If this file doesn't exist, and for assignments not listed, see file
-#              assignment_defaults.qdf
-
-# Altera recommends that you do not modify this file. This
-# file is updated automatically by the Quartus II software
-# and any changes you make may be lost or overwritten.
-
-
-# Project-Wide Assignments
-# ========================
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 3.0
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:14:04  JULY 13, 2003"
-set_global_assignment -name LAST_QUARTUS_VERSION "5.1 SP2"
-
-# Pin & Location Assignments
-# ==========================
-set_global_assignment -name RESERVE_PIN "AS INPUT TRI-STATED"
-set_location_assignment PIN_29 -to SCLK
-set_location_assignment PIN_117 -to SDI
-set_location_assignment PIN_28 -to usbclk
-set_location_assignment PIN_107 -to usbctl[0]
-set_location_assignment PIN_106 -to usbctl[1]
-set_location_assignment PIN_105 -to usbctl[2]
-set_location_assignment PIN_100 -to usbdata[0]
-set_location_assignment PIN_84 -to usbdata[10]
-set_location_assignment PIN_83 -to usbdata[11]
-set_location_assignment PIN_82 -to usbdata[12]
-set_location_assignment PIN_79 -to usbdata[13]
-set_location_assignment PIN_78 -to usbdata[14]
-set_location_assignment PIN_77 -to usbdata[15]
-set_location_assignment PIN_99 -to usbdata[1]
-set_location_assignment PIN_98 -to usbdata[2]
-set_location_assignment PIN_95 -to usbdata[3]
-set_location_assignment PIN_94 -to usbdata[4]
-set_location_assignment PIN_93 -to usbdata[5]
-set_location_assignment PIN_88 -to usbdata[6]
-set_location_assignment PIN_87 -to usbdata[7]
-set_location_assignment PIN_86 -to usbdata[8]
-set_location_assignment PIN_85 -to usbdata[9]
-set_location_assignment PIN_104 -to usbrdy[0]
-set_location_assignment PIN_101 -to usbrdy[1]
-set_location_assignment PIN_76 -to FX2_1
-set_location_assignment PIN_75 -to FX2_2
-set_location_assignment PIN_74 -to FX2_3
-set_location_assignment PIN_116 -to io_rx_a[0]
-set_location_assignment PIN_115 -to io_rx_a[1]
-set_location_assignment PIN_114 -to io_rx_a[2]
-set_location_assignment PIN_113 -to io_rx_a[3]
-set_location_assignment PIN_108 -to io_rx_a[4]
-set_location_assignment PIN_195 -to io_rx_a[5]
-set_location_assignment PIN_196 -to io_rx_a[6]
-set_location_assignment PIN_197 -to io_rx_a[7]
-set_location_assignment PIN_200 -to io_rx_a[8]
-set_location_assignment PIN_201 -to io_rx_a[9]
-set_location_assignment PIN_202 -to io_rx_a[10]
-set_location_assignment PIN_203 -to io_rx_a[11]
-set_location_assignment PIN_206 -to io_rx_a[12]
-set_location_assignment PIN_207 -to io_rx_a[13]
-set_location_assignment PIN_208 -to io_rx_a[14]
-set_location_assignment PIN_214 -to io_rx_b[0]
-set_location_assignment PIN_215 -to io_rx_b[1]
-set_location_assignment PIN_216 -to io_rx_b[2]
-set_location_assignment PIN_217 -to io_rx_b[3]
-set_location_assignment PIN_218 -to io_rx_b[4]
-set_location_assignment PIN_219 -to io_rx_b[5]
-set_location_assignment PIN_222 -to io_rx_b[6]
-set_location_assignment PIN_223 -to io_rx_b[7]
-set_location_assignment PIN_224 -to io_rx_b[8]
-set_location_assignment PIN_225 -to io_rx_b[9]
-set_location_assignment PIN_226 -to io_rx_b[10]
-set_location_assignment PIN_227 -to io_rx_b[11]
-set_location_assignment PIN_228 -to io_rx_b[12]
-set_location_assignment PIN_233 -to io_rx_b[13]
-set_location_assignment PIN_234 -to io_rx_b[14]
-set_location_assignment PIN_175 -to io_tx_a[0]
-set_location_assignment PIN_176 -to io_tx_a[1]
-set_location_assignment PIN_177 -to io_tx_a[2]
-set_location_assignment PIN_178 -to io_tx_a[3]
-set_location_assignment PIN_179 -to io_tx_a[4]
-set_location_assignment PIN_180 -to io_tx_a[5]
-set_location_assignment PIN_181 -to io_tx_a[6]
-set_location_assignment PIN_182 -to io_tx_a[7]
-set_location_assignment PIN_183 -to io_tx_a[8]
-set_location_assignment PIN_184 -to io_tx_a[9]
-set_location_assignment PIN_185 -to io_tx_a[10]
-set_location_assignment PIN_186 -to io_tx_a[11]
-set_location_assignment PIN_187 -to io_tx_a[12]
-set_location_assignment PIN_188 -to io_tx_a[13]
-set_location_assignment PIN_193 -to io_tx_a[14]
-set_location_assignment PIN_73 -to io_tx_b[0]
-set_location_assignment PIN_68 -to io_tx_b[1]
-set_location_assignment PIN_67 -to io_tx_b[2]
-set_location_assignment PIN_66 -to io_tx_b[3]
-set_location_assignment PIN_65 -to io_tx_b[4]
-set_location_assignment PIN_64 -to io_tx_b[5]
-set_location_assignment PIN_63 -to io_tx_b[6]
-set_location_assignment PIN_62 -to io_tx_b[7]
-set_location_assignment PIN_61 -to io_tx_b[8]
-set_location_assignment PIN_60 -to io_tx_b[9]
-set_location_assignment PIN_59 -to io_tx_b[10]
-set_location_assignment PIN_58 -to io_tx_b[11]
-set_location_assignment PIN_57 -to io_tx_b[12]
-set_location_assignment PIN_56 -to io_tx_b[13]
-set_location_assignment PIN_55 -to io_tx_b[14]
-set_location_assignment PIN_152 -to master_clk
-set_location_assignment PIN_144 -to rx_a_a[0]
-set_location_assignment PIN_143 -to rx_a_a[1]
-set_location_assignment PIN_141 -to rx_a_a[2]
-set_location_assignment PIN_140 -to rx_a_a[3]
-set_location_assignment PIN_139 -to rx_a_a[4]
-set_location_assignment PIN_138 -to rx_a_a[5]
-set_location_assignment PIN_137 -to rx_a_a[6]
-set_location_assignment PIN_136 -to rx_a_a[7]
-set_location_assignment PIN_135 -to rx_a_a[8]
-set_location_assignment PIN_134 -to rx_a_a[9]
-set_location_assignment PIN_133 -to rx_a_a[10]
-set_location_assignment PIN_132 -to rx_a_a[11]
-set_location_assignment PIN_23 -to rx_a_b[0]
-set_location_assignment PIN_21 -to rx_a_b[1]
-set_location_assignment PIN_20 -to rx_a_b[2]
-set_location_assignment PIN_19 -to rx_a_b[3]
-set_location_assignment PIN_18 -to rx_a_b[4]
-set_location_assignment PIN_17 -to rx_a_b[5]
-set_location_assignment PIN_16 -to rx_a_b[6]
-set_location_assignment PIN_15 -to rx_a_b[7]
-set_location_assignment PIN_14 -to rx_a_b[8]
-set_location_assignment PIN_13 -to rx_a_b[9]
-set_location_assignment PIN_12 -to rx_a_b[10]
-set_location_assignment PIN_11 -to rx_a_b[11]
-set_location_assignment PIN_131 -to rx_b_a[0]
-set_location_assignment PIN_128 -to rx_b_a[1]
-set_location_assignment PIN_127 -to rx_b_a[2]
-set_location_assignment PIN_126 -to rx_b_a[3]
-set_location_assignment PIN_125 -to rx_b_a[4]
-set_location_assignment PIN_124 -to rx_b_a[5]
-set_location_assignment PIN_123 -to rx_b_a[6]
-set_location_assignment PIN_122 -to rx_b_a[7]
-set_location_assignment PIN_121 -to rx_b_a[8]
-set_location_assignment PIN_120 -to rx_b_a[9]
-set_location_assignment PIN_119 -to rx_b_a[10]
-set_location_assignment PIN_118 -to rx_b_a[11]
-set_location_assignment PIN_8 -to rx_b_b[0]
-set_location_assignment PIN_7 -to rx_b_b[1]
-set_location_assignment PIN_6 -to rx_b_b[2]
-set_location_assignment PIN_5 -to rx_b_b[3]
-set_location_assignment PIN_4 -to rx_b_b[4]
-set_location_assignment PIN_3 -to rx_b_b[5]
-set_location_assignment PIN_2 -to rx_b_b[6]
-set_location_assignment PIN_240 -to rx_b_b[7]
-set_location_assignment PIN_239 -to rx_b_b[8]
-set_location_assignment PIN_238 -to rx_b_b[9]
-set_location_assignment PIN_237 -to rx_b_b[10]
-set_location_assignment PIN_236 -to rx_b_b[11]
-set_location_assignment PIN_156 -to SDO
-set_location_assignment PIN_153 -to SEN_FPGA
-set_location_assignment PIN_159 -to tx_a[0]
-set_location_assignment PIN_160 -to tx_a[1]
-set_location_assignment PIN_161 -to tx_a[2]
-set_location_assignment PIN_162 -to tx_a[3]
-set_location_assignment PIN_163 -to tx_a[4]
-set_location_assignment PIN_164 -to tx_a[5]
-set_location_assignment PIN_165 -to tx_a[6]
-set_location_assignment PIN_166 -to tx_a[7]
-set_location_assignment PIN_167 -to tx_a[8]
-set_location_assignment PIN_168 -to tx_a[9]
-set_location_assignment PIN_169 -to tx_a[10]
-set_location_assignment PIN_170 -to tx_a[11]
-set_location_assignment PIN_173 -to tx_a[12]
-set_location_assignment PIN_174 -to tx_a[13]
-set_location_assignment PIN_38 -to tx_b[0]
-set_location_assignment PIN_39 -to tx_b[1]
-set_location_assignment PIN_41 -to tx_b[2]
-set_location_assignment PIN_42 -to tx_b[3]
-set_location_assignment PIN_43 -to tx_b[4]
-set_location_assignment PIN_44 -to tx_b[5]
-set_location_assignment PIN_45 -to tx_b[6]
-set_location_assignment PIN_46 -to tx_b[7]
-set_location_assignment PIN_47 -to tx_b[8]
-set_location_assignment PIN_48 -to tx_b[9]
-set_location_assignment PIN_49 -to tx_b[10]
-set_location_assignment PIN_50 -to tx_b[11]
-set_location_assignment PIN_53 -to tx_b[12]
-set_location_assignment PIN_54 -to tx_b[13]
-set_location_assignment PIN_158 -to TXSYNC_A
-set_location_assignment PIN_37 -to TXSYNC_B
-set_location_assignment PIN_235 -to io_rx_b[15]
-set_location_assignment PIN_24 -to io_tx_b[15]
-set_location_assignment PIN_213 -to io_rx_a[15]
-set_location_assignment PIN_194 -to io_tx_a[15]
-set_location_assignment PIN_1 -to MYSTERY_SIGNAL
-
-# Timing Assignments
-# ==================
-set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF
-
-# Analysis & Synthesis Assignments
-# ================================
-set_global_assignment -name SAVE_DISK_SPACE OFF
-set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP"
-set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240
-set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
-set_global_assignment -name FAMILY Cyclone
-set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE SPEED
-set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED
-set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED
-set_global_assignment -name TOP_LEVEL_ENTITY mrfm
-set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
-set_global_assignment -name USER_LIBRARIES "e:\\usrp\\fpga\\megacells"
-set_global_assignment -name AUTO_ENABLE_SMART_COMPILE ON
-
-# Fitter Assignments
-# ==================
-set_global_assignment -name DEVICE EP1C12Q240C8
-set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "PASSIVE SERIAL"
-set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
-set_global_assignment -name OPTIMIZE_TIMING "NORMAL COMPILATION"
-set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
-set_global_assignment -name IO_PLACEMENT_OPTIMIZATION OFF
-set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
-set_global_assignment -name INC_PLC_MODE OFF
-set_global_assignment -name ROUTING_BACK_ANNOTATION_MODE OFF
-set_instance_assignment -name IO_STANDARD LVTTL -to usbdata[12]
-set_global_assignment -name STRATIX_DEVICE_IO_STANDARD LVTTL
-set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
-
-# Timing Analysis Assignments
-# ===========================
-set_global_assignment -name MAX_SCC_SIZE 50
-
-# EDA Netlist Writer Assignments
-# ==============================
-set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
-set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<NONE>"
-set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<NONE>"
-set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<NONE>"
-set_global_assignment -name EDA_RESYNTHESIS_TOOL "<NONE>"
-
-# Assembler Assignments
-# =====================
-set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
-set_global_assignment -name GENERATE_RBF_FILE ON
-set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
-set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF
-
-# Simulator Assignments
-# =====================
-set_global_assignment -name START_TIME "0 ns"
-set_global_assignment -name GLITCH_INTERVAL "1 ns"
-
-# Design Assistant Assignments
-# ============================
-set_global_assignment -name DRC_REPORT_TOP_FANOUT OFF
-set_global_assignment -name DRC_REPORT_FANOUT_EXCEEDING OFF
-set_global_assignment -name ASSG_CAT OFF
-set_global_assignment -name ASSG_RULE_MISSING_FMAX OFF
-set_global_assignment -name ASSG_RULE_MISSING_TIMING OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_ASYN_RAM OFF
-set_global_assignment -name CLK_CAT OFF
-set_global_assignment -name CLK_RULE_COMB_CLOCK OFF
-set_global_assignment -name CLK_RULE_INV_CLOCK OFF
-set_global_assignment -name CLK_RULE_GATING_SCHEME OFF
-set_global_assignment -name CLK_RULE_INPINS_CLKNET OFF
-set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES OFF
-set_global_assignment -name CLK_RULE_MIX_EDGES OFF
-set_global_assignment -name RESET_CAT OFF
-set_global_assignment -name RESET_RULE_INPINS_RESETNET OFF
-set_global_assignment -name RESET_RULE_UNSYNCH_EXRESET OFF
-set_global_assignment -name RESET_RULE_IMSYNCH_EXRESET OFF
-set_global_assignment -name RESET_RULE_COMB_ASYNCH_RESET OFF
-set_global_assignment -name RESET_RULE_UNSYNCH_ASYNCH_DOMAIN OFF
-set_global_assignment -name RESET_RULE_IMSYNCH_ASYNCH_DOMAIN OFF
-set_global_assignment -name TIMING_CAT OFF
-set_global_assignment -name TIMING_RULE_SHIFT_REG OFF
-set_global_assignment -name TIMING_RULE_COIN_CLKEDGE OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE OFF
-set_global_assignment -name NONSYNCHSTRUCT_CAT OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_COMBLOOP OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_REG_LOOP OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_DELAY_CHAIN OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_RIPPLE_CLK OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_SRLATCH OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED OFF
-set_global_assignment -name SIGNALRACE_CAT OFF
-set_global_assignment -name ACLK_CAT OFF
-set_global_assignment -name ACLK_RULE_NO_SZER_ACLK_DOMAIN OFF
-set_global_assignment -name ACLK_RULE_SZER_BTW_ACLK_DOMAIN OFF
-set_global_assignment -name ACLK_RULE_IMSZER_ADOMAIN OFF
-set_global_assignment -name HCPY_CAT OFF
-set_global_assignment -name HCPY_VREF_PINS OFF
-
-# SignalTap II Assignments
-# ========================
-set_global_assignment -name HUB_ENTITY_NAME SLD_HUB
-set_global_assignment -name HUB_INSTANCE_NAME SLD_HUB_INST
-set_global_assignment -name ENABLE_SIGNALTAP OFF
-
-# LogicLock Region Assignments
-# ============================
-set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT OFF
-
-# -----------------
-# start CLOCK(SCLK)
-
-       # Timing Assignments
-       # ==================
-set_global_assignment -name DUTY_CYCLE 50 -section_id SCLK
-set_global_assignment -name FMAX_REQUIREMENT "1 MHz" -section_id SCLK
-set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id SCLK
-
-# end CLOCK(SCLK)
-# ---------------
-
-# -----------------------
-# start CLOCK(master_clk)
-
-       # Timing Assignments
-       # ==================
-set_global_assignment -name DUTY_CYCLE 50 -section_id master_clk
-set_global_assignment -name FMAX_REQUIREMENT "64 MHz" -section_id master_clk
-set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id master_clk
-
-# end CLOCK(master_clk)
-# ---------------------
-
-# -------------------
-# start CLOCK(usbclk)
-
-       # Timing Assignments
-       # ==================
-set_global_assignment -name DUTY_CYCLE 50 -section_id usbclk
-set_global_assignment -name FMAX_REQUIREMENT "48 MHz" -section_id usbclk
-set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id usbclk
-
-# end CLOCK(usbclk)
-# -----------------
-
-# ----------------------
-# start ENTITY(mrfm)
-
-       # Timing Assignments
-       # ==================
-set_instance_assignment -name CLOCK_SETTINGS SCLK -to SCLK
-set_instance_assignment -name CLOCK_SETTINGS usbclk -to usbclk
-set_instance_assignment -name CLOCK_SETTINGS master_clk -to master_clk
-
-# end ENTITY(mrfm)
-# --------------------
-
-
-set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
-set_global_assignment -name SMART_RECOMPILE ON
-set_global_assignment -name VERILOG_FILE mrfm.vh
-set_global_assignment -name VERILOG_FILE biquad_2stage.v
-set_global_assignment -name VERILOG_FILE mrfm_compensator.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/ram16.v
-set_global_assignment -name VERILOG_FILE mrfm_proc.v
-set_global_assignment -name VERILOG_FILE ../../megacells/fifo_4k.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/acc.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/mult.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/ram16_2sum.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/coeff_rom.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/halfband_decim.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/mac.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/coeff_ram.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/tx_chain.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_dcoffset.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/adc_interface.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/io_pins.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/setting_reg.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/bidir_reg.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_int_shifter.v
-set_global_assignment -name VERILOG_FILE ../../megacells/clk_doubler.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/gen_sync.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/master_control.v
-set_global_assignment -name VERILOG_FILE ../../megacells/fifo_2k.v
-set_global_assignment -name VERILOG_FILE ../../megacells/bustri.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_buffer.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/tx_buffer.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/phase_acc.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_interp.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_decim.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/cordic_stage.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/cordic.v
-set_global_assignment -name VERILOG_FILE mrfm.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/clk_divider.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/serial_io.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/strobe_gen.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/sign_extend.v
-set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
\ No newline at end of file

diff --git a/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qpf b/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qpf
deleted file mode 100644 (file)
index f6220e3..0000000
--- a/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qpf
+++ /dev/null
@@ -1,29 +0,0 @@
-# Copyright (C) 1991-2004 Altera Corporation
-# Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
-# support information,  device programming or simulation file,  and any other
-# associated  documentation or information  provided by  Altera  or a partner
-# under  Altera's   Megafunction   Partnership   Program  may  be  used  only
-# to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
-# other  use  of such  megafunction  design,  netlist,  support  information,
-# device programming or simulation file,  or any other  related documentation
-# or information  is prohibited  for  any  other purpose,  including, but not
-# limited to  modification,  reverse engineering,  de-compiling, or use  with
-# any other  silicon devices,  unless such use is  explicitly  licensed under
-# a separate agreement with  Altera  or a megafunction partner.  Title to the
-# intellectual property,  including patents,  copyrights,  trademarks,  trade
-# secrets,  or maskworks,  embodied in any such megafunction design, netlist,
-# support  information,  device programming or simulation file,  or any other
-# related documentation or information provided by  Altera  or a megafunction
-# partner, remains with Altera, the megafunction partner, or their respective
-# licensors. No other licenses, including any licenses needed under any third
-# party's intellectual property, are provided herein.
-
-
-
-QUARTUS_VERSION = "4.0"
-DATE = "17:10:11  December 20, 2004"
-
-
-# Active Revisions
-
-PROJECT_REVISION = "usrp_inband_usb"

diff --git a/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qsf b/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qsf
deleted file mode 100644 (file)
index ae0807f..0000000
--- a/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qsf
+++ /dev/null
@@ -1,423 +0,0 @@
-# Copyright (C) 1991-2005 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic       
-# functions, and any output files any of the foregoing           
-# (including device programming or simulation files), and any    
-# associated documentation or information are expressly subject  
-# to the terms and conditions of the Altera Program License      
-# Subscription Agreement, Altera MegaCore Function License       
-# Agreement, or other applicable license agreement, including,   
-# without limitation, that your use is for the sole purpose of   
-# programming logic devices manufactured by Altera and sold by   
-# Altera or its authorized distributors.  Please refer to the    
-# applicable agreement for further details.
-
-
-# The default values for assignments are stored in the file
-#              usrp_inband_usb_assignment_defaults.qdf
-# If this file doesn't exist, and for assignments not listed, see file
-#              assignment_defaults.qdf
-
-# Altera recommends that you do not modify this file. This
-# file is updated automatically by the Quartus II software
-# and any changes you make may be lost or overwritten.
-
-
-# Project-Wide Assignments
-# ========================
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 3.0
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:14:04  JULY 13, 2003"
-set_global_assignment -name LAST_QUARTUS_VERSION "7.2 SP2"
-
-# Pin & Location Assignments
-# ==========================
-set_global_assignment -name RESERVE_PIN "AS INPUT TRI-STATED"
-set_location_assignment PIN_29 -to SCLK
-set_location_assignment PIN_117 -to SDI
-set_location_assignment PIN_28 -to usbclk
-set_location_assignment PIN_107 -to usbctl[0]
-set_location_assignment PIN_106 -to usbctl[1]
-set_location_assignment PIN_105 -to usbctl[2]
-set_location_assignment PIN_100 -to usbdata[0]
-set_location_assignment PIN_84 -to usbdata[10]
-set_location_assignment PIN_83 -to usbdata[11]
-set_location_assignment PIN_82 -to usbdata[12]
-set_location_assignment PIN_79 -to usbdata[13]
-set_location_assignment PIN_78 -to usbdata[14]
-set_location_assignment PIN_77 -to usbdata[15]
-set_location_assignment PIN_99 -to usbdata[1]
-set_location_assignment PIN_98 -to usbdata[2]
-set_location_assignment PIN_95 -to usbdata[3]
-set_location_assignment PIN_94 -to usbdata[4]
-set_location_assignment PIN_93 -to usbdata[5]
-set_location_assignment PIN_88 -to usbdata[6]
-set_location_assignment PIN_87 -to usbdata[7]
-set_location_assignment PIN_86 -to usbdata[8]
-set_location_assignment PIN_85 -to usbdata[9]
-set_location_assignment PIN_104 -to usbrdy[0]
-set_location_assignment PIN_101 -to usbrdy[1]
-set_location_assignment PIN_76 -to FX2_1
-set_location_assignment PIN_75 -to FX2_2
-set_location_assignment PIN_74 -to FX2_3
-set_location_assignment PIN_116 -to io_rx_a[0]
-set_location_assignment PIN_115 -to io_rx_a[1]
-set_location_assignment PIN_114 -to io_rx_a[2]
-set_location_assignment PIN_113 -to io_rx_a[3]
-set_location_assignment PIN_108 -to io_rx_a[4]
-set_location_assignment PIN_195 -to io_rx_a[5]
-set_location_assignment PIN_196 -to io_rx_a[6]
-set_location_assignment PIN_197 -to io_rx_a[7]
-set_location_assignment PIN_200 -to io_rx_a[8]
-set_location_assignment PIN_201 -to io_rx_a[9]
-set_location_assignment PIN_202 -to io_rx_a[10]
-set_location_assignment PIN_203 -to io_rx_a[11]
-set_location_assignment PIN_206 -to io_rx_a[12]
-set_location_assignment PIN_207 -to io_rx_a[13]
-set_location_assignment PIN_208 -to io_rx_a[14]
-set_location_assignment PIN_214 -to io_rx_b[0]
-set_location_assignment PIN_215 -to io_rx_b[1]
-set_location_assignment PIN_216 -to io_rx_b[2]
-set_location_assignment PIN_217 -to io_rx_b[3]
-set_location_assignment PIN_218 -to io_rx_b[4]
-set_location_assignment PIN_219 -to io_rx_b[5]
-set_location_assignment PIN_222 -to io_rx_b[6]
-set_location_assignment PIN_223 -to io_rx_b[7]
-set_location_assignment PIN_224 -to io_rx_b[8]
-set_location_assignment PIN_225 -to io_rx_b[9]
-set_location_assignment PIN_226 -to io_rx_b[10]
-set_location_assignment PIN_227 -to io_rx_b[11]
-set_location_assignment PIN_228 -to io_rx_b[12]
-set_location_assignment PIN_233 -to io_rx_b[13]
-set_location_assignment PIN_234 -to io_rx_b[14]
-set_location_assignment PIN_175 -to io_tx_a[0]
-set_location_assignment PIN_176 -to io_tx_a[1]
-set_location_assignment PIN_177 -to io_tx_a[2]
-set_location_assignment PIN_178 -to io_tx_a[3]
-set_location_assignment PIN_179 -to io_tx_a[4]
-set_location_assignment PIN_180 -to io_tx_a[5]
-set_location_assignment PIN_181 -to io_tx_a[6]
-set_location_assignment PIN_182 -to io_tx_a[7]
-set_location_assignment PIN_183 -to io_tx_a[8]
-set_location_assignment PIN_184 -to io_tx_a[9]
-set_location_assignment PIN_185 -to io_tx_a[10]
-set_location_assignment PIN_186 -to io_tx_a[11]
-set_location_assignment PIN_187 -to io_tx_a[12]
-set_location_assignment PIN_188 -to io_tx_a[13]
-set_location_assignment PIN_193 -to io_tx_a[14]
-set_location_assignment PIN_73 -to io_tx_b[0]
-set_location_assignment PIN_68 -to io_tx_b[1]
-set_location_assignment PIN_67 -to io_tx_b[2]
-set_location_assignment PIN_66 -to io_tx_b[3]
-set_location_assignment PIN_65 -to io_tx_b[4]
-set_location_assignment PIN_64 -to io_tx_b[5]
-set_location_assignment PIN_63 -to io_tx_b[6]
-set_location_assignment PIN_62 -to io_tx_b[7]
-set_location_assignment PIN_61 -to io_tx_b[8]
-set_location_assignment PIN_60 -to io_tx_b[9]
-set_location_assignment PIN_59 -to io_tx_b[10]
-set_location_assignment PIN_58 -to io_tx_b[11]
-set_location_assignment PIN_57 -to io_tx_b[12]
-set_location_assignment PIN_56 -to io_tx_b[13]
-set_location_assignment PIN_55 -to io_tx_b[14]
-set_location_assignment PIN_152 -to master_clk
-set_location_assignment PIN_144 -to rx_a_a[0]
-set_location_assignment PIN_143 -to rx_a_a[1]
-set_location_assignment PIN_141 -to rx_a_a[2]
-set_location_assignment PIN_140 -to rx_a_a[3]
-set_location_assignment PIN_139 -to rx_a_a[4]
-set_location_assignment PIN_138 -to rx_a_a[5]
-set_location_assignment PIN_137 -to rx_a_a[6]
-set_location_assignment PIN_136 -to rx_a_a[7]
-set_location_assignment PIN_135 -to rx_a_a[8]
-set_location_assignment PIN_134 -to rx_a_a[9]
-set_location_assignment PIN_133 -to rx_a_a[10]
-set_location_assignment PIN_132 -to rx_a_a[11]
-set_location_assignment PIN_23 -to rx_a_b[0]
-set_location_assignment PIN_21 -to rx_a_b[1]
-set_location_assignment PIN_20 -to rx_a_b[2]
-set_location_assignment PIN_19 -to rx_a_b[3]
-set_location_assignment PIN_18 -to rx_a_b[4]
-set_location_assignment PIN_17 -to rx_a_b[5]
-set_location_assignment PIN_16 -to rx_a_b[6]
-set_location_assignment PIN_15 -to rx_a_b[7]
-set_location_assignment PIN_14 -to rx_a_b[8]
-set_location_assignment PIN_13 -to rx_a_b[9]
-set_location_assignment PIN_12 -to rx_a_b[10]
-set_location_assignment PIN_11 -to rx_a_b[11]
-set_location_assignment PIN_131 -to rx_b_a[0]
-set_location_assignment PIN_128 -to rx_b_a[1]
-set_location_assignment PIN_127 -to rx_b_a[2]
-set_location_assignment PIN_126 -to rx_b_a[3]
-set_location_assignment PIN_125 -to rx_b_a[4]
-set_location_assignment PIN_124 -to rx_b_a[5]
-set_location_assignment PIN_123 -to rx_b_a[6]
-set_location_assignment PIN_122 -to rx_b_a[7]
-set_location_assignment PIN_121 -to rx_b_a[8]
-set_location_assignment PIN_120 -to rx_b_a[9]
-set_location_assignment PIN_119 -to rx_b_a[10]
-set_location_assignment PIN_118 -to rx_b_a[11]
-set_location_assignment PIN_8 -to rx_b_b[0]
-set_location_assignment PIN_7 -to rx_b_b[1]
-set_location_assignment PIN_6 -to rx_b_b[2]
-set_location_assignment PIN_5 -to rx_b_b[3]
-set_location_assignment PIN_4 -to rx_b_b[4]
-set_location_assignment PIN_3 -to rx_b_b[5]
-set_location_assignment PIN_2 -to rx_b_b[6]
-set_location_assignment PIN_240 -to rx_b_b[7]
-set_location_assignment PIN_239 -to rx_b_b[8]
-set_location_assignment PIN_238 -to rx_b_b[9]
-set_location_assignment PIN_237 -to rx_b_b[10]
-set_location_assignment PIN_236 -to rx_b_b[11]
-set_location_assignment PIN_156 -to SDO
-set_location_assignment PIN_153 -to SEN_FPGA
-set_location_assignment PIN_159 -to tx_a[0]
-set_location_assignment PIN_160 -to tx_a[1]
-set_location_assignment PIN_161 -to tx_a[2]
-set_location_assignment PIN_162 -to tx_a[3]
-set_location_assignment PIN_163 -to tx_a[4]
-set_location_assignment PIN_164 -to tx_a[5]
-set_location_assignment PIN_165 -to tx_a[6]
-set_location_assignment PIN_166 -to tx_a[7]
-set_location_assignment PIN_167 -to tx_a[8]
-set_location_assignment PIN_168 -to tx_a[9]
-set_location_assignment PIN_169 -to tx_a[10]
-set_location_assignment PIN_170 -to tx_a[11]
-set_location_assignment PIN_173 -to tx_a[12]
-set_location_assignment PIN_174 -to tx_a[13]
-set_location_assignment PIN_38 -to tx_b[0]
-set_location_assignment PIN_39 -to tx_b[1]
-set_location_assignment PIN_41 -to tx_b[2]
-set_location_assignment PIN_42 -to tx_b[3]
-set_location_assignment PIN_43 -to tx_b[4]
-set_location_assignment PIN_44 -to tx_b[5]
-set_location_assignment PIN_45 -to tx_b[6]
-set_location_assignment PIN_46 -to tx_b[7]
-set_location_assignment PIN_47 -to tx_b[8]
-set_location_assignment PIN_48 -to tx_b[9]
-set_location_assignment PIN_49 -to tx_b[10]
-set_location_assignment PIN_50 -to tx_b[11]
-set_location_assignment PIN_53 -to tx_b[12]
-set_location_assignment PIN_54 -to tx_b[13]
-set_location_assignment PIN_158 -to TXSYNC_A
-set_location_assignment PIN_37 -to TXSYNC_B
-set_location_assignment PIN_235 -to io_rx_b[15]
-set_location_assignment PIN_24 -to io_tx_b[15]
-set_location_assignment PIN_213 -to io_rx_a[15]
-set_location_assignment PIN_194 -to io_tx_a[15]
-set_location_assignment PIN_1 -to MYSTERY_SIGNAL
-
-# Timing Assignments
-# ==================
-set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF
-
-# Analysis & Synthesis Assignments
-# ================================
-set_global_assignment -name SAVE_DISK_SPACE OFF
-set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP"
-set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240
-set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
-set_global_assignment -name FAMILY Cyclone
-set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE BALANCED
-set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED
-set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED
-set_global_assignment -name TOP_LEVEL_ENTITY usrp_inband_usb
-set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
-set_global_assignment -name USER_LIBRARIES "e:\\usrp\\fpga\\megacells"
-set_global_assignment -name AUTO_ENABLE_SMART_COMPILE ON
-
-# Fitter Assignments
-# ==================
-set_global_assignment -name DEVICE EP1C12Q240C8
-set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "PASSIVE SERIAL"
-set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
-set_global_assignment -name OPTIMIZE_TIMING "NORMAL COMPILATION"
-set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF
-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF
-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
-set_global_assignment -name IO_PLACEMENT_OPTIMIZATION OFF
-set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL
-set_global_assignment -name INC_PLC_MODE OFF
-set_global_assignment -name ROUTING_BACK_ANNOTATION_MODE OFF
-set_instance_assignment -name IO_STANDARD LVTTL -to usbdata[12]
-set_global_assignment -name STRATIX_DEVICE_IO_STANDARD LVTTL
-set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
-
-# Timing Analysis Assignments
-# ===========================
-set_global_assignment -name MAX_SCC_SIZE 50
-
-# EDA Netlist Writer Assignments
-# ==============================
-set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
-set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<NONE>"
-set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<NONE>"
-set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<NONE>"
-set_global_assignment -name EDA_RESYNTHESIS_TOOL "<NONE>"
-
-# Assembler Assignments
-# =====================
-set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
-set_global_assignment -name GENERATE_RBF_FILE ON
-set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
-set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF
-
-# Simulator Assignments
-# =====================
-set_global_assignment -name START_TIME "0 ns"
-set_global_assignment -name GLITCH_INTERVAL "1 ns"
-
-# Design Assistant Assignments
-# ============================
-set_global_assignment -name DRC_REPORT_TOP_FANOUT OFF
-set_global_assignment -name DRC_REPORT_FANOUT_EXCEEDING OFF
-set_global_assignment -name ASSG_CAT OFF
-set_global_assignment -name ASSG_RULE_MISSING_FMAX OFF
-set_global_assignment -name ASSG_RULE_MISSING_TIMING OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_ASYN_RAM OFF
-set_global_assignment -name CLK_CAT OFF
-set_global_assignment -name CLK_RULE_COMB_CLOCK OFF
-set_global_assignment -name CLK_RULE_INV_CLOCK OFF
-set_global_assignment -name CLK_RULE_GATING_SCHEME OFF
-set_global_assignment -name CLK_RULE_INPINS_CLKNET OFF
-set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES OFF
-set_global_assignment -name CLK_RULE_MIX_EDGES OFF
-set_global_assignment -name RESET_CAT OFF
-set_global_assignment -name RESET_RULE_INPINS_RESETNET OFF
-set_global_assignment -name RESET_RULE_UNSYNCH_EXRESET OFF
-set_global_assignment -name RESET_RULE_IMSYNCH_EXRESET OFF
-set_global_assignment -name RESET_RULE_COMB_ASYNCH_RESET OFF
-set_global_assignment -name RESET_RULE_UNSYNCH_ASYNCH_DOMAIN OFF
-set_global_assignment -name RESET_RULE_IMSYNCH_ASYNCH_DOMAIN OFF
-set_global_assignment -name TIMING_CAT OFF
-set_global_assignment -name TIMING_RULE_SHIFT_REG OFF
-set_global_assignment -name TIMING_RULE_COIN_CLKEDGE OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE OFF
-set_global_assignment -name NONSYNCHSTRUCT_CAT OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_COMBLOOP OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_REG_LOOP OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_DELAY_CHAIN OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_RIPPLE_CLK OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_SRLATCH OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED OFF
-set_global_assignment -name SIGNALRACE_CAT OFF
-set_global_assignment -name ACLK_CAT OFF
-set_global_assignment -name ACLK_RULE_NO_SZER_ACLK_DOMAIN OFF
-set_global_assignment -name ACLK_RULE_SZER_BTW_ACLK_DOMAIN OFF
-set_global_assignment -name ACLK_RULE_IMSZER_ADOMAIN OFF
-set_global_assignment -name HCPY_CAT OFF
-set_global_assignment -name HCPY_VREF_PINS OFF
-
-# SignalTap II Assignments
-# ========================
-set_global_assignment -name HUB_ENTITY_NAME SLD_HUB
-set_global_assignment -name HUB_INSTANCE_NAME SLD_HUB_INST
-set_global_assignment -name ENABLE_SIGNALTAP OFF
-
-# LogicLock Region Assignments
-# ============================
-set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT OFF
-
-# -----------------
-# start CLOCK(SCLK)
-
-       # Timing Assignments
-       # ==================
-set_global_assignment -name DUTY_CYCLE 50 -section_id SCLK
-set_global_assignment -name FMAX_REQUIREMENT "1 MHz" -section_id SCLK
-set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id SCLK
-
-# end CLOCK(SCLK)
-# ---------------
-
-# -----------------------
-# start CLOCK(master_clk)
-
-       # Timing Assignments
-       # ==================
-set_global_assignment -name DUTY_CYCLE 50 -section_id master_clk
-set_global_assignment -name FMAX_REQUIREMENT "64 MHz" -section_id master_clk
-set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id master_clk
-
-# end CLOCK(master_clk)
-# ---------------------
-
-# -------------------
-# start CLOCK(usbclk)
-
-       # Timing Assignments
-       # ==================
-set_global_assignment -name DUTY_CYCLE 50 -section_id usbclk
-set_global_assignment -name FMAX_REQUIREMENT "48 MHz" -section_id usbclk
-set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id usbclk
-
-# end CLOCK(usbclk)
-# -----------------
-
-# ----------------------
-# start ENTITY(usrp_inband_usb)
-
-       # Timing Assignments
-       # ==================
-set_instance_assignment -name CLOCK_SETTINGS SCLK -to SCLK
-set_instance_assignment -name CLOCK_SETTINGS usbclk -to usbclk
-set_instance_assignment -name CLOCK_SETTINGS master_clk -to master_clk
-
-# end ENTITY(usrp_inband_usb)
-# --------------------
-
-
-set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN "100 ps"
-set_global_assignment -name VERILOG_FILE ../../megacells/fifo_4kx16_dc.v
-set_global_assignment -name VERILOG_FILE ../../megacells/fifo_1kx16.v
-set_global_assignment -name VERILOG_FILE ../../inband_lib/channel_demux.v
-set_global_assignment -name VERILOG_FILE ../../inband_lib/tx_packer.v
-set_global_assignment -name VERILOG_FILE ../../inband_lib/cmd_reader.v
-set_global_assignment -name VERILOG_FILE ../../inband_lib/packet_builder.v
-set_global_assignment -name VERILOG_FILE ../../inband_lib/rx_buffer_inband.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/atr_delay.v
-set_global_assignment -name VERILOG_FILE ../../inband_lib/tx_buffer_inband.v
-set_global_assignment -name VERILOG_FILE ../../inband_lib/chan_fifo_reader.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_dec_shifter.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/rssi.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/ram16.v
-set_global_assignment -name VERILOG_FILE ../../megacells/fifo_4k.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/acc.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/mult.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/ram16_2sum.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/coeff_rom.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/halfband_decim.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/mac.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/tx_chain.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_dcoffset.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/adc_interface.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/io_pins.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/setting_reg.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/bidir_reg.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_int_shifter.v
-set_global_assignment -name VERILOG_FILE ../../megacells/clk_doubler.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_chain.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/gen_sync.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/master_control.v
-set_global_assignment -name VERILOG_FILE ../../megacells/fifo_2k.v
-set_global_assignment -name VERILOG_FILE ../../megacells/bustri.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_buffer.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/tx_buffer.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/phase_acc.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_interp.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_decim.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/cordic_stage.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/cordic.v
-set_global_assignment -name VERILOG_FILE usrp_inband_usb.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/clk_divider.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/serial_io.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/strobe_gen.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/sign_extend.v
-set_global_assignment -name VERILOG_FILE ../../inband_lib/channel_ram.v
-set_global_assignment -name VERILOG_FILE ../../inband_lib/register_io.v
-set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
-set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
\ No newline at end of file

diff --git a/usrp/fpga/toplevel/usrp_multi/usrp_multi.qpf b/usrp/fpga/toplevel/usrp_multi/usrp_multi.qpf
deleted file mode 100644 (file)
index 1524de1..0000000
--- a/usrp/fpga/toplevel/usrp_multi/usrp_multi.qpf
+++ /dev/null
@@ -1,29 +0,0 @@
-# Copyright (C) 1991-2004 Altera Corporation
-# Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
-# support information,  device programming or simulation file,  and any other
-# associated  documentation or information  provided by  Altera  or a partner
-# under  Altera's   Megafunction   Partnership   Program  may  be  used  only
-# to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
-# other  use  of such  megafunction  design,  netlist,  support  information,
-# device programming or simulation file,  or any other  related documentation
-# or information  is prohibited  for  any  other purpose,  including, but not
-# limited to  modification,  reverse engineering,  de-compiling, or use  with
-# any other  silicon devices,  unless such use is  explicitly  licensed under
-# a separate agreement with  Altera  or a megafunction partner.  Title to the
-# intellectual property,  including patents,  copyrights,  trademarks,  trade
-# secrets,  or maskworks,  embodied in any such megafunction design, netlist,
-# support  information,  device programming or simulation file,  or any other
-# related documentation or information provided by  Altera  or a megafunction
-# partner, remains with Altera, the megafunction partner, or their respective
-# licensors. No other licenses, including any licenses needed under any third
-# party's intellectual property, are provided herein.
-
-
-
-QUARTUS_VERSION = "4.0"
-DATE = "17:10:11  December 20, 2004"
-
-
-# Active Revisions
-
-PROJECT_REVISION = "usrp_multi"

diff --git a/usrp/fpga/toplevel/usrp_multi/usrp_multi.qsf b/usrp/fpga/toplevel/usrp_multi/usrp_multi.qsf
deleted file mode 100644 (file)
index 9f0efbd..0000000
--- a/usrp/fpga/toplevel/usrp_multi/usrp_multi.qsf
+++ /dev/null
@@ -1,408 +0,0 @@
-# Copyright (C) 1991-2005 Altera Corporation\r
-# Your use of Altera Corporation's design tools, logic functions \r
-# and other software and tools, and its AMPP partner logic       \r
-# functions, and any output files any of the foregoing           \r
-# (including device programming or simulation files), and any    \r
-# associated documentation or information are expressly subject  \r
-# to the terms and conditions of the Altera Program License      \r
-# Subscription Agreement, Altera MegaCore Function License       \r
-# Agreement, or other applicable license agreement, including,   \r
-# without limitation, that your use is for the sole purpose of   \r
-# programming logic devices manufactured by Altera and sold by   \r
-# Altera or its authorized distributors.  Please refer to the    \r
-# applicable agreement for further details.\r
-\r
-\r
-# The default values for assignments are stored in the file\r
-#              usrp_multi_assignment_defaults.qdf\r
-# If this file doesn't exist, and for assignments not listed, see file\r
-#              assignment_defaults.qdf\r
-\r
-# Altera recommends that you do not modify this file. This\r
-# file is updated automatically by the Quartus II software\r
-# and any changes you make may be lost or overwritten.\r
-\r
-\r
-# Project-Wide Assignments\r
-# ========================\r
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 3.0\r
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:14:04  JULY 13, 2003"\r
-set_global_assignment -name LAST_QUARTUS_VERSION 6.1\r
-\r
-# Pin & Location Assignments\r
-# ==========================\r
-set_global_assignment -name RESERVE_PIN "AS INPUT TRI-STATED"\r
-set_location_assignment PIN_29 -to SCLK\r
-set_location_assignment PIN_117 -to SDI\r
-set_location_assignment PIN_28 -to usbclk\r
-set_location_assignment PIN_107 -to usbctl[0]\r
-set_location_assignment PIN_106 -to usbctl[1]\r
-set_location_assignment PIN_105 -to usbctl[2]\r
-set_location_assignment PIN_100 -to usbdata[0]\r
-set_location_assignment PIN_84 -to usbdata[10]\r
-set_location_assignment PIN_83 -to usbdata[11]\r
-set_location_assignment PIN_82 -to usbdata[12]\r
-set_location_assignment PIN_79 -to usbdata[13]\r
-set_location_assignment PIN_78 -to usbdata[14]\r
-set_location_assignment PIN_77 -to usbdata[15]\r
-set_location_assignment PIN_99 -to usbdata[1]\r
-set_location_assignment PIN_98 -to usbdata[2]\r
-set_location_assignment PIN_95 -to usbdata[3]\r
-set_location_assignment PIN_94 -to usbdata[4]\r
-set_location_assignment PIN_93 -to usbdata[5]\r
-set_location_assignment PIN_88 -to usbdata[6]\r
-set_location_assignment PIN_87 -to usbdata[7]\r
-set_location_assignment PIN_86 -to usbdata[8]\r
-set_location_assignment PIN_85 -to usbdata[9]\r
-set_location_assignment PIN_104 -to usbrdy[0]\r
-set_location_assignment PIN_101 -to usbrdy[1]\r
-set_location_assignment PIN_76 -to FX2_1\r
-set_location_assignment PIN_75 -to FX2_2\r
-set_location_assignment PIN_74 -to FX2_3\r
-set_location_assignment PIN_116 -to io_rx_a[0]\r
-set_location_assignment PIN_115 -to io_rx_a[1]\r
-set_location_assignment PIN_114 -to io_rx_a[2]\r
-set_location_assignment PIN_113 -to io_rx_a[3]\r
-set_location_assignment PIN_108 -to io_rx_a[4]\r
-set_location_assignment PIN_195 -to io_rx_a[5]\r
-set_location_assignment PIN_196 -to io_rx_a[6]\r
-set_location_assignment PIN_197 -to io_rx_a[7]\r
-set_location_assignment PIN_200 -to io_rx_a[8]\r
-set_location_assignment PIN_201 -to io_rx_a[9]\r
-set_location_assignment PIN_202 -to io_rx_a[10]\r
-set_location_assignment PIN_203 -to io_rx_a[11]\r
-set_location_assignment PIN_206 -to io_rx_a[12]\r
-set_location_assignment PIN_207 -to io_rx_a[13]\r
-set_location_assignment PIN_208 -to io_rx_a[14]\r
-set_location_assignment PIN_214 -to io_rx_b[0]\r
-set_location_assignment PIN_215 -to io_rx_b[1]\r
-set_location_assignment PIN_216 -to io_rx_b[2]\r
-set_location_assignment PIN_217 -to io_rx_b[3]\r
-set_location_assignment PIN_218 -to io_rx_b[4]\r
-set_location_assignment PIN_219 -to io_rx_b[5]\r
-set_location_assignment PIN_222 -to io_rx_b[6]\r
-set_location_assignment PIN_223 -to io_rx_b[7]\r
-set_location_assignment PIN_224 -to io_rx_b[8]\r
-set_location_assignment PIN_225 -to io_rx_b[9]\r
-set_location_assignment PIN_226 -to io_rx_b[10]\r
-set_location_assignment PIN_227 -to io_rx_b[11]\r
-set_location_assignment PIN_228 -to io_rx_b[12]\r
-set_location_assignment PIN_233 -to io_rx_b[13]\r
-set_location_assignment PIN_234 -to io_rx_b[14]\r
-set_location_assignment PIN_175 -to io_tx_a[0]\r
-set_location_assignment PIN_176 -to io_tx_a[1]\r
-set_location_assignment PIN_177 -to io_tx_a[2]\r
-set_location_assignment PIN_178 -to io_tx_a[3]\r
-set_location_assignment PIN_179 -to io_tx_a[4]\r
-set_location_assignment PIN_180 -to io_tx_a[5]\r
-set_location_assignment PIN_181 -to io_tx_a[6]\r
-set_location_assignment PIN_182 -to io_tx_a[7]\r
-set_location_assignment PIN_183 -to io_tx_a[8]\r
-set_location_assignment PIN_184 -to io_tx_a[9]\r
-set_location_assignment PIN_185 -to io_tx_a[10]\r
-set_location_assignment PIN_186 -to io_tx_a[11]\r
-set_location_assignment PIN_187 -to io_tx_a[12]\r
-set_location_assignment PIN_188 -to io_tx_a[13]\r
-set_location_assignment PIN_193 -to io_tx_a[14]\r
-set_location_assignment PIN_73 -to io_tx_b[0]\r
-set_location_assignment PIN_68 -to io_tx_b[1]\r
-set_location_assignment PIN_67 -to io_tx_b[2]\r
-set_location_assignment PIN_66 -to io_tx_b[3]\r
-set_location_assignment PIN_65 -to io_tx_b[4]\r
-set_location_assignment PIN_64 -to io_tx_b[5]\r
-set_location_assignment PIN_63 -to io_tx_b[6]\r
-set_location_assignment PIN_62 -to io_tx_b[7]\r
-set_location_assignment PIN_61 -to io_tx_b[8]\r
-set_location_assignment PIN_60 -to io_tx_b[9]\r
-set_location_assignment PIN_59 -to io_tx_b[10]\r
-set_location_assignment PIN_58 -to io_tx_b[11]\r
-set_location_assignment PIN_57 -to io_tx_b[12]\r
-set_location_assignment PIN_56 -to io_tx_b[13]\r
-set_location_assignment PIN_55 -to io_tx_b[14]\r
-set_location_assignment PIN_152 -to master_clk\r
-set_location_assignment PIN_144 -to rx_a_a[0]\r
-set_location_assignment PIN_143 -to rx_a_a[1]\r
-set_location_assignment PIN_141 -to rx_a_a[2]\r
-set_location_assignment PIN_140 -to rx_a_a[3]\r
-set_location_assignment PIN_139 -to rx_a_a[4]\r
-set_location_assignment PIN_138 -to rx_a_a[5]\r
-set_location_assignment PIN_137 -to rx_a_a[6]\r
-set_location_assignment PIN_136 -to rx_a_a[7]\r
-set_location_assignment PIN_135 -to rx_a_a[8]\r
-set_location_assignment PIN_134 -to rx_a_a[9]\r
-set_location_assignment PIN_133 -to rx_a_a[10]\r
-set_location_assignment PIN_132 -to rx_a_a[11]\r
-set_location_assignment PIN_23 -to rx_a_b[0]\r
-set_location_assignment PIN_21 -to rx_a_b[1]\r
-set_location_assignment PIN_20 -to rx_a_b[2]\r
-set_location_assignment PIN_19 -to rx_a_b[3]\r
-set_location_assignment PIN_18 -to rx_a_b[4]\r
-set_location_assignment PIN_17 -to rx_a_b[5]\r
-set_location_assignment PIN_16 -to rx_a_b[6]\r
-set_location_assignment PIN_15 -to rx_a_b[7]\r
-set_location_assignment PIN_14 -to rx_a_b[8]\r
-set_location_assignment PIN_13 -to rx_a_b[9]\r
-set_location_assignment PIN_12 -to rx_a_b[10]\r
-set_location_assignment PIN_11 -to rx_a_b[11]\r
-set_location_assignment PIN_131 -to rx_b_a[0]\r
-set_location_assignment PIN_128 -to rx_b_a[1]\r
-set_location_assignment PIN_127 -to rx_b_a[2]\r
-set_location_assignment PIN_126 -to rx_b_a[3]\r
-set_location_assignment PIN_125 -to rx_b_a[4]\r
-set_location_assignment PIN_124 -to rx_b_a[5]\r
-set_location_assignment PIN_123 -to rx_b_a[6]\r
-set_location_assignment PIN_122 -to rx_b_a[7]\r
-set_location_assignment PIN_121 -to rx_b_a[8]\r
-set_location_assignment PIN_120 -to rx_b_a[9]\r
-set_location_assignment PIN_119 -to rx_b_a[10]\r
-set_location_assignment PIN_118 -to rx_b_a[11]\r
-set_location_assignment PIN_8 -to rx_b_b[0]\r
-set_location_assignment PIN_7 -to rx_b_b[1]\r
-set_location_assignment PIN_6 -to rx_b_b[2]\r
-set_location_assignment PIN_5 -to rx_b_b[3]\r
-set_location_assignment PIN_4 -to rx_b_b[4]\r
-set_location_assignment PIN_3 -to rx_b_b[5]\r
-set_location_assignment PIN_2 -to rx_b_b[6]\r
-set_location_assignment PIN_240 -to rx_b_b[7]\r
-set_location_assignment PIN_239 -to rx_b_b[8]\r
-set_location_assignment PIN_238 -to rx_b_b[9]\r
-set_location_assignment PIN_237 -to rx_b_b[10]\r
-set_location_assignment PIN_236 -to rx_b_b[11]\r
-set_location_assignment PIN_156 -to SDO\r
-set_location_assignment PIN_153 -to SEN_FPGA\r
-set_location_assignment PIN_159 -to tx_a[0]\r
-set_location_assignment PIN_160 -to tx_a[1]\r
-set_location_assignment PIN_161 -to tx_a[2]\r
-set_location_assignment PIN_162 -to tx_a[3]\r
-set_location_assignment PIN_163 -to tx_a[4]\r
-set_location_assignment PIN_164 -to tx_a[5]\r
-set_location_assignment PIN_165 -to tx_a[6]\r
-set_location_assignment PIN_166 -to tx_a[7]\r
-set_location_assignment PIN_167 -to tx_a[8]\r
-set_location_assignment PIN_168 -to tx_a[9]\r
-set_location_assignment PIN_169 -to tx_a[10]\r
-set_location_assignment PIN_170 -to tx_a[11]\r
-set_location_assignment PIN_173 -to tx_a[12]\r
-set_location_assignment PIN_174 -to tx_a[13]\r
-set_location_assignment PIN_38 -to tx_b[0]\r
-set_location_assignment PIN_39 -to tx_b[1]\r
-set_location_assignment PIN_41 -to tx_b[2]\r
-set_location_assignment PIN_42 -to tx_b[3]\r
-set_location_assignment PIN_43 -to tx_b[4]\r
-set_location_assignment PIN_44 -to tx_b[5]\r
-set_location_assignment PIN_45 -to tx_b[6]\r
-set_location_assignment PIN_46 -to tx_b[7]\r
-set_location_assignment PIN_47 -to tx_b[8]\r
-set_location_assignment PIN_48 -to tx_b[9]\r
-set_location_assignment PIN_49 -to tx_b[10]\r
-set_location_assignment PIN_50 -to tx_b[11]\r
-set_location_assignment PIN_53 -to tx_b[12]\r
-set_location_assignment PIN_54 -to tx_b[13]\r
-set_location_assignment PIN_158 -to TXSYNC_A\r
-set_location_assignment PIN_37 -to TXSYNC_B\r
-set_location_assignment PIN_235 -to io_rx_b[15]\r
-set_location_assignment PIN_24 -to io_tx_b[15]\r
-set_location_assignment PIN_213 -to io_rx_a[15]\r
-set_location_assignment PIN_194 -to io_tx_a[15]\r
-set_location_assignment PIN_1 -to MYSTERY_SIGNAL\r
-\r
-# Timing Assignments\r
-# ==================\r
-set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF\r
-\r
-# Analysis & Synthesis Assignments\r
-# ================================\r
-set_global_assignment -name SAVE_DISK_SPACE OFF\r
-set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP"\r
-set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240\r
-set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"\r
-set_global_assignment -name FAMILY Cyclone\r
-set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE BALANCED\r
-set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED\r
-set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED\r
-set_global_assignment -name TOP_LEVEL_ENTITY usrp_multi\r
-set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF\r
-set_global_assignment -name USER_LIBRARIES "H:\\usrp-for2.7\\fpga\\megacells"\r
-set_global_assignment -name AUTO_ENABLE_SMART_COMPILE ON\r
-\r
-# Fitter Assignments\r
-# ==================\r
-set_global_assignment -name DEVICE EP1C12Q240C8\r
-set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "PASSIVE SERIAL"\r
-set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"\r
-set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF\r
-set_global_assignment -name OPTIMIZE_TIMING "NORMAL COMPILATION"\r
-set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF\r
-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF\r
-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF\r
-set_global_assignment -name IO_PLACEMENT_OPTIMIZATION OFF\r
-set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL\r
-set_global_assignment -name INC_PLC_MODE OFF\r
-set_global_assignment -name ROUTING_BACK_ANNOTATION_MODE OFF\r
-set_instance_assignment -name IO_STANDARD LVTTL -to usbdata[12]\r
-set_global_assignment -name STRATIX_DEVICE_IO_STANDARD LVTTL\r
-set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1\r
-\r
-# Timing Analysis Assignments\r
-# ===========================\r
-set_global_assignment -name MAX_SCC_SIZE 50\r
-\r
-# EDA Netlist Writer Assignments\r
-# ==============================\r
-set_global_assignment -name EDA_SIMULATION_TOOL "<None>"\r
-set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<NONE>"\r
-set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<NONE>"\r
-set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<NONE>"\r
-set_global_assignment -name EDA_RESYNTHESIS_TOOL "<NONE>"\r
-\r
-# Assembler Assignments\r
-# =====================\r
-set_global_assignment -name USE_CONFIGURATION_DEVICE OFF\r
-set_global_assignment -name GENERATE_RBF_FILE ON\r
-set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"\r
-set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF\r
-\r
-# Simulator Assignments\r
-# =====================\r
-set_global_assignment -name START_TIME "0 ns"\r
-set_global_assignment -name GLITCH_INTERVAL "1 ns"\r
-\r
-# Design Assistant Assignments\r
-# ============================\r
-set_global_assignment -name DRC_REPORT_TOP_FANOUT OFF\r
-set_global_assignment -name DRC_REPORT_FANOUT_EXCEEDING OFF\r
-set_global_assignment -name ASSG_CAT OFF\r
-set_global_assignment -name ASSG_RULE_MISSING_FMAX OFF\r
-set_global_assignment -name ASSG_RULE_MISSING_TIMING OFF\r
-set_global_assignment -name NONSYNCHSTRUCT_RULE_ASYN_RAM OFF\r
-set_global_assignment -name CLK_CAT OFF\r
-set_global_assignment -name CLK_RULE_COMB_CLOCK OFF\r
-set_global_assignment -name CLK_RULE_INV_CLOCK OFF\r
-set_global_assignment -name CLK_RULE_GATING_SCHEME OFF\r
-set_global_assignment -name CLK_RULE_INPINS_CLKNET OFF\r
-set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES OFF\r
-set_global_assignment -name CLK_RULE_MIX_EDGES OFF\r
-set_global_assignment -name RESET_CAT OFF\r
-set_global_assignment -name RESET_RULE_INPINS_RESETNET OFF\r
-set_global_assignment -name RESET_RULE_UNSYNCH_EXRESET OFF\r
-set_global_assignment -name RESET_RULE_IMSYNCH_EXRESET OFF\r
-set_global_assignment -name RESET_RULE_COMB_ASYNCH_RESET OFF\r
-set_global_assignment -name RESET_RULE_UNSYNCH_ASYNCH_DOMAIN OFF\r
-set_global_assignment -name RESET_RULE_IMSYNCH_ASYNCH_DOMAIN OFF\r
-set_global_assignment -name TIMING_CAT OFF\r
-set_global_assignment -name TIMING_RULE_SHIFT_REG OFF\r
-set_global_assignment -name TIMING_RULE_COIN_CLKEDGE OFF\r
-set_global_assignment -name NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE OFF\r
-set_global_assignment -name NONSYNCHSTRUCT_CAT OFF\r
-set_global_assignment -name NONSYNCHSTRUCT_RULE_COMBLOOP OFF\r
-set_global_assignment -name NONSYNCHSTRUCT_RULE_REG_LOOP OFF\r
-set_global_assignment -name NONSYNCHSTRUCT_RULE_DELAY_CHAIN OFF\r
-set_global_assignment -name NONSYNCHSTRUCT_RULE_RIPPLE_CLK OFF\r
-set_global_assignment -name NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN OFF\r
-set_global_assignment -name NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR OFF\r
-set_global_assignment -name NONSYNCHSTRUCT_RULE_SRLATCH OFF\r
-set_global_assignment -name NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED OFF\r
-set_global_assignment -name SIGNALRACE_CAT OFF\r
-set_global_assignment -name ACLK_CAT OFF\r
-set_global_assignment -name ACLK_RULE_NO_SZER_ACLK_DOMAIN OFF\r
-set_global_assignment -name ACLK_RULE_SZER_BTW_ACLK_DOMAIN OFF\r
-set_global_assignment -name ACLK_RULE_IMSZER_ADOMAIN OFF\r
-set_global_assignment -name HCPY_CAT OFF\r
-set_global_assignment -name HCPY_VREF_PINS OFF\r
-\r
-# SignalTap II Assignments\r
-# ========================\r
-set_global_assignment -name HUB_ENTITY_NAME SLD_HUB\r
-set_global_assignment -name HUB_INSTANCE_NAME SLD_HUB_INST\r
-set_global_assignment -name ENABLE_SIGNALTAP OFF\r
-\r
-# LogicLock Region Assignments\r
-# ============================\r
-set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT OFF\r
-\r
-# -----------------\r
-# start CLOCK(SCLK)\r
-\r
-       # Timing Assignments\r
-       # ==================\r
-set_global_assignment -name DUTY_CYCLE 50 -section_id SCLK\r
-set_global_assignment -name FMAX_REQUIREMENT "1 MHz" -section_id SCLK\r
-set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id SCLK\r
-\r
-# end CLOCK(SCLK)\r
-# ---------------\r
-\r
-# -----------------------\r
-# start CLOCK(master_clk)\r
-\r
-       # Timing Assignments\r
-       # ==================\r
-set_global_assignment -name DUTY_CYCLE 50 -section_id master_clk\r
-set_global_assignment -name FMAX_REQUIREMENT "64 MHz" -section_id master_clk\r
-set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id master_clk\r
-\r
-# end CLOCK(master_clk)\r
-# ---------------------\r
-\r
-# -------------------\r
-# start CLOCK(usbclk)\r
-\r
-       # Timing Assignments\r
-       # ==================\r
-set_global_assignment -name DUTY_CYCLE 50 -section_id usbclk\r
-set_global_assignment -name FMAX_REQUIREMENT "48 MHz" -section_id usbclk\r
-set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id usbclk\r
-\r
-# end CLOCK(usbclk)\r
-# -----------------\r
-\r
-# ----------------------\r
-# start ENTITY(usrp_multi)\r
-\r
-       # Timing Assignments\r
-       # ==================\r
-set_instance_assignment -name CLOCK_SETTINGS SCLK -to SCLK\r
-set_instance_assignment -name CLOCK_SETTINGS usbclk -to usbclk\r
-set_instance_assignment -name CLOCK_SETTINGS master_clk -to master_clk\r
-\r
-# end ENTITY(usrp_multi)\r
-# --------------------\r
-\r
-\r
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/rssi.v\r
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/setting_reg_masked.v\r
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/master_control_multi.v\r
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/ram16.v\r
-set_global_assignment -name VERILOG_FILE ../../megacells/fifo_4k.v\r
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/acc.v\r
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/mult.v\r
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/ram16_2sum.v\r
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/coeff_rom.v\r
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/halfband_decim.v\r
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/mac.v\r
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/coeff_ram.v\r
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/tx_chain.v\r
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_dcoffset.v\r
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/adc_interface.v\r
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/io_pins.v\r
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/setting_reg.v\r
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/bidir_reg.v\r
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_int_shifter.v\r
-set_global_assignment -name VERILOG_FILE ../../megacells/clk_doubler.v\r
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_chain.v\r
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/gen_sync.v\r
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/master_control.v\r
-set_global_assignment -name VERILOG_FILE ../../megacells/fifo_2k.v\r
-set_global_assignment -name VERILOG_FILE ../../megacells/bustri.v\r
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_buffer.v\r
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/tx_buffer.v\r
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/phase_acc.v\r
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_interp.v\r
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_decim.v\r
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/cordic_stage.v\r
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/cordic.v\r
-set_global_assignment -name VERILOG_FILE usrp_multi.v\r
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/clk_divider.v\r
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/serial_io.v\r
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/strobe_gen.v\r
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/sign_extend.v
\ No newline at end of file

diff --git a/usrp/fpga/toplevel/usrp_std/usrp_std.qpf b/usrp/fpga/toplevel/usrp_std/usrp_std.qpf
deleted file mode 100644 (file)
index e8b2750..0000000
--- a/usrp/fpga/toplevel/usrp_std/usrp_std.qpf
+++ /dev/null
@@ -1,29 +0,0 @@
-# Copyright (C) 1991-2004 Altera Corporation
-# Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
-# support information,  device programming or simulation file,  and any other
-# associated  documentation or information  provided by  Altera  or a partner
-# under  Altera's   Megafunction   Partnership   Program  may  be  used  only
-# to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
-# other  use  of such  megafunction  design,  netlist,  support  information,
-# device programming or simulation file,  or any other  related documentation
-# or information  is prohibited  for  any  other purpose,  including, but not
-# limited to  modification,  reverse engineering,  de-compiling, or use  with
-# any other  silicon devices,  unless such use is  explicitly  licensed under
-# a separate agreement with  Altera  or a megafunction partner.  Title to the
-# intellectual property,  including patents,  copyrights,  trademarks,  trade
-# secrets,  or maskworks,  embodied in any such megafunction design, netlist,
-# support  information,  device programming or simulation file,  or any other
-# related documentation or information provided by  Altera  or a megafunction
-# partner, remains with Altera, the megafunction partner, or their respective
-# licensors. No other licenses, including any licenses needed under any third
-# party's intellectual property, are provided herein.
-
-
-
-QUARTUS_VERSION = "4.0"
-DATE = "17:10:11  December 20, 2004"
-
-
-# Active Revisions
-
-PROJECT_REVISION = "usrp_std"

diff --git a/usrp/fpga/toplevel/usrp_std/usrp_std.qsf b/usrp/fpga/toplevel/usrp_std/usrp_std.qsf
deleted file mode 100644 (file)
index e0bac48..0000000
--- a/usrp/fpga/toplevel/usrp_std/usrp_std.qsf
+++ /dev/null
@@ -1,409 +0,0 @@
-# Copyright (C) 1991-2005 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic       
-# functions, and any output files any of the foregoing           
-# (including device programming or simulation files), and any    
-# associated documentation or information are expressly subject  
-# to the terms and conditions of the Altera Program License      
-# Subscription Agreement, Altera MegaCore Function License       
-# Agreement, or other applicable license agreement, including,   
-# without limitation, that your use is for the sole purpose of   
-# programming logic devices manufactured by Altera and sold by   
-# Altera or its authorized distributors.  Please refer to the    
-# applicable agreement for further details.
-
-
-# The default values for assignments are stored in the file
-#              usrp_std_assignment_defaults.qdf
-# If this file doesn't exist, and for assignments not listed, see file
-#              assignment_defaults.qdf
-
-# Altera recommends that you do not modify this file. This
-# file is updated automatically by the Quartus II software
-# and any changes you make may be lost or overwritten.
-
-
-# Project-Wide Assignments
-# ========================
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 3.0
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:14:04  JULY 13, 2003"
-set_global_assignment -name LAST_QUARTUS_VERSION "7.1 SP1"
-
-# Pin & Location Assignments
-# ==========================
-set_global_assignment -name RESERVE_PIN "AS INPUT TRI-STATED"
-set_location_assignment PIN_29 -to SCLK
-set_location_assignment PIN_117 -to SDI
-set_location_assignment PIN_28 -to usbclk
-set_location_assignment PIN_107 -to usbctl[0]
-set_location_assignment PIN_106 -to usbctl[1]
-set_location_assignment PIN_105 -to usbctl[2]
-set_location_assignment PIN_100 -to usbdata[0]
-set_location_assignment PIN_84 -to usbdata[10]
-set_location_assignment PIN_83 -to usbdata[11]
-set_location_assignment PIN_82 -to usbdata[12]
-set_location_assignment PIN_79 -to usbdata[13]
-set_location_assignment PIN_78 -to usbdata[14]
-set_location_assignment PIN_77 -to usbdata[15]
-set_location_assignment PIN_99 -to usbdata[1]
-set_location_assignment PIN_98 -to usbdata[2]
-set_location_assignment PIN_95 -to usbdata[3]
-set_location_assignment PIN_94 -to usbdata[4]
-set_location_assignment PIN_93 -to usbdata[5]
-set_location_assignment PIN_88 -to usbdata[6]
-set_location_assignment PIN_87 -to usbdata[7]
-set_location_assignment PIN_86 -to usbdata[8]
-set_location_assignment PIN_85 -to usbdata[9]
-set_location_assignment PIN_104 -to usbrdy[0]
-set_location_assignment PIN_101 -to usbrdy[1]
-set_location_assignment PIN_76 -to FX2_1
-set_location_assignment PIN_75 -to FX2_2
-set_location_assignment PIN_74 -to FX2_3
-set_location_assignment PIN_116 -to io_rx_a[0]
-set_location_assignment PIN_115 -to io_rx_a[1]
-set_location_assignment PIN_114 -to io_rx_a[2]
-set_location_assignment PIN_113 -to io_rx_a[3]
-set_location_assignment PIN_108 -to io_rx_a[4]
-set_location_assignment PIN_195 -to io_rx_a[5]
-set_location_assignment PIN_196 -to io_rx_a[6]
-set_location_assignment PIN_197 -to io_rx_a[7]
-set_location_assignment PIN_200 -to io_rx_a[8]
-set_location_assignment PIN_201 -to io_rx_a[9]
-set_location_assignment PIN_202 -to io_rx_a[10]
-set_location_assignment PIN_203 -to io_rx_a[11]
-set_location_assignment PIN_206 -to io_rx_a[12]
-set_location_assignment PIN_207 -to io_rx_a[13]
-set_location_assignment PIN_208 -to io_rx_a[14]
-set_location_assignment PIN_214 -to io_rx_b[0]
-set_location_assignment PIN_215 -to io_rx_b[1]
-set_location_assignment PIN_216 -to io_rx_b[2]
-set_location_assignment PIN_217 -to io_rx_b[3]
-set_location_assignment PIN_218 -to io_rx_b[4]
-set_location_assignment PIN_219 -to io_rx_b[5]
-set_location_assignment PIN_222 -to io_rx_b[6]
-set_location_assignment PIN_223 -to io_rx_b[7]
-set_location_assignment PIN_224 -to io_rx_b[8]
-set_location_assignment PIN_225 -to io_rx_b[9]
-set_location_assignment PIN_226 -to io_rx_b[10]
-set_location_assignment PIN_227 -to io_rx_b[11]
-set_location_assignment PIN_228 -to io_rx_b[12]
-set_location_assignment PIN_233 -to io_rx_b[13]
-set_location_assignment PIN_234 -to io_rx_b[14]
-set_location_assignment PIN_175 -to io_tx_a[0]
-set_location_assignment PIN_176 -to io_tx_a[1]
-set_location_assignment PIN_177 -to io_tx_a[2]
-set_location_assignment PIN_178 -to io_tx_a[3]
-set_location_assignment PIN_179 -to io_tx_a[4]
-set_location_assignment PIN_180 -to io_tx_a[5]
-set_location_assignment PIN_181 -to io_tx_a[6]
-set_location_assignment PIN_182 -to io_tx_a[7]
-set_location_assignment PIN_183 -to io_tx_a[8]
-set_location_assignment PIN_184 -to io_tx_a[9]
-set_location_assignment PIN_185 -to io_tx_a[10]
-set_location_assignment PIN_186 -to io_tx_a[11]
-set_location_assignment PIN_187 -to io_tx_a[12]
-set_location_assignment PIN_188 -to io_tx_a[13]
-set_location_assignment PIN_193 -to io_tx_a[14]
-set_location_assignment PIN_73 -to io_tx_b[0]
-set_location_assignment PIN_68 -to io_tx_b[1]
-set_location_assignment PIN_67 -to io_tx_b[2]
-set_location_assignment PIN_66 -to io_tx_b[3]
-set_location_assignment PIN_65 -to io_tx_b[4]
-set_location_assignment PIN_64 -to io_tx_b[5]
-set_location_assignment PIN_63 -to io_tx_b[6]
-set_location_assignment PIN_62 -to io_tx_b[7]
-set_location_assignment PIN_61 -to io_tx_b[8]
-set_location_assignment PIN_60 -to io_tx_b[9]
-set_location_assignment PIN_59 -to io_tx_b[10]
-set_location_assignment PIN_58 -to io_tx_b[11]
-set_location_assignment PIN_57 -to io_tx_b[12]
-set_location_assignment PIN_56 -to io_tx_b[13]
-set_location_assignment PIN_55 -to io_tx_b[14]
-set_location_assignment PIN_152 -to master_clk
-set_location_assignment PIN_144 -to rx_a_a[0]
-set_location_assignment PIN_143 -to rx_a_a[1]
-set_location_assignment PIN_141 -to rx_a_a[2]
-set_location_assignment PIN_140 -to rx_a_a[3]
-set_location_assignment PIN_139 -to rx_a_a[4]
-set_location_assignment PIN_138 -to rx_a_a[5]
-set_location_assignment PIN_137 -to rx_a_a[6]
-set_location_assignment PIN_136 -to rx_a_a[7]
-set_location_assignment PIN_135 -to rx_a_a[8]
-set_location_assignment PIN_134 -to rx_a_a[9]
-set_location_assignment PIN_133 -to rx_a_a[10]
-set_location_assignment PIN_132 -to rx_a_a[11]
-set_location_assignment PIN_23 -to rx_a_b[0]
-set_location_assignment PIN_21 -to rx_a_b[1]
-set_location_assignment PIN_20 -to rx_a_b[2]
-set_location_assignment PIN_19 -to rx_a_b[3]
-set_location_assignment PIN_18 -to rx_a_b[4]
-set_location_assignment PIN_17 -to rx_a_b[5]
-set_location_assignment PIN_16 -to rx_a_b[6]
-set_location_assignment PIN_15 -to rx_a_b[7]
-set_location_assignment PIN_14 -to rx_a_b[8]
-set_location_assignment PIN_13 -to rx_a_b[9]
-set_location_assignment PIN_12 -to rx_a_b[10]
-set_location_assignment PIN_11 -to rx_a_b[11]
-set_location_assignment PIN_131 -to rx_b_a[0]
-set_location_assignment PIN_128 -to rx_b_a[1]
-set_location_assignment PIN_127 -to rx_b_a[2]
-set_location_assignment PIN_126 -to rx_b_a[3]
-set_location_assignment PIN_125 -to rx_b_a[4]
-set_location_assignment PIN_124 -to rx_b_a[5]
-set_location_assignment PIN_123 -to rx_b_a[6]
-set_location_assignment PIN_122 -to rx_b_a[7]
-set_location_assignment PIN_121 -to rx_b_a[8]
-set_location_assignment PIN_120 -to rx_b_a[9]
-set_location_assignment PIN_119 -to rx_b_a[10]
-set_location_assignment PIN_118 -to rx_b_a[11]
-set_location_assignment PIN_8 -to rx_b_b[0]
-set_location_assignment PIN_7 -to rx_b_b[1]
-set_location_assignment PIN_6 -to rx_b_b[2]
-set_location_assignment PIN_5 -to rx_b_b[3]
-set_location_assignment PIN_4 -to rx_b_b[4]
-set_location_assignment PIN_3 -to rx_b_b[5]
-set_location_assignment PIN_2 -to rx_b_b[6]
-set_location_assignment PIN_240 -to rx_b_b[7]
-set_location_assignment PIN_239 -to rx_b_b[8]
-set_location_assignment PIN_238 -to rx_b_b[9]
-set_location_assignment PIN_237 -to rx_b_b[10]
-set_location_assignment PIN_236 -to rx_b_b[11]
-set_location_assignment PIN_156 -to SDO
-set_location_assignment PIN_153 -to SEN_FPGA
-set_location_assignment PIN_159 -to tx_a[0]
-set_location_assignment PIN_160 -to tx_a[1]
-set_location_assignment PIN_161 -to tx_a[2]
-set_location_assignment PIN_162 -to tx_a[3]
-set_location_assignment PIN_163 -to tx_a[4]
-set_location_assignment PIN_164 -to tx_a[5]
-set_location_assignment PIN_165 -to tx_a[6]
-set_location_assignment PIN_166 -to tx_a[7]
-set_location_assignment PIN_167 -to tx_a[8]
-set_location_assignment PIN_168 -to tx_a[9]
-set_location_assignment PIN_169 -to tx_a[10]
-set_location_assignment PIN_170 -to tx_a[11]
-set_location_assignment PIN_173 -to tx_a[12]
-set_location_assignment PIN_174 -to tx_a[13]
-set_location_assignment PIN_38 -to tx_b[0]
-set_location_assignment PIN_39 -to tx_b[1]
-set_location_assignment PIN_41 -to tx_b[2]
-set_location_assignment PIN_42 -to tx_b[3]
-set_location_assignment PIN_43 -to tx_b[4]
-set_location_assignment PIN_44 -to tx_b[5]
-set_location_assignment PIN_45 -to tx_b[6]
-set_location_assignment PIN_46 -to tx_b[7]
-set_location_assignment PIN_47 -to tx_b[8]
-set_location_assignment PIN_48 -to tx_b[9]
-set_location_assignment PIN_49 -to tx_b[10]
-set_location_assignment PIN_50 -to tx_b[11]
-set_location_assignment PIN_53 -to tx_b[12]
-set_location_assignment PIN_54 -to tx_b[13]
-set_location_assignment PIN_158 -to TXSYNC_A
-set_location_assignment PIN_37 -to TXSYNC_B
-set_location_assignment PIN_235 -to io_rx_b[15]
-set_location_assignment PIN_24 -to io_tx_b[15]
-set_location_assignment PIN_213 -to io_rx_a[15]
-set_location_assignment PIN_194 -to io_tx_a[15]
-set_location_assignment PIN_1 -to MYSTERY_SIGNAL
-
-# Timing Assignments
-# ==================
-set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF
-
-# Analysis & Synthesis Assignments
-# ================================
-set_global_assignment -name SAVE_DISK_SPACE OFF
-set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP"
-set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240
-set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
-set_global_assignment -name FAMILY Cyclone
-set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE BALANCED
-set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED
-set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED
-set_global_assignment -name TOP_LEVEL_ENTITY usrp_std
-set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
-set_global_assignment -name USER_LIBRARIES "e:\\usrp\\fpga\\megacells"
-set_global_assignment -name AUTO_ENABLE_SMART_COMPILE ON
-
-# Fitter Assignments
-# ==================
-set_global_assignment -name DEVICE EP1C12Q240C8
-set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "PASSIVE SERIAL"
-set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
-set_global_assignment -name OPTIMIZE_TIMING "NORMAL COMPILATION"
-set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF
-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF
-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
-set_global_assignment -name IO_PLACEMENT_OPTIMIZATION OFF
-set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL
-set_global_assignment -name INC_PLC_MODE OFF
-set_global_assignment -name ROUTING_BACK_ANNOTATION_MODE OFF
-set_instance_assignment -name IO_STANDARD LVTTL -to usbdata[12]
-set_global_assignment -name STRATIX_DEVICE_IO_STANDARD LVTTL
-set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
-
-# Timing Analysis Assignments
-# ===========================
-set_global_assignment -name MAX_SCC_SIZE 50
-
-# EDA Netlist Writer Assignments
-# ==============================
-set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
-set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<NONE>"
-set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<NONE>"
-set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<NONE>"
-set_global_assignment -name EDA_RESYNTHESIS_TOOL "<NONE>"
-
-# Assembler Assignments
-# =====================
-set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
-set_global_assignment -name GENERATE_RBF_FILE ON
-set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
-set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF
-
-# Simulator Assignments
-# =====================
-set_global_assignment -name START_TIME "0 ns"
-set_global_assignment -name GLITCH_INTERVAL "1 ns"
-
-# Design Assistant Assignments
-# ============================
-set_global_assignment -name DRC_REPORT_TOP_FANOUT OFF
-set_global_assignment -name DRC_REPORT_FANOUT_EXCEEDING OFF
-set_global_assignment -name ASSG_CAT OFF
-set_global_assignment -name ASSG_RULE_MISSING_FMAX OFF
-set_global_assignment -name ASSG_RULE_MISSING_TIMING OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_ASYN_RAM OFF
-set_global_assignment -name CLK_CAT OFF
-set_global_assignment -name CLK_RULE_COMB_CLOCK OFF
-set_global_assignment -name CLK_RULE_INV_CLOCK OFF
-set_global_assignment -name CLK_RULE_GATING_SCHEME OFF
-set_global_assignment -name CLK_RULE_INPINS_CLKNET OFF
-set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES OFF
-set_global_assignment -name CLK_RULE_MIX_EDGES OFF
-set_global_assignment -name RESET_CAT OFF
-set_global_assignment -name RESET_RULE_INPINS_RESETNET OFF
-set_global_assignment -name RESET_RULE_UNSYNCH_EXRESET OFF
-set_global_assignment -name RESET_RULE_IMSYNCH_EXRESET OFF
-set_global_assignment -name RESET_RULE_COMB_ASYNCH_RESET OFF
-set_global_assignment -name RESET_RULE_UNSYNCH_ASYNCH_DOMAIN OFF
-set_global_assignment -name RESET_RULE_IMSYNCH_ASYNCH_DOMAIN OFF
-set_global_assignment -name TIMING_CAT OFF
-set_global_assignment -name TIMING_RULE_SHIFT_REG OFF
-set_global_assignment -name TIMING_RULE_COIN_CLKEDGE OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE OFF
-set_global_assignment -name NONSYNCHSTRUCT_CAT OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_COMBLOOP OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_REG_LOOP OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_DELAY_CHAIN OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_RIPPLE_CLK OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_SRLATCH OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED OFF
-set_global_assignment -name SIGNALRACE_CAT OFF
-set_global_assignment -name ACLK_CAT OFF
-set_global_assignment -name ACLK_RULE_NO_SZER_ACLK_DOMAIN OFF
-set_global_assignment -name ACLK_RULE_SZER_BTW_ACLK_DOMAIN OFF
-set_global_assignment -name ACLK_RULE_IMSZER_ADOMAIN OFF
-set_global_assignment -name HCPY_CAT OFF
-set_global_assignment -name HCPY_VREF_PINS OFF
-
-# SignalTap II Assignments
-# ========================
-set_global_assignment -name HUB_ENTITY_NAME SLD_HUB
-set_global_assignment -name HUB_INSTANCE_NAME SLD_HUB_INST
-set_global_assignment -name ENABLE_SIGNALTAP OFF
-
-# LogicLock Region Assignments
-# ============================
-set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT OFF
-
-# -----------------
-# start CLOCK(SCLK)
-
-       # Timing Assignments
-       # ==================
-set_global_assignment -name DUTY_CYCLE 50 -section_id SCLK
-set_global_assignment -name FMAX_REQUIREMENT "1 MHz" -section_id SCLK
-set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id SCLK
-
-# end CLOCK(SCLK)
-# ---------------
-
-# -----------------------
-# start CLOCK(master_clk)
-
-       # Timing Assignments
-       # ==================
-set_global_assignment -name DUTY_CYCLE 50 -section_id master_clk
-set_global_assignment -name FMAX_REQUIREMENT "64 MHz" -section_id master_clk
-set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id master_clk
-
-# end CLOCK(master_clk)
-# ---------------------
-
-# -------------------
-# start CLOCK(usbclk)
-
-       # Timing Assignments
-       # ==================
-set_global_assignment -name DUTY_CYCLE 50 -section_id usbclk
-set_global_assignment -name FMAX_REQUIREMENT "48 MHz" -section_id usbclk
-set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id usbclk
-
-# end CLOCK(usbclk)
-# -----------------
-
-# ----------------------
-# start ENTITY(usrp_std)
-
-       # Timing Assignments
-       # ==================
-set_instance_assignment -name CLOCK_SETTINGS SCLK -to SCLK
-set_instance_assignment -name CLOCK_SETTINGS usbclk -to usbclk
-set_instance_assignment -name CLOCK_SETTINGS master_clk -to master_clk
-
-# end ENTITY(usrp_std)
-# --------------------
-
-set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name VERILOG_FILE ../../megacells/fifo_4k_18.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/atr_delay.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_dec_shifter.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/rssi.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/ram16.v
-set_global_assignment -name VERILOG_FILE ../../megacells/fifo_4k.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/acc.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/mult.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/ram16_2sum.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/coeff_rom.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/halfband_decim.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/mac.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/tx_chain.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_dcoffset.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/adc_interface.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/io_pins.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/setting_reg.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/bidir_reg.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_int_shifter.v
-set_global_assignment -name VERILOG_FILE ../../megacells/clk_doubler.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_chain.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/gen_sync.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/master_control.v
-set_global_assignment -name VERILOG_FILE ../../megacells/fifo_2k.v
-set_global_assignment -name VERILOG_FILE ../../megacells/bustri.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_buffer.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/tx_buffer.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/phase_acc.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_interp.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_decim.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/cordic_stage.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/cordic.v
-set_global_assignment -name VERILOG_FILE usrp_std.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/clk_divider.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/serial_io.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/strobe_gen.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/sign_extend.v
\ No newline at end of file