1 # Copyright (C) 1991-2007 Altera Corporation
2 # Your use of Altera Corporation's design tools, logic functions
3 # and other software and tools, and its AMPP partner logic
4 # functions, and any output files from any of the foregoing
5 # (including device programming or simulation files), and any
6 # associated documentation or information are expressly subject
7 # to the terms and conditions of the Altera Program License
8 # Subscription Agreement, Altera MegaCore Function License
9 # Agreement, or other applicable license agreement, including,
10 # without limitation, that your use is for the sole purpose of
11 # programming logic devices manufactured by Altera and sold by
12 # Altera or its authorized distributors. Please refer to the
13 # applicable agreement for further details.
16 # The default values for assignments are stored in the file
17 # usrp_radar_mono_assignment_defaults.qdf
18 # If this file doesn't exist, and for assignments not listed, see file
19 # assignment_defaults.qdf
21 # Altera recommends that you do not modify this file. This
22 # file is updated automatically by the Quartus II software
23 # and any changes you make may be lost or overwritten.
27 # Project-Wide Assignments
28 # ========================
29 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 3.0
30 set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:14:04 JULY 13, 2003"
31 set_global_assignment -name LAST_QUARTUS_VERSION "7.1 SP1"
32 set_global_assignment -name MESSAGE_SUPPRESSION_RULE_FILE usrp_radar_mono.srf
34 # Pin & Location Assignments
35 # ==========================
36 set_global_assignment -name RESERVE_PIN "AS INPUT TRI-STATED"
37 set_location_assignment PIN_29 -to SCLK
38 set_location_assignment PIN_117 -to SDI
39 set_location_assignment PIN_28 -to usbclk
40 set_location_assignment PIN_107 -to usbctl[0]
41 set_location_assignment PIN_106 -to usbctl[1]
42 set_location_assignment PIN_105 -to usbctl[2]
43 set_location_assignment PIN_100 -to usbdata[0]
44 set_location_assignment PIN_84 -to usbdata[10]
45 set_location_assignment PIN_83 -to usbdata[11]
46 set_location_assignment PIN_82 -to usbdata[12]
47 set_location_assignment PIN_79 -to usbdata[13]
48 set_location_assignment PIN_78 -to usbdata[14]
49 set_location_assignment PIN_77 -to usbdata[15]
50 set_location_assignment PIN_99 -to usbdata[1]
51 set_location_assignment PIN_98 -to usbdata[2]
52 set_location_assignment PIN_95 -to usbdata[3]
53 set_location_assignment PIN_94 -to usbdata[4]
54 set_location_assignment PIN_93 -to usbdata[5]
55 set_location_assignment PIN_88 -to usbdata[6]
56 set_location_assignment PIN_87 -to usbdata[7]
57 set_location_assignment PIN_86 -to usbdata[8]
58 set_location_assignment PIN_85 -to usbdata[9]
59 set_location_assignment PIN_104 -to usbrdy[0]
60 set_location_assignment PIN_101 -to usbrdy[1]
61 set_location_assignment PIN_76 -to FX2_1
62 set_location_assignment PIN_75 -to FX2_2
63 set_location_assignment PIN_74 -to FX2_3
64 set_location_assignment PIN_116 -to io_rx_a[0]
65 set_location_assignment PIN_115 -to io_rx_a[1]
66 set_location_assignment PIN_114 -to io_rx_a[2]
67 set_location_assignment PIN_113 -to io_rx_a[3]
68 set_location_assignment PIN_108 -to io_rx_a[4]
69 set_location_assignment PIN_195 -to io_rx_a[5]
70 set_location_assignment PIN_196 -to io_rx_a[6]
71 set_location_assignment PIN_197 -to io_rx_a[7]
72 set_location_assignment PIN_200 -to io_rx_a[8]
73 set_location_assignment PIN_201 -to io_rx_a[9]
74 set_location_assignment PIN_202 -to io_rx_a[10]
75 set_location_assignment PIN_203 -to io_rx_a[11]
76 set_location_assignment PIN_206 -to io_rx_a[12]
77 set_location_assignment PIN_207 -to io_rx_a[13]
78 set_location_assignment PIN_208 -to io_rx_a[14]
79 set_location_assignment PIN_214 -to io_rx_b[0]
80 set_location_assignment PIN_215 -to io_rx_b[1]
81 set_location_assignment PIN_216 -to io_rx_b[2]
82 set_location_assignment PIN_217 -to io_rx_b[3]
83 set_location_assignment PIN_218 -to io_rx_b[4]
84 set_location_assignment PIN_219 -to io_rx_b[5]
85 set_location_assignment PIN_222 -to io_rx_b[6]
86 set_location_assignment PIN_223 -to io_rx_b[7]
87 set_location_assignment PIN_224 -to io_rx_b[8]
88 set_location_assignment PIN_225 -to io_rx_b[9]
89 set_location_assignment PIN_226 -to io_rx_b[10]
90 set_location_assignment PIN_227 -to io_rx_b[11]
91 set_location_assignment PIN_228 -to io_rx_b[12]
92 set_location_assignment PIN_233 -to io_rx_b[13]
93 set_location_assignment PIN_234 -to io_rx_b[14]
94 set_location_assignment PIN_175 -to io_tx_a[0]
95 set_location_assignment PIN_176 -to io_tx_a[1]
96 set_location_assignment PIN_177 -to io_tx_a[2]
97 set_location_assignment PIN_178 -to io_tx_a[3]
98 set_location_assignment PIN_179 -to io_tx_a[4]
99 set_location_assignment PIN_180 -to io_tx_a[5]
100 set_location_assignment PIN_181 -to io_tx_a[6]
101 set_location_assignment PIN_182 -to io_tx_a[7]
102 set_location_assignment PIN_183 -to io_tx_a[8]
103 set_location_assignment PIN_184 -to io_tx_a[9]
104 set_location_assignment PIN_185 -to io_tx_a[10]
105 set_location_assignment PIN_186 -to io_tx_a[11]
106 set_location_assignment PIN_187 -to io_tx_a[12]
107 set_location_assignment PIN_188 -to io_tx_a[13]
108 set_location_assignment PIN_193 -to io_tx_a[14]
109 set_location_assignment PIN_73 -to io_tx_b[0]
110 set_location_assignment PIN_68 -to io_tx_b[1]
111 set_location_assignment PIN_67 -to io_tx_b[2]
112 set_location_assignment PIN_66 -to io_tx_b[3]
113 set_location_assignment PIN_65 -to io_tx_b[4]
114 set_location_assignment PIN_64 -to io_tx_b[5]
115 set_location_assignment PIN_63 -to io_tx_b[6]
116 set_location_assignment PIN_62 -to io_tx_b[7]
117 set_location_assignment PIN_61 -to io_tx_b[8]
118 set_location_assignment PIN_60 -to io_tx_b[9]
119 set_location_assignment PIN_59 -to io_tx_b[10]
120 set_location_assignment PIN_58 -to io_tx_b[11]
121 set_location_assignment PIN_57 -to io_tx_b[12]
122 set_location_assignment PIN_56 -to io_tx_b[13]
123 set_location_assignment PIN_55 -to io_tx_b[14]
124 set_location_assignment PIN_152 -to master_clk
125 set_location_assignment PIN_144 -to rx_a_a[0]
126 set_location_assignment PIN_143 -to rx_a_a[1]
127 set_location_assignment PIN_141 -to rx_a_a[2]
128 set_location_assignment PIN_140 -to rx_a_a[3]
129 set_location_assignment PIN_139 -to rx_a_a[4]
130 set_location_assignment PIN_138 -to rx_a_a[5]
131 set_location_assignment PIN_137 -to rx_a_a[6]
132 set_location_assignment PIN_136 -to rx_a_a[7]
133 set_location_assignment PIN_135 -to rx_a_a[8]
134 set_location_assignment PIN_134 -to rx_a_a[9]
135 set_location_assignment PIN_133 -to rx_a_a[10]
136 set_location_assignment PIN_132 -to rx_a_a[11]
137 set_location_assignment PIN_23 -to rx_a_b[0]
138 set_location_assignment PIN_21 -to rx_a_b[1]
139 set_location_assignment PIN_20 -to rx_a_b[2]
140 set_location_assignment PIN_19 -to rx_a_b[3]
141 set_location_assignment PIN_18 -to rx_a_b[4]
142 set_location_assignment PIN_17 -to rx_a_b[5]
143 set_location_assignment PIN_16 -to rx_a_b[6]
144 set_location_assignment PIN_15 -to rx_a_b[7]
145 set_location_assignment PIN_14 -to rx_a_b[8]
146 set_location_assignment PIN_13 -to rx_a_b[9]
147 set_location_assignment PIN_12 -to rx_a_b[10]
148 set_location_assignment PIN_11 -to rx_a_b[11]
149 set_location_assignment PIN_131 -to rx_b_a[0]
150 set_location_assignment PIN_128 -to rx_b_a[1]
151 set_location_assignment PIN_127 -to rx_b_a[2]
152 set_location_assignment PIN_126 -to rx_b_a[3]
153 set_location_assignment PIN_125 -to rx_b_a[4]
154 set_location_assignment PIN_124 -to rx_b_a[5]
155 set_location_assignment PIN_123 -to rx_b_a[6]
156 set_location_assignment PIN_122 -to rx_b_a[7]
157 set_location_assignment PIN_121 -to rx_b_a[8]
158 set_location_assignment PIN_120 -to rx_b_a[9]
159 set_location_assignment PIN_119 -to rx_b_a[10]
160 set_location_assignment PIN_118 -to rx_b_a[11]
161 set_location_assignment PIN_8 -to rx_b_b[0]
162 set_location_assignment PIN_7 -to rx_b_b[1]
163 set_location_assignment PIN_6 -to rx_b_b[2]
164 set_location_assignment PIN_5 -to rx_b_b[3]
165 set_location_assignment PIN_4 -to rx_b_b[4]
166 set_location_assignment PIN_3 -to rx_b_b[5]
167 set_location_assignment PIN_2 -to rx_b_b[6]
168 set_location_assignment PIN_240 -to rx_b_b[7]
169 set_location_assignment PIN_239 -to rx_b_b[8]
170 set_location_assignment PIN_238 -to rx_b_b[9]
171 set_location_assignment PIN_237 -to rx_b_b[10]
172 set_location_assignment PIN_236 -to rx_b_b[11]
173 set_location_assignment PIN_156 -to SDO
174 set_location_assignment PIN_153 -to SEN_FPGA
175 set_location_assignment PIN_159 -to tx_a[0]
176 set_location_assignment PIN_160 -to tx_a[1]
177 set_location_assignment PIN_161 -to tx_a[2]
178 set_location_assignment PIN_162 -to tx_a[3]
179 set_location_assignment PIN_163 -to tx_a[4]
180 set_location_assignment PIN_164 -to tx_a[5]
181 set_location_assignment PIN_165 -to tx_a[6]
182 set_location_assignment PIN_166 -to tx_a[7]
183 set_location_assignment PIN_167 -to tx_a[8]
184 set_location_assignment PIN_168 -to tx_a[9]
185 set_location_assignment PIN_169 -to tx_a[10]
186 set_location_assignment PIN_170 -to tx_a[11]
187 set_location_assignment PIN_173 -to tx_a[12]
188 set_location_assignment PIN_174 -to tx_a[13]
189 set_location_assignment PIN_38 -to tx_b[0]
190 set_location_assignment PIN_39 -to tx_b[1]
191 set_location_assignment PIN_41 -to tx_b[2]
192 set_location_assignment PIN_42 -to tx_b[3]
193 set_location_assignment PIN_43 -to tx_b[4]
194 set_location_assignment PIN_44 -to tx_b[5]
195 set_location_assignment PIN_45 -to tx_b[6]
196 set_location_assignment PIN_46 -to tx_b[7]
197 set_location_assignment PIN_47 -to tx_b[8]
198 set_location_assignment PIN_48 -to tx_b[9]
199 set_location_assignment PIN_49 -to tx_b[10]
200 set_location_assignment PIN_50 -to tx_b[11]
201 set_location_assignment PIN_53 -to tx_b[12]
202 set_location_assignment PIN_54 -to tx_b[13]
203 set_location_assignment PIN_158 -to TXSYNC_A
204 set_location_assignment PIN_37 -to TXSYNC_B
205 set_location_assignment PIN_235 -to io_rx_b[15]
206 set_location_assignment PIN_24 -to io_tx_b[15]
207 set_location_assignment PIN_213 -to io_rx_a[15]
208 set_location_assignment PIN_194 -to io_tx_a[15]
209 set_location_assignment PIN_1 -to MYSTERY_SIGNAL
211 # Classic Timing Assignments
212 # ==========================
213 set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF
214 set_global_assignment -name MAX_SCC_SIZE 50
216 # Analysis & Synthesis Assignments
217 # ================================
218 set_global_assignment -name SAVE_DISK_SPACE OFF
219 set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP"
220 set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240
221 set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
222 set_global_assignment -name FAMILY Cyclone
223 set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE BALANCED
224 set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED
225 set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED
226 set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
227 set_global_assignment -name USER_LIBRARIES "h:\\gnuradio\\trunk\\usrp\\fpga\\megacells"
228 set_global_assignment -name AUTO_ENABLE_SMART_COMPILE ON
229 set_global_assignment -name TOP_LEVEL_ENTITY usrp_radar_mono
233 set_global_assignment -name DEVICE EP1C12Q240C8
234 set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "PASSIVE SERIAL"
235 set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
236 set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
237 set_global_assignment -name OPTIMIZE_TIMING "NORMAL COMPILATION"
238 set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF
239 set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF
240 set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
241 set_global_assignment -name IO_PLACEMENT_OPTIMIZATION ON
242 set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL
243 set_global_assignment -name INC_PLC_MODE OFF
244 set_global_assignment -name ROUTING_BACK_ANNOTATION_MODE OFF
245 set_instance_assignment -name IO_STANDARD LVTTL -to usbdata[12]
246 set_global_assignment -name STRATIX_DEVICE_IO_STANDARD LVTTL
247 set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
249 # EDA Netlist Writer Assignments
250 # ==============================
251 set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
252 set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<NONE>"
253 set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<NONE>"
254 set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<NONE>"
255 set_global_assignment -name EDA_RESYNTHESIS_TOOL "<NONE>"
257 # Assembler Assignments
258 # =====================
259 set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
260 set_global_assignment -name GENERATE_RBF_FILE ON
261 set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
262 set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF
264 # Simulator Assignments
265 # =====================
266 set_global_assignment -name START_TIME "0 ns"
267 set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE
269 # Design Assistant Assignments
270 # ============================
271 set_global_assignment -name DRC_REPORT_TOP_FANOUT OFF
272 set_global_assignment -name DRC_REPORT_FANOUT_EXCEEDING OFF
273 set_global_assignment -name ASSG_CAT OFF
274 set_global_assignment -name ASSG_RULE_MISSING_FMAX OFF
275 set_global_assignment -name ASSG_RULE_MISSING_TIMING OFF
276 set_global_assignment -name NONSYNCHSTRUCT_RULE_ASYN_RAM OFF
277 set_global_assignment -name CLK_CAT OFF
278 set_global_assignment -name CLK_RULE_COMB_CLOCK OFF
279 set_global_assignment -name CLK_RULE_INV_CLOCK OFF
280 set_global_assignment -name CLK_RULE_GATING_SCHEME OFF
281 set_global_assignment -name CLK_RULE_INPINS_CLKNET OFF
282 set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES OFF
283 set_global_assignment -name CLK_RULE_MIX_EDGES OFF
284 set_global_assignment -name RESET_CAT OFF
285 set_global_assignment -name RESET_RULE_INPINS_RESETNET OFF
286 set_global_assignment -name RESET_RULE_UNSYNCH_EXRESET OFF
287 set_global_assignment -name RESET_RULE_IMSYNCH_EXRESET OFF
288 set_global_assignment -name RESET_RULE_COMB_ASYNCH_RESET OFF
289 set_global_assignment -name RESET_RULE_UNSYNCH_ASYNCH_DOMAIN OFF
290 set_global_assignment -name RESET_RULE_IMSYNCH_ASYNCH_DOMAIN OFF
291 set_global_assignment -name TIMING_CAT OFF
292 set_global_assignment -name TIMING_RULE_SHIFT_REG OFF
293 set_global_assignment -name TIMING_RULE_COIN_CLKEDGE OFF
294 set_global_assignment -name NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE OFF
295 set_global_assignment -name NONSYNCHSTRUCT_CAT OFF
296 set_global_assignment -name NONSYNCHSTRUCT_RULE_COMBLOOP OFF
297 set_global_assignment -name NONSYNCHSTRUCT_RULE_REG_LOOP OFF
298 set_global_assignment -name NONSYNCHSTRUCT_RULE_DELAY_CHAIN OFF
299 set_global_assignment -name NONSYNCHSTRUCT_RULE_RIPPLE_CLK OFF
300 set_global_assignment -name NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN OFF
301 set_global_assignment -name NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR OFF
302 set_global_assignment -name NONSYNCHSTRUCT_RULE_SRLATCH OFF
303 set_global_assignment -name NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED OFF
304 set_global_assignment -name SIGNALRACE_CAT OFF
305 set_global_assignment -name ACLK_CAT OFF
306 set_global_assignment -name ACLK_RULE_NO_SZER_ACLK_DOMAIN OFF
307 set_global_assignment -name ACLK_RULE_SZER_BTW_ACLK_DOMAIN OFF
308 set_global_assignment -name ACLK_RULE_IMSZER_ADOMAIN OFF
309 set_global_assignment -name HCPY_CAT OFF
310 set_global_assignment -name HCPY_VREF_PINS OFF
311 set_global_assignment -name ENABLE_DA_RULE "C101, C102, C103, C104, C105, C106, R101, R102, R103, R104, R105, T101, T102, A101, A102, A103, A104, A105, A106, A107, A108, A109, A110, S101, S102, D101, D102, D103, H102"
312 set_global_assignment -name DISABLE_DA_RULE H101
314 # SignalTap II Assignments
315 # ========================
316 set_global_assignment -name HUB_ENTITY_NAME SLD_HUB
317 set_global_assignment -name HUB_INSTANCE_NAME SLD_HUB_INST
318 set_global_assignment -name ENABLE_SIGNALTAP OFF
320 # LogicLock Region Assignments
321 # ============================
322 set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT OFF
327 # Classic Timing Assignments
328 # ==========================
329 set_global_assignment -name DUTY_CYCLE 50 -section_id SCLK
330 set_global_assignment -name FMAX_REQUIREMENT "1 MHz" -section_id SCLK
335 # start CLOCK(master_clk)
336 # -----------------------
338 # Classic Timing Assignments
339 # ==========================
340 set_global_assignment -name DUTY_CYCLE 50 -section_id master_clk
341 set_global_assignment -name FMAX_REQUIREMENT "64 MHz" -section_id master_clk
343 # end CLOCK(master_clk)
344 # ---------------------
346 # start CLOCK(usbclk)
347 # -------------------
349 # Classic Timing Assignments
350 # ==========================
351 set_global_assignment -name DUTY_CYCLE 50 -section_id usbclk
352 set_global_assignment -name FMAX_REQUIREMENT "48 MHz" -section_id usbclk
357 # -----------------------------
358 # start ENTITY(usrp_radar_mono)
360 # Classic Timing Assignments
361 # ==========================
362 set_instance_assignment -name CLOCK_SETTINGS SCLK -to SCLK
363 set_instance_assignment -name CLOCK_SETTINGS usbclk -to usbclk
364 set_instance_assignment -name CLOCK_SETTINGS master_clk -to master_clk
366 # start DESIGN_PARTITION(Top)
367 # ---------------------------
369 # Incremental Compilation Assignments
370 # ===================================
371 set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top
372 set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
374 # end DESIGN_PARTITION(Top)
375 # -------------------------
377 # end ENTITY(usrp_radar_mono)
378 # ---------------------------
379 set_global_assignment -name VERILOG_FILE usrp_radar_mono.v
380 set_global_assignment -name VERILOG_FILE dacpll.v
381 set_global_assignment -name VERILOG_FILE ../lib/cordic_nco.v
382 set_global_assignment -name VERILOG_FILE ../lib/dac_interface.v
383 set_global_assignment -name VERILOG_FILE ../lib/fifo32_2k.v
384 set_global_assignment -name VERILOG_FILE ../lib/radar_control.v
385 set_global_assignment -name VERILOG_FILE ../lib/radar_rx.v
386 set_global_assignment -name VERILOG_FILE ../lib/radar_tx.v
387 set_global_assignment -name VERILOG_FILE ../lib/radar.v
388 set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/adc_interface.v
389 set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/atr_delay.v
390 set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/bidir_reg.v
391 set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/clk_divider.v
392 set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/cordic_stage.v
393 set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/cordic.v
394 set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/gen_sync.v
395 set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/io_pins.v
396 set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/master_control.v
397 set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/rssi.v
398 set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/rx_buffer.v
399 set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/rx_dcoffset.v
400 set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/serial_io.v
401 set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/setting_reg.v
402 set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/strobe_gen.v
projects / debian / gnuradio / blob