1 # Copyright (C) 1991-2005 Altera Corporation
2 # Your use of Altera Corporation's design tools, logic functions
3 # and other software and tools, and its AMPP partner logic
4 # functions, and any output files any of the foregoing
5 # (including device programming or simulation files), and any
6 # associated documentation or information are expressly subject
7 # to the terms and conditions of the Altera Program License
8 # Subscription Agreement, Altera MegaCore Function License
9 # Agreement, or other applicable license agreement, including,
10 # without limitation, that your use is for the sole purpose of
11 # programming logic devices manufactured by Altera and sold by
12 # Altera or its authorized distributors. Please refer to the
13 # applicable agreement for further details.
16 # The default values for assignments are stored in the file
17 # usrp_inband_usb_assignment_defaults.qdf
18 # If this file doesn't exist, and for assignments not listed, see file
19 # assignment_defaults.qdf
21 # Altera recommends that you do not modify this file. This
22 # file is updated automatically by the Quartus II software
23 # and any changes you make may be lost or overwritten.
26 # Project-Wide Assignments
27 # ========================
28 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 3.0
29 set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:14:04 JULY 13, 2003"
30 set_global_assignment -name LAST_QUARTUS_VERSION "7.2 SP2"
32 # Pin & Location Assignments
33 # ==========================
34 set_global_assignment -name RESERVE_PIN "AS INPUT TRI-STATED"
35 set_location_assignment PIN_29 -to SCLK
36 set_location_assignment PIN_117 -to SDI
37 set_location_assignment PIN_28 -to usbclk
38 set_location_assignment PIN_107 -to usbctl[0]
39 set_location_assignment PIN_106 -to usbctl[1]
40 set_location_assignment PIN_105 -to usbctl[2]
41 set_location_assignment PIN_100 -to usbdata[0]
42 set_location_assignment PIN_84 -to usbdata[10]
43 set_location_assignment PIN_83 -to usbdata[11]
44 set_location_assignment PIN_82 -to usbdata[12]
45 set_location_assignment PIN_79 -to usbdata[13]
46 set_location_assignment PIN_78 -to usbdata[14]
47 set_location_assignment PIN_77 -to usbdata[15]
48 set_location_assignment PIN_99 -to usbdata[1]
49 set_location_assignment PIN_98 -to usbdata[2]
50 set_location_assignment PIN_95 -to usbdata[3]
51 set_location_assignment PIN_94 -to usbdata[4]
52 set_location_assignment PIN_93 -to usbdata[5]
53 set_location_assignment PIN_88 -to usbdata[6]
54 set_location_assignment PIN_87 -to usbdata[7]
55 set_location_assignment PIN_86 -to usbdata[8]
56 set_location_assignment PIN_85 -to usbdata[9]
57 set_location_assignment PIN_104 -to usbrdy[0]
58 set_location_assignment PIN_101 -to usbrdy[1]
59 set_location_assignment PIN_76 -to FX2_1
60 set_location_assignment PIN_75 -to FX2_2
61 set_location_assignment PIN_74 -to FX2_3
62 set_location_assignment PIN_116 -to io_rx_a[0]
63 set_location_assignment PIN_115 -to io_rx_a[1]
64 set_location_assignment PIN_114 -to io_rx_a[2]
65 set_location_assignment PIN_113 -to io_rx_a[3]
66 set_location_assignment PIN_108 -to io_rx_a[4]
67 set_location_assignment PIN_195 -to io_rx_a[5]
68 set_location_assignment PIN_196 -to io_rx_a[6]
69 set_location_assignment PIN_197 -to io_rx_a[7]
70 set_location_assignment PIN_200 -to io_rx_a[8]
71 set_location_assignment PIN_201 -to io_rx_a[9]
72 set_location_assignment PIN_202 -to io_rx_a[10]
73 set_location_assignment PIN_203 -to io_rx_a[11]
74 set_location_assignment PIN_206 -to io_rx_a[12]
75 set_location_assignment PIN_207 -to io_rx_a[13]
76 set_location_assignment PIN_208 -to io_rx_a[14]
77 set_location_assignment PIN_214 -to io_rx_b[0]
78 set_location_assignment PIN_215 -to io_rx_b[1]
79 set_location_assignment PIN_216 -to io_rx_b[2]
80 set_location_assignment PIN_217 -to io_rx_b[3]
81 set_location_assignment PIN_218 -to io_rx_b[4]
82 set_location_assignment PIN_219 -to io_rx_b[5]
83 set_location_assignment PIN_222 -to io_rx_b[6]
84 set_location_assignment PIN_223 -to io_rx_b[7]
85 set_location_assignment PIN_224 -to io_rx_b[8]
86 set_location_assignment PIN_225 -to io_rx_b[9]
87 set_location_assignment PIN_226 -to io_rx_b[10]
88 set_location_assignment PIN_227 -to io_rx_b[11]
89 set_location_assignment PIN_228 -to io_rx_b[12]
90 set_location_assignment PIN_233 -to io_rx_b[13]
91 set_location_assignment PIN_234 -to io_rx_b[14]
92 set_location_assignment PIN_175 -to io_tx_a[0]
93 set_location_assignment PIN_176 -to io_tx_a[1]
94 set_location_assignment PIN_177 -to io_tx_a[2]
95 set_location_assignment PIN_178 -to io_tx_a[3]
96 set_location_assignment PIN_179 -to io_tx_a[4]
97 set_location_assignment PIN_180 -to io_tx_a[5]
98 set_location_assignment PIN_181 -to io_tx_a[6]
99 set_location_assignment PIN_182 -to io_tx_a[7]
100 set_location_assignment PIN_183 -to io_tx_a[8]
101 set_location_assignment PIN_184 -to io_tx_a[9]
102 set_location_assignment PIN_185 -to io_tx_a[10]
103 set_location_assignment PIN_186 -to io_tx_a[11]
104 set_location_assignment PIN_187 -to io_tx_a[12]
105 set_location_assignment PIN_188 -to io_tx_a[13]
106 set_location_assignment PIN_193 -to io_tx_a[14]
107 set_location_assignment PIN_73 -to io_tx_b[0]
108 set_location_assignment PIN_68 -to io_tx_b[1]
109 set_location_assignment PIN_67 -to io_tx_b[2]
110 set_location_assignment PIN_66 -to io_tx_b[3]
111 set_location_assignment PIN_65 -to io_tx_b[4]
112 set_location_assignment PIN_64 -to io_tx_b[5]
113 set_location_assignment PIN_63 -to io_tx_b[6]
114 set_location_assignment PIN_62 -to io_tx_b[7]
115 set_location_assignment PIN_61 -to io_tx_b[8]
116 set_location_assignment PIN_60 -to io_tx_b[9]
117 set_location_assignment PIN_59 -to io_tx_b[10]
118 set_location_assignment PIN_58 -to io_tx_b[11]
119 set_location_assignment PIN_57 -to io_tx_b[12]
120 set_location_assignment PIN_56 -to io_tx_b[13]
121 set_location_assignment PIN_55 -to io_tx_b[14]
122 set_location_assignment PIN_152 -to master_clk
123 set_location_assignment PIN_144 -to rx_a_a[0]
124 set_location_assignment PIN_143 -to rx_a_a[1]
125 set_location_assignment PIN_141 -to rx_a_a[2]
126 set_location_assignment PIN_140 -to rx_a_a[3]
127 set_location_assignment PIN_139 -to rx_a_a[4]
128 set_location_assignment PIN_138 -to rx_a_a[5]
129 set_location_assignment PIN_137 -to rx_a_a[6]
130 set_location_assignment PIN_136 -to rx_a_a[7]
131 set_location_assignment PIN_135 -to rx_a_a[8]
132 set_location_assignment PIN_134 -to rx_a_a[9]
133 set_location_assignment PIN_133 -to rx_a_a[10]
134 set_location_assignment PIN_132 -to rx_a_a[11]
135 set_location_assignment PIN_23 -to rx_a_b[0]
136 set_location_assignment PIN_21 -to rx_a_b[1]
137 set_location_assignment PIN_20 -to rx_a_b[2]
138 set_location_assignment PIN_19 -to rx_a_b[3]
139 set_location_assignment PIN_18 -to rx_a_b[4]
140 set_location_assignment PIN_17 -to rx_a_b[5]
141 set_location_assignment PIN_16 -to rx_a_b[6]
142 set_location_assignment PIN_15 -to rx_a_b[7]
143 set_location_assignment PIN_14 -to rx_a_b[8]
144 set_location_assignment PIN_13 -to rx_a_b[9]
145 set_location_assignment PIN_12 -to rx_a_b[10]
146 set_location_assignment PIN_11 -to rx_a_b[11]
147 set_location_assignment PIN_131 -to rx_b_a[0]
148 set_location_assignment PIN_128 -to rx_b_a[1]
149 set_location_assignment PIN_127 -to rx_b_a[2]
150 set_location_assignment PIN_126 -to rx_b_a[3]
151 set_location_assignment PIN_125 -to rx_b_a[4]
152 set_location_assignment PIN_124 -to rx_b_a[5]
153 set_location_assignment PIN_123 -to rx_b_a[6]
154 set_location_assignment PIN_122 -to rx_b_a[7]
155 set_location_assignment PIN_121 -to rx_b_a[8]
156 set_location_assignment PIN_120 -to rx_b_a[9]
157 set_location_assignment PIN_119 -to rx_b_a[10]
158 set_location_assignment PIN_118 -to rx_b_a[11]
159 set_location_assignment PIN_8 -to rx_b_b[0]
160 set_location_assignment PIN_7 -to rx_b_b[1]
161 set_location_assignment PIN_6 -to rx_b_b[2]
162 set_location_assignment PIN_5 -to rx_b_b[3]
163 set_location_assignment PIN_4 -to rx_b_b[4]
164 set_location_assignment PIN_3 -to rx_b_b[5]
165 set_location_assignment PIN_2 -to rx_b_b[6]
166 set_location_assignment PIN_240 -to rx_b_b[7]
167 set_location_assignment PIN_239 -to rx_b_b[8]
168 set_location_assignment PIN_238 -to rx_b_b[9]
169 set_location_assignment PIN_237 -to rx_b_b[10]
170 set_location_assignment PIN_236 -to rx_b_b[11]
171 set_location_assignment PIN_156 -to SDO
172 set_location_assignment PIN_153 -to SEN_FPGA
173 set_location_assignment PIN_159 -to tx_a[0]
174 set_location_assignment PIN_160 -to tx_a[1]
175 set_location_assignment PIN_161 -to tx_a[2]
176 set_location_assignment PIN_162 -to tx_a[3]
177 set_location_assignment PIN_163 -to tx_a[4]
178 set_location_assignment PIN_164 -to tx_a[5]
179 set_location_assignment PIN_165 -to tx_a[6]
180 set_location_assignment PIN_166 -to tx_a[7]
181 set_location_assignment PIN_167 -to tx_a[8]
182 set_location_assignment PIN_168 -to tx_a[9]
183 set_location_assignment PIN_169 -to tx_a[10]
184 set_location_assignment PIN_170 -to tx_a[11]
185 set_location_assignment PIN_173 -to tx_a[12]
186 set_location_assignment PIN_174 -to tx_a[13]
187 set_location_assignment PIN_38 -to tx_b[0]
188 set_location_assignment PIN_39 -to tx_b[1]
189 set_location_assignment PIN_41 -to tx_b[2]
190 set_location_assignment PIN_42 -to tx_b[3]
191 set_location_assignment PIN_43 -to tx_b[4]
192 set_location_assignment PIN_44 -to tx_b[5]
193 set_location_assignment PIN_45 -to tx_b[6]
194 set_location_assignment PIN_46 -to tx_b[7]
195 set_location_assignment PIN_47 -to tx_b[8]
196 set_location_assignment PIN_48 -to tx_b[9]
197 set_location_assignment PIN_49 -to tx_b[10]
198 set_location_assignment PIN_50 -to tx_b[11]
199 set_location_assignment PIN_53 -to tx_b[12]
200 set_location_assignment PIN_54 -to tx_b[13]
201 set_location_assignment PIN_158 -to TXSYNC_A
202 set_location_assignment PIN_37 -to TXSYNC_B
203 set_location_assignment PIN_235 -to io_rx_b[15]
204 set_location_assignment PIN_24 -to io_tx_b[15]
205 set_location_assignment PIN_213 -to io_rx_a[15]
206 set_location_assignment PIN_194 -to io_tx_a[15]
207 set_location_assignment PIN_1 -to MYSTERY_SIGNAL
211 set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF
213 # Analysis & Synthesis Assignments
214 # ================================
215 set_global_assignment -name SAVE_DISK_SPACE OFF
216 set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP"
217 set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240
218 set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
219 set_global_assignment -name FAMILY Cyclone
220 set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE BALANCED
221 set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED
222 set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED
223 set_global_assignment -name TOP_LEVEL_ENTITY usrp_inband_usb
224 set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
225 set_global_assignment -name USER_LIBRARIES "e:\\usrp\\fpga\\megacells"
226 set_global_assignment -name AUTO_ENABLE_SMART_COMPILE ON
230 set_global_assignment -name DEVICE EP1C12Q240C8
231 set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "PASSIVE SERIAL"
232 set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
233 set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
234 set_global_assignment -name OPTIMIZE_TIMING "NORMAL COMPILATION"
235 set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF
236 set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF
237 set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
238 set_global_assignment -name IO_PLACEMENT_OPTIMIZATION OFF
239 set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL
240 set_global_assignment -name INC_PLC_MODE OFF
241 set_global_assignment -name ROUTING_BACK_ANNOTATION_MODE OFF
242 set_instance_assignment -name IO_STANDARD LVTTL -to usbdata[12]
243 set_global_assignment -name STRATIX_DEVICE_IO_STANDARD LVTTL
244 set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
246 # Timing Analysis Assignments
247 # ===========================
248 set_global_assignment -name MAX_SCC_SIZE 50
250 # EDA Netlist Writer Assignments
251 # ==============================
252 set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
253 set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<NONE>"
254 set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<NONE>"
255 set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<NONE>"
256 set_global_assignment -name EDA_RESYNTHESIS_TOOL "<NONE>"
258 # Assembler Assignments
259 # =====================
260 set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
261 set_global_assignment -name GENERATE_RBF_FILE ON
262 set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
263 set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF
265 # Simulator Assignments
266 # =====================
267 set_global_assignment -name START_TIME "0 ns"
268 set_global_assignment -name GLITCH_INTERVAL "1 ns"
270 # Design Assistant Assignments
271 # ============================
272 set_global_assignment -name DRC_REPORT_TOP_FANOUT OFF
273 set_global_assignment -name DRC_REPORT_FANOUT_EXCEEDING OFF
274 set_global_assignment -name ASSG_CAT OFF
275 set_global_assignment -name ASSG_RULE_MISSING_FMAX OFF
276 set_global_assignment -name ASSG_RULE_MISSING_TIMING OFF
277 set_global_assignment -name NONSYNCHSTRUCT_RULE_ASYN_RAM OFF
278 set_global_assignment -name CLK_CAT OFF
279 set_global_assignment -name CLK_RULE_COMB_CLOCK OFF
280 set_global_assignment -name CLK_RULE_INV_CLOCK OFF
281 set_global_assignment -name CLK_RULE_GATING_SCHEME OFF
282 set_global_assignment -name CLK_RULE_INPINS_CLKNET OFF
283 set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES OFF
284 set_global_assignment -name CLK_RULE_MIX_EDGES OFF
285 set_global_assignment -name RESET_CAT OFF
286 set_global_assignment -name RESET_RULE_INPINS_RESETNET OFF
287 set_global_assignment -name RESET_RULE_UNSYNCH_EXRESET OFF
288 set_global_assignment -name RESET_RULE_IMSYNCH_EXRESET OFF
289 set_global_assignment -name RESET_RULE_COMB_ASYNCH_RESET OFF
290 set_global_assignment -name RESET_RULE_UNSYNCH_ASYNCH_DOMAIN OFF
291 set_global_assignment -name RESET_RULE_IMSYNCH_ASYNCH_DOMAIN OFF
292 set_global_assignment -name TIMING_CAT OFF
293 set_global_assignment -name TIMING_RULE_SHIFT_REG OFF
294 set_global_assignment -name TIMING_RULE_COIN_CLKEDGE OFF
295 set_global_assignment -name NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE OFF
296 set_global_assignment -name NONSYNCHSTRUCT_CAT OFF
297 set_global_assignment -name NONSYNCHSTRUCT_RULE_COMBLOOP OFF
298 set_global_assignment -name NONSYNCHSTRUCT_RULE_REG_LOOP OFF
299 set_global_assignment -name NONSYNCHSTRUCT_RULE_DELAY_CHAIN OFF
300 set_global_assignment -name NONSYNCHSTRUCT_RULE_RIPPLE_CLK OFF
301 set_global_assignment -name NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN OFF
302 set_global_assignment -name NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR OFF
303 set_global_assignment -name NONSYNCHSTRUCT_RULE_SRLATCH OFF
304 set_global_assignment -name NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED OFF
305 set_global_assignment -name SIGNALRACE_CAT OFF
306 set_global_assignment -name ACLK_CAT OFF
307 set_global_assignment -name ACLK_RULE_NO_SZER_ACLK_DOMAIN OFF
308 set_global_assignment -name ACLK_RULE_SZER_BTW_ACLK_DOMAIN OFF
309 set_global_assignment -name ACLK_RULE_IMSZER_ADOMAIN OFF
310 set_global_assignment -name HCPY_CAT OFF
311 set_global_assignment -name HCPY_VREF_PINS OFF
313 # SignalTap II Assignments
314 # ========================
315 set_global_assignment -name HUB_ENTITY_NAME SLD_HUB
316 set_global_assignment -name HUB_INSTANCE_NAME SLD_HUB_INST
317 set_global_assignment -name ENABLE_SIGNALTAP OFF
319 # LogicLock Region Assignments
320 # ============================
321 set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT OFF
328 set_global_assignment -name DUTY_CYCLE 50 -section_id SCLK
329 set_global_assignment -name FMAX_REQUIREMENT "1 MHz" -section_id SCLK
330 set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id SCLK
335 # -----------------------
336 # start CLOCK(master_clk)
340 set_global_assignment -name DUTY_CYCLE 50 -section_id master_clk
341 set_global_assignment -name FMAX_REQUIREMENT "64 MHz" -section_id master_clk
342 set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id master_clk
344 # end CLOCK(master_clk)
345 # ---------------------
347 # -------------------
348 # start CLOCK(usbclk)
352 set_global_assignment -name DUTY_CYCLE 50 -section_id usbclk
353 set_global_assignment -name FMAX_REQUIREMENT "48 MHz" -section_id usbclk
354 set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id usbclk
359 # ----------------------
360 # start ENTITY(usrp_inband_usb)
364 set_instance_assignment -name CLOCK_SETTINGS SCLK -to SCLK
365 set_instance_assignment -name CLOCK_SETTINGS usbclk -to usbclk
366 set_instance_assignment -name CLOCK_SETTINGS master_clk -to master_clk
368 # end ENTITY(usrp_inband_usb)
369 # --------------------
372 set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top
373 set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
374 set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN "100 ps"
375 set_global_assignment -name VERILOG_FILE ../../megacells/fifo_4kx16_dc.v
376 set_global_assignment -name VERILOG_FILE ../../megacells/fifo_1kx16.v
377 set_global_assignment -name VERILOG_FILE ../../inband_lib/channel_demux.v
378 set_global_assignment -name VERILOG_FILE ../../inband_lib/tx_packer.v
379 set_global_assignment -name VERILOG_FILE ../../inband_lib/cmd_reader.v
380 set_global_assignment -name VERILOG_FILE ../../inband_lib/packet_builder.v
381 set_global_assignment -name VERILOG_FILE ../../inband_lib/rx_buffer_inband.v
382 set_global_assignment -name VERILOG_FILE ../../sdr_lib/atr_delay.v
383 set_global_assignment -name VERILOG_FILE ../../inband_lib/tx_buffer_inband.v
384 set_global_assignment -name VERILOG_FILE ../../inband_lib/chan_fifo_reader.v
385 set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_dec_shifter.v
386 set_global_assignment -name VERILOG_FILE ../../sdr_lib/rssi.v
387 set_global_assignment -name VERILOG_FILE ../../sdr_lib/ram16.v
388 set_global_assignment -name VERILOG_FILE ../../megacells/fifo_4k.v
389 set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/acc.v
390 set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/mult.v
391 set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/ram16_2sum.v
392 set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/coeff_rom.v
393 set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/halfband_decim.v
394 set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/mac.v
395 set_global_assignment -name VERILOG_FILE ../../sdr_lib/tx_chain.v
396 set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_dcoffset.v
397 set_global_assignment -name VERILOG_FILE ../../sdr_lib/adc_interface.v
398 set_global_assignment -name VERILOG_FILE ../../sdr_lib/io_pins.v
399 set_global_assignment -name VERILOG_FILE ../../sdr_lib/setting_reg.v
400 set_global_assignment -name VERILOG_FILE ../../sdr_lib/bidir_reg.v
401 set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_int_shifter.v
402 set_global_assignment -name VERILOG_FILE ../../megacells/clk_doubler.v
403 set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_chain.v
404 set_global_assignment -name VERILOG_FILE ../../sdr_lib/gen_sync.v
405 set_global_assignment -name VERILOG_FILE ../../sdr_lib/master_control.v
406 set_global_assignment -name VERILOG_FILE ../../megacells/fifo_2k.v
407 set_global_assignment -name VERILOG_FILE ../../megacells/bustri.v
408 set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_buffer.v
409 set_global_assignment -name VERILOG_FILE ../../sdr_lib/tx_buffer.v
410 set_global_assignment -name VERILOG_FILE ../../sdr_lib/phase_acc.v
411 set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_interp.v
412 set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_decim.v
413 set_global_assignment -name VERILOG_FILE ../../sdr_lib/cordic_stage.v
414 set_global_assignment -name VERILOG_FILE ../../sdr_lib/cordic.v
415 set_global_assignment -name VERILOG_FILE usrp_inband_usb.v
416 set_global_assignment -name VERILOG_FILE ../../sdr_lib/clk_divider.v
417 set_global_assignment -name VERILOG_FILE ../../sdr_lib/serial_io.v
418 set_global_assignment -name VERILOG_FILE ../../sdr_lib/strobe_gen.v
419 set_global_assignment -name VERILOG_FILE ../../sdr_lib/sign_extend.v
420 set_global_assignment -name VERILOG_FILE ../../inband_lib/channel_ram.v
421 set_global_assignment -name VERILOG_FILE ../../inband_lib/register_io.v
422 set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
423 set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
projects / debian / gnuradio / blob