fix errant boundary line

diff --git a/telebt.pcb b/telebt.pcb
index 2a5dd2e4c226beaaaa1c12131e78f4c23b6db03d..5c5c294c41298839a4b9b2238ad179ec074b64c4 100644 (file)
--- a/telebt.pcb
+++ b/telebt.pcb
@@ -1507,7 +1507,7 @@ Layer(1 "top")
        Line[24606 133854 24606 121063 600 2000 "clearline,lock"]
        Line[12795 109252 0 109252 600 2000 "clearline,lock"]
        Line[3927 0 266732 0 600 2000 "clearline,lock"]
-       Line[278543 24606 913398 24606 600 2000 "clearline,lock"]
+       Line[278543 24606 291339 24606 600 2000 "clearline,lock"]
        Line[266732 0 266732 12795 600 2000 "clearline,lock"]
        Line[0 109252 0 3937 600 2000 "clearline,lock"]
        Line[148267 78386 138780 70079 1000 2000 "clearline"]