From 0049d9164fc8f6bc7410a6af45a3f0dc296645b6 Mon Sep 17 00:00:00 2001
From: Bdale Garbee <bdale@gag.com>
Date: Sun, 11 Sep 2011 21:38:09 -0600
Subject: [PATCH] fix errant boundary line

---
 telebt.pcb | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/telebt.pcb b/telebt.pcb
index 2a5dd2e..5c5c294 100644
--- a/telebt.pcb
+++ b/telebt.pcb
@@ -1507,7 +1507,7 @@ Layer(1 "top")
 	Line[24606 133854 24606 121063 600 2000 "clearline,lock"]
 	Line[12795 109252 0 109252 600 2000 "clearline,lock"]
 	Line[3927 0 266732 0 600 2000 "clearline,lock"]
-	Line[278543 24606 913398 24606 600 2000 "clearline,lock"]
+	Line[278543 24606 291339 24606 600 2000 "clearline,lock"]
 	Line[266732 0 266732 12795 600 2000 "clearline,lock"]
 	Line[0 109252 0 3937 600 2000 "clearline,lock"]
 	Line[148267 78386 138780 70079 1000 2000 "clearline"]
-- 
2.30.2