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make sure all silk elements are within pcb outline
2010-11-23 Bdale Garbeemake sure all silk elements are within pcb outline
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2010-11-23 Bdale Garbeetweaking silk and attributes
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2010-11-18 Bdale Garbeenew footprint for the IC with vias, DRC clean again
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2010-11-18 Bdale Garbeeadd explicit netlist connection for exposed ground...
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2010-11-18 Bdale Garbeemove vias outside the battery connector pads
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2010-11-11 Bdale Garbeeadd targets for automating outputs
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2010-11-11 Bdale Garbeefix layout name
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2010-11-11 Bdale Garbeefix DFM identified soldermask issues
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2010-11-11 Bdale Garbeetweaks based on freedfm.com output
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2010-11-05 Bdale Garbeeground prog2, fatten supply and output traces
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2010-11-05 Bdale Garbeeenabling outline layer causes bogus drc errors, so...
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2010-11-04 Bdale Garbeeinitial capture of LiPo charger
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charger for single-cell Lithium Polymer batteries