+# Main file for NXP LPC11Uxx Cortex-M0
+#
+# !!!!!!
+#
+# This file should not be included directly, rather
+# by the lpc11u12.cfg, lpc11u14.cfg, etc. which set the
+# needed variables to the appropriate values.
+#
+# !!!!!!
+
+# LPC11Uxx chips support both JTAG and SWD transports.
+# Adapt based on what transport is active.
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ error "_CHIPNAME not set. Please do not include lpc11uxx.cfg directly, but the specific chip configuration file (lpc11u12.cfg, lpc11u14.cfg, etc)."
+}
+
+# After reset the chip is clocked by the ~12MHz internal RC oscillator.
+# When board-specific code (reset-init handler or device firmware)
+# configures another oscillator and/or PLL0, set CCLK to match; if
+# you don't, then flash erase and write operations may misbehave.
+# (The ROM code doing those updates cares about core clock speed...)
+#
+# CCLK is the core clock frequency in KHz
+if { [info exists CCLK] } {
+ set _CCLK $CCLK
+} else {
+ set _CCLK 12000
+}
+
+if { [info exists CPUTAPID] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ error "_CPUTAPID not set. Please do not include lpc11uxx.cfg directly, but the specific chip configuration file (lpc11u12.cfg, lpc11u14.cfg, etc)."
+}
+
+if { [info exists CPURAMSIZE] } {
+ set _CPURAMSIZE $CPURAMSIZE
+} else {
+ error "_CPURAMSIZE not set. Please do not include lpc11uxx.cfg directly, but the specific chip configuration file (lpc11u12.cfg, lpc11u14.cfg, etc)."
+}
+
+if { [info exists CPUROMSIZE] } {
+ set _CPUROMSIZE $CPUROMSIZE
+} else {
+ error "_CPUROMSIZE not set. Please do not include lpc11uxx.cfg directly, but the specific chip configuration file (lpc11u12.cfg, lpc11u14.cfg, etc)."
+}
+
+if { [info exists TRANSPORT] } {
+ set _TRANSPORT $TRANSPORT
+} else {
+ set _TRANSPORT stlink_swd
+}
+
+transport select $_TRANSPORT
+
+stlink newtap $_CHIPNAME cpu -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME stm32_stlink -chain-position $_TARGETNAME
+
+# The LPC11Uxx devices have 4/6/8kB of SRAM In the ARMv6-M "Code" area (at 0x10000000)
+$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_CPURAMSIZE
+
+# The LPC11Uxx devices have 16/24/32kB of flash memory, managed by ROM code
+# (including a boot loader which verifies the flash exception table's checksum).
+# flash bank <name> lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc checksum]
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME lpc2000 0x0 $_CPUROMSIZE 0 0 $_TARGETNAME lpc11u $_CCLK calc_checksum
+
+$_TARGETNAME configure -event reset-init {
+ # Do not remap 0x0000-0x0200 to anything but the flash (i.e. select
+ # "User Flash Mode" where interrupt vectors are _not_ remapped,
+ # and reside in flash instead).
+ #
+ # See Table 7. System memory remap register (SYSMEMREMAP, address 0x4004 8000) bit description
+ # Bit Symbol Value Description Reset value
+ # 1:0 MAP Memory map control. 0
+ # 0x0 Boot Loader Mode. Interrupt vectors are re-mapped to Boot ROM.
+ # 0x1 User RAM Mode. Interrupt vectors are re-mapped to Static RAM.
+ # 0x2 User Flash Mode. Interrupt vectors are not re-mapped and reside in Flash.
+ # 31:2 - - Reserved. The value read from a reserved bit is not defined. NA
+
+ mww 0x40048000 0x02
+}