1 # NXP LPC11U14 Cortex-M0 with 32kB Flash and 4kB Local On-Chip SRAM,
4 set CPUTAPID 0x0bb11477
8 # After reset the chip is clocked by the ~12MHz internal RC oscillator.
9 # When board-specific code (reset-init handler or device firmware)
10 # configures another oscillator and/or PLL0, set CCLK to match; if
11 # you don't, then flash erase and write operations may misbehave.
12 # (The ROM code doing those updates cares about core clock speed...)
14 # CCLK is the core clock frequency in KHz
17 # Include the main configuration file.
18 source [find target/lpc11uxx_stlink.cfg]