1 # Main file for NXP LPC11Uxx Cortex-M0
5 # This file should not be included directly, rather
6 # by the lpc11u12.cfg, lpc11u14.cfg, etc. which set the
7 # needed variables to the appropriate values.
11 # LPC11Uxx chips support both JTAG and SWD transports.
12 # Adapt based on what transport is active.
13 source [find target/swj-dp.tcl]
15 if { [info exists CHIPNAME] } {
16 set _CHIPNAME $CHIPNAME
18 error "_CHIPNAME not set. Please do not include lpc11uxx.cfg directly, but the specific chip configuration file (lpc11u12.cfg, lpc11u14.cfg, etc)."
21 # After reset the chip is clocked by the ~12MHz internal RC oscillator.
22 # When board-specific code (reset-init handler or device firmware)
23 # configures another oscillator and/or PLL0, set CCLK to match; if
24 # you don't, then flash erase and write operations may misbehave.
25 # (The ROM code doing those updates cares about core clock speed...)
27 # CCLK is the core clock frequency in KHz
28 if { [info exists CCLK] } {
34 if { [info exists CPUTAPID] } {
35 set _CPUTAPID $CPUTAPID
37 error "_CPUTAPID not set. Please do not include lpc11uxx.cfg directly, but the specific chip configuration file (lpc11u12.cfg, lpc11u14.cfg, etc)."
40 if { [info exists CPURAMSIZE] } {
41 set _CPURAMSIZE $CPURAMSIZE
43 error "_CPURAMSIZE not set. Please do not include lpc11uxx.cfg directly, but the specific chip configuration file (lpc11u12.cfg, lpc11u14.cfg, etc)."
46 if { [info exists CPUROMSIZE] } {
47 set _CPUROMSIZE $CPUROMSIZE
49 error "_CPUROMSIZE not set. Please do not include lpc11uxx.cfg directly, but the specific chip configuration file (lpc11u12.cfg, lpc11u14.cfg, etc)."
52 if { [info exists TRANSPORT] } {
53 set _TRANSPORT $TRANSPORT
55 set _TRANSPORT stlink_swd
58 transport select $_TRANSPORT
60 stlink newtap $_CHIPNAME cpu -expected-id $_CPUTAPID
62 set _TARGETNAME $_CHIPNAME.cpu
63 target create $_TARGETNAME stm32_stlink -chain-position $_TARGETNAME
65 # The LPC11Uxx devices have 4/6/8kB of SRAM In the ARMv6-M "Code" area (at 0x10000000)
66 $_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_CPURAMSIZE
68 # The LPC11Uxx devices have 16/24/32kB of flash memory, managed by ROM code
69 # (including a boot loader which verifies the flash exception table's checksum).
70 # flash bank <name> lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc checksum]
71 set _FLASHNAME $_CHIPNAME.flash
72 flash bank $_FLASHNAME lpc2000 0x0 $_CPUROMSIZE 0 0 $_TARGETNAME lpc11u $_CCLK calc_checksum
74 $_TARGETNAME configure -event reset-init {
75 # Do not remap 0x0000-0x0200 to anything but the flash (i.e. select
76 # "User Flash Mode" where interrupt vectors are _not_ remapped,
77 # and reside in flash instead).
79 # See Table 7. System memory remap register (SYSMEMREMAP, address 0x4004 8000) bit description
80 # Bit Symbol Value Description Reset value
81 # 1:0 MAP Memory map control. 0
82 # 0x0 Boot Loader Mode. Interrupt vectors are re-mapped to Boot ROM.
83 # 0x1 User RAM Mode. Interrupt vectors are re-mapped to Static RAM.
84 # 0x2 User Flash Mode. Interrupt vectors are not re-mapped and reside in Flash.
85 # 31:2 - - Reserved. The value read from a reserved bit is not defined. NA