altos/stm32f4: Wrong value for CK48MSEL_PLL_Q

This meant that the USB clock wasn't actually getting started...

Signed-off-by: Keith Packard <keithp@keithp.com>

diff --git a/src/stm32f4/ao_exti.h b/src/stm32f4/ao_exti.h
index 0216f3528822d0271d42dff1716ae72577983637..032466058ed2cb7a4afb55db3e77669142c4ba56 100644 (file)
--- a/src/stm32f4/ao_exti.h
+++ b/src/stm32f4/ao_exti.h
@@ -30,13 +30,13 @@
 #define AO_EXTI_PIN_NOCONFIGURE        64
 
 void
 #define AO_EXTI_PIN_NOCONFIGURE        64
 
 void

-ao_exti_setup(struct stm_gpio *gpio, uint8_t pin, uint8_t mode, void (*callback)());
+ao_exti_setup(struct stm_gpio *gpio, uint8_t pin, uint8_t mode, void (*callback)(void));

 
 void
 ao_exti_set_mode(struct stm_gpio *gpio, uint8_t pin, uint8_t mode);
 
 void
 
 void
 ao_exti_set_mode(struct stm_gpio *gpio, uint8_t pin, uint8_t mode);
 
 void

-ao_exti_set_callback(struct stm_gpio *gpio, uint8_t pin, void (*callback)());
+ao_exti_set_callback(struct stm_gpio *gpio, uint8_t pin, void (*callback)(void));

 
 void
 ao_exti_enable(struct stm_gpio *gpio, uint8_t pin);
 
 void
 ao_exti_enable(struct stm_gpio *gpio, uint8_t pin);

diff --git a/src/stm32f4/ao_exti_stm32f4.c b/src/stm32f4/ao_exti_stm32f4.c
index 1e288f9c6ef5b4b1308782a6498105c0f3b5d81b..900fe90318623635436dd18229567c839d4ad1f8 100644 (file)
--- a/src/stm32f4/ao_exti_stm32f4.c
+++ b/src/stm32f4/ao_exti_stm32f4.c
@@ -135,7 +135,7 @@ ao_exti_set_mode(struct stm_gpio *gpio, uint8_t pin, uint8_t mode) {
 }
 
 void
 }
 
 void

-ao_exti_set_callback(struct stm_gpio *gpio, uint8_t pin, void (*callback)()) {
+ao_exti_set_callback(struct stm_gpio *gpio, uint8_t pin, void (*callback)(void)) {

        (void) gpio;
        ao_exti_callback[pin] = callback;
 }
        (void) gpio;
        ao_exti_callback[pin] = callback;
 }

diff --git a/src/stm32f4/stm32f4.h b/src/stm32f4/stm32f4.h
index 3e8ec95776678b7bdbc914d474a1d7868b8fc592..94ee23bf9e83e25b55154fdb7014cfabdd696e25 100644 (file)
--- a/src/stm32f4/stm32f4.h
+++ b/src/stm32f4/stm32f4.h
@@ -269,7 +269,7 @@ extern struct stm_rcc stm_rcc;
 #define  STM_RCC_DCKCFGR2_SDIOSEL_CK_48MHZ     0
 #define  STM_RCC_DCKCFGR2_SDIOSEL_SYSTEM_CLOCK 1
 #define STM_RCC_DCKCFGR2_CK48MSEL      27
 #define  STM_RCC_DCKCFGR2_SDIOSEL_CK_48MHZ     0
 #define  STM_RCC_DCKCFGR2_SDIOSEL_SYSTEM_CLOCK 1
 #define STM_RCC_DCKCFGR2_CK48MSEL      27

-#define  STM_RCC_DCKCFGR2_CK48MSEL_PLL_Q       1
+#define  STM_RCC_DCKCFGR2_CK48MSEL_PLL_Q       0

 #define  STM_RCC_DCKCFGR2_CK48MSEL_PLLI2S_Q    1
 #define STM_RCC_DCKCFGR2_I2CFMP1SEL    22
 #define  STM_RCC_DCKCFGR2_I2CFMP1SEL_APB               0
 #define  STM_RCC_DCKCFGR2_CK48MSEL_PLLI2S_Q    1
 #define STM_RCC_DCKCFGR2_I2CFMP1SEL    22
 #define  STM_RCC_DCKCFGR2_I2CFMP1SEL_APB               0