This was reported as necessary; I have no idea, but it's not
expensive, so why not...
Signed-off-by: Keith Packard <keithp@keithp.com>
-ao_arch_memory_barrier() {
+ao_arch_memory_barrier(void) {
asm volatile("" ::: "memory");
}
asm volatile("" ::: "memory");
}
static inline void ao_enable_port(struct stm_gpio *port)
{
if ((port) == &stm_gpioa) {
static inline void ao_enable_port(struct stm_gpio *port)
{
if ((port) == &stm_gpioa) {
- stm_rcc.ahb1enr |= (1 << STM_RCC_AHB1ENR_IOPAEN);
+ stm_rcc_ahb1_clk_enable(1 << STM_RCC_AHB1ENR_IOPAEN);
ao_power_register(&ao_power_gpioa);
} else if ((port) == &stm_gpiob) {
ao_power_register(&ao_power_gpioa);
} else if ((port) == &stm_gpiob) {
- stm_rcc.ahb1enr |= (1 << STM_RCC_AHB1ENR_IOPBEN);
+ stm_rcc_ahb1_clk_enable(1 << STM_RCC_AHB1ENR_IOPBEN);
ao_power_register(&ao_power_gpiob);
} else if ((port) == &stm_gpioc) {
ao_power_register(&ao_power_gpiob);
} else if ((port) == &stm_gpioc) {
- stm_rcc.ahb1enr |= (1 << STM_RCC_AHB1ENR_IOPCEN);
+ stm_rcc_ahb1_clk_enable(1 << STM_RCC_AHB1ENR_IOPCEN);
ao_power_register(&ao_power_gpioc);
} else if ((port) == &stm_gpiod) {
ao_power_register(&ao_power_gpioc);
} else if ((port) == &stm_gpiod) {
- stm_rcc.ahb1enr |= (1 << STM_RCC_AHB1ENR_IOPDEN);
+ stm_rcc_ahb1_clk_enable(1 << STM_RCC_AHB1ENR_IOPDEN);
ao_power_register(&ao_power_gpiod);
} else if ((port) == &stm_gpioe) {
ao_power_register(&ao_power_gpiod);
} else if ((port) == &stm_gpioe) {
- stm_rcc.ahb1enr |= (1 << STM_RCC_AHB1ENR_IOPEEN);
+ stm_rcc_ahb1_clk_enable(1 << STM_RCC_AHB1ENR_IOPEEN);
ao_power_register(&ao_power_gpioe);
} else if ((port) == &stm_gpiof) {
ao_power_register(&ao_power_gpioe);
} else if ((port) == &stm_gpiof) {
- stm_rcc.ahb1enr |= (1 << STM_RCC_AHB1ENR_IOPFEN);
+ stm_rcc_ahb1_clk_enable(1 << STM_RCC_AHB1ENR_IOPFEN);
ao_power_register(&ao_power_gpiof);
} else if ((port) == &stm_gpiog) {
ao_power_register(&ao_power_gpiof);
} else if ((port) == &stm_gpiog) {
- stm_rcc.ahb1enr |= (1 << STM_RCC_AHB1ENR_IOPGEN);
+ stm_rcc_ahb1_clk_enable(1 << STM_RCC_AHB1ENR_IOPGEN);
ao_power_register(&ao_power_gpiog);
} else if ((port) == &stm_gpioh) {
ao_power_register(&ao_power_gpiog);
} else if ((port) == &stm_gpioh) {
- stm_rcc.ahb1enr |= (1 << STM_RCC_AHB1ENR_IOPHEN);
+ stm_rcc_ahb1_clk_enable(1 << STM_RCC_AHB1ENR_IOPHEN);
ao_power_register(&ao_power_gpioh);
}
}
ao_power_register(&ao_power_gpioh);
}
}
static inline void ao_disable_port(struct stm_gpio *port)
{
if ((port) == &stm_gpioa) {
static inline void ao_disable_port(struct stm_gpio *port)
{
if ((port) == &stm_gpioa) {
- stm_rcc.ahb1enr &= ~(1 << STM_RCC_AHB1ENR_IOPAEN);
+ stm_rcc_ahb1_clk_disable(1 << STM_RCC_AHB1ENR_IOPAEN);
ao_power_unregister(&ao_power_gpioa);
} else if ((port) == &stm_gpiob) {
ao_power_unregister(&ao_power_gpioa);
} else if ((port) == &stm_gpiob) {
- stm_rcc.ahb1enr &= ~(1 << STM_RCC_AHB1ENR_IOPBEN);
+ stm_rcc_ahb1_clk_disable(1 << STM_RCC_AHB1ENR_IOPBEN);
ao_power_unregister(&ao_power_gpiob);
} else if ((port) == &stm_gpioc) {
ao_power_unregister(&ao_power_gpiob);
} else if ((port) == &stm_gpioc) {
- stm_rcc.ahb1enr &= ~(1 << STM_RCC_AHB1ENR_IOPCEN);
+ stm_rcc_ahb1_clk_disable(1 << STM_RCC_AHB1ENR_IOPCEN);
ao_power_unregister(&ao_power_gpioc);
} else if ((port) == &stm_gpiod) {
ao_power_unregister(&ao_power_gpioc);
} else if ((port) == &stm_gpiod) {
- stm_rcc.ahb1enr &= ~(1 << STM_RCC_AHB1ENR_IOPDEN);
+ stm_rcc_ahb1_clk_disable(1 << STM_RCC_AHB1ENR_IOPDEN);
ao_power_unregister(&ao_power_gpiod);
} else if ((port) == &stm_gpioe) {
ao_power_unregister(&ao_power_gpiod);
} else if ((port) == &stm_gpioe) {
- stm_rcc.ahb1enr &= ~(1 << STM_RCC_AHB1ENR_IOPEEN);
+ stm_rcc_ahb1_clk_disable(1 << STM_RCC_AHB1ENR_IOPEEN);
ao_power_unregister(&ao_power_gpioe);
} else if ((port) == &stm_gpiof) {
ao_power_unregister(&ao_power_gpioe);
} else if ((port) == &stm_gpiof) {
- stm_rcc.ahb1enr &= ~(1 << STM_RCC_AHB1ENR_IOPFEN);
+ stm_rcc_ahb1_clk_disable(1 << STM_RCC_AHB1ENR_IOPFEN);
ao_power_unregister(&ao_power_gpiof);
} else if ((port) == &stm_gpiog) {
ao_power_unregister(&ao_power_gpiof);
} else if ((port) == &stm_gpiog) {
- stm_rcc.ahb1enr &= ~(1 << STM_RCC_AHB1ENR_IOPGEN);
+ stm_rcc_ahb1_clk_disable(1 << STM_RCC_AHB1ENR_IOPGEN);
ao_power_unregister(&ao_power_gpiog);
} else if ((port) == &stm_gpioh) {
ao_power_unregister(&ao_power_gpiog);
} else if ((port) == &stm_gpioh) {
- stm_rcc.ahb1enr &= ~(1 << STM_RCC_AHB1ENR_IOPHEN);
+ stm_rcc_ahb1_clk_disable(1 << STM_RCC_AHB1ENR_IOPHEN);
ao_power_unregister(&ao_power_gpioh);
}
}
ao_power_unregister(&ao_power_gpioh);
}
}
void
ao_usart_init(void);
void
ao_usart_init(void);
+void
+start(void);
+
+char
+ao_serial6_getchar(void);
+
+void
+ao_serial6_putchar(char c);
+
+int
+_ao_serial6_pollchar(void);
+
+uint8_t
+_ao_serial6_sleep_for(uint16_t timeout);
+
+void
+ao_serial6_set_speed(uint32_t speed);
+
+void
+ao_serial6_drain(void);
#endif /* _AO_ARCH_FUNCS_H_ */
#endif /* _AO_ARCH_FUNCS_H_ */
#if DEBUG_THE_CLOCK
/* Output PLL clock on PA8 and SYCLK on PC9 for measurments */
#if DEBUG_THE_CLOCK
/* Output PLL clock on PA8 and SYCLK on PC9 for measurments */
- stm_rcc.ahb1enr |= ((1 << STM_RCC_AHB1ENR_IOPAEN) |
- (1 << STM_RCC_AHB1ENR_IOPCEN));
-
+ ao_enable_port(&stm_gpioa);
stm_afr_set(&stm_gpioa, 8, STM_AFR_AF0);
stm_moder_set(&stm_gpioa, 8, STM_MODER_ALTERNATE);
stm_ospeedr_set(&stm_gpioa, 8, STM_OSPEEDR_HIGH);
stm_afr_set(&stm_gpioa, 8, STM_AFR_AF0);
stm_moder_set(&stm_gpioa, 8, STM_MODER_ALTERNATE);
stm_ospeedr_set(&stm_gpioa, 8, STM_OSPEEDR_HIGH);
+ ao_enable_port(&stm_gpioc);
stm_afr_set(&stm_gpioc, 9, STM_AFR_AF0);
stm_moder_set(&stm_gpioc, 9, STM_MODER_ALTERNATE);
stm_ospeedr_set(&stm_gpioc, 9, STM_OSPEEDR_HIGH);
stm_afr_set(&stm_gpioc, 9, STM_AFR_AF0);
stm_moder_set(&stm_gpioc, 9, STM_MODER_ALTERNATE);
stm_ospeedr_set(&stm_gpioc, 9, STM_OSPEEDR_HIGH);
vuint32_t pad_28;
vuint32_t pad_2c;
vuint32_t pad_28;
vuint32_t pad_2c;
- vuint32_t ahb1enr;
- vuint32_t ahb2enr;
+ vuint32_t _ahb1enr;
+ vuint32_t _ahb2enr;
vuint32_t ahbdnr;
vuint32_t pad_3c;
vuint32_t ahbdnr;
vuint32_t pad_3c;
#define STM_RCC_DCKCFGR2_I2CFMP1SEL_HSI 2
#define STM_RCC_DCKCFGR2_I2CFMP1SEL_APB_ALSO 3
#define STM_RCC_DCKCFGR2_I2CFMP1SEL_HSI 2
#define STM_RCC_DCKCFGR2_I2CFMP1SEL_APB_ALSO 3
+static inline void
+stm_rcc_ahb1_clk_enable(uint32_t bit)
+{
+ stm_rcc._ahb1enr |= bit;
+ uint32_t value = stm_rcc._ahb1enr;
+ (void) value;
+}
+
+static inline void
+stm_rcc_ahb1_clk_disable(uint32_t bit)
+{
+ stm_rcc._ahb1enr &= ~bit;
+ uint32_t value = stm_rcc._ahb1enr;
+ (void) value;
+}
+
+static inline void
+stm_rcc_ahb2_clk_enable(uint32_t bit)
+{
+ stm_rcc._ahb2enr |= bit;
+ uint32_t value = stm_rcc._ahb2enr;
+ (void) value;
+}
+
+static inline void
+stm_rcc_ahb2_clk_disable(uint32_t bit)
+{
+ stm_rcc._ahb2enr &= ~bit;
+ uint32_t value = stm_rcc._ahb2enr;
+ (void) value;
+}
+
struct stm_ictr {
vuint32_t ictr;
};
struct stm_ictr {
vuint32_t ictr;
};
#define isr(name) void stm_ ## name ## _isr(void)
#define isr(name) void stm_ ## name ## _isr(void)
+isr(halt);
+isr(ignore);
isr(nmi);
isr(hardfault);
isr(memmanage);
isr(nmi);
isr(hardfault);
isr(memmanage);