summary |
shortlog |
log |
commit | commitdiff |
tree
raw |
patch |
inline | side by side (from parent 1:
992eee8)
Because the STM32L only offers 16 priority levels, the bottom four
bits of each priority mask are not used. All of the interrupt priority
settings in the system were using values < 16, making them all
effectively the same. Fix that by moving them into the upper 4 bits
and using symbolic constants everywhere.
Signed-off-by: Keith Packard <keithp@keithp.com>
#define AO_TIM91011_CLK (2 * AO_PCLK2)
#endif
#define AO_TIM91011_CLK (2 * AO_PCLK2)
#endif
-#define AO_STM_NVIC_HIGH_PRIORITY 4
-#define AO_STM_NVIC_CLOCK_PRIORITY 6
-#define AO_STM_NVIC_MED_PRIORITY 8
-#define AO_STM_NVIC_LOW_PRIORITY 10
+/* The stm32l implements only 4 bits of the priority fields */
+
+#define AO_STM_NVIC_HIGH_PRIORITY 0x40
+#define AO_STM_NVIC_MED_PRIORITY 0x80
+#define AO_STM_NVIC_LOW_PRIORITY 0xC0
+#define AO_STM_NVIC_CLOCK_PRIORITY 0xf0
void ao_lcd_stm_init(void);
void ao_lcd_stm_init(void);
for (index = 0; index < STM_NUM_DMA; index++) {
stm_nvic_set_enable(STM_ISR_DMA1_CHANNEL1_POS + index);
for (index = 0; index < STM_NUM_DMA; index++) {
stm_nvic_set_enable(STM_ISR_DMA1_CHANNEL1_POS + index);
- stm_nvic_set_priority(STM_ISR_DMA1_CHANNEL1_POS + index, 4);
+ stm_nvic_set_priority(STM_ISR_DMA1_CHANNEL1_POS + index,
+ AO_STM_NVIC_MED_PRIORITY);
ao_dma_allocated[index] = 0;
ao_dma_mutex[index] = 0;
}
ao_dma_allocated[index] = 0;
ao_dma_mutex[index] = 0;
}
(void) gpio;
uint32_t mask = 1 << pin;
(void) gpio;
uint32_t mask = 1 << pin;
if (mode & AO_EXTI_MODE_RISING)
stm_exti.rtsr |= mask;
else
if (mode & AO_EXTI_MODE_RISING)
stm_exti.rtsr |= mask;
else
ao_usart_init(&ao_stm_usart1);
stm_nvic_set_enable(STM_ISR_USART1_POS);
ao_usart_init(&ao_stm_usart1);
stm_nvic_set_enable(STM_ISR_USART1_POS);
- stm_nvic_set_priority(STM_ISR_USART1_POS, 4);
+ stm_nvic_set_priority(STM_ISR_USART1_POS, AO_STM_NVIC_MED_PRIORITY);
#if USE_SERIAL_1_STDIN && !DELAY_SERIAL_1_STDIN
ao_add_stdio(_ao_serial1_pollchar,
ao_serial1_putchar,
#if USE_SERIAL_1_STDIN && !DELAY_SERIAL_1_STDIN
ao_add_stdio(_ao_serial1_pollchar,
ao_serial1_putchar,
#endif
stm_nvic_set_enable(STM_ISR_USART2_POS);
#endif
stm_nvic_set_enable(STM_ISR_USART2_POS);
- stm_nvic_set_priority(STM_ISR_USART2_POS, 4);
+ stm_nvic_set_priority(STM_ISR_USART2_POS, AO_STM_NVIC_MED_PRIORITY);
#if USE_SERIAL_2_STDIN && !DELAY_SERIAL_2_STDIN
ao_add_stdio(_ao_serial2_pollchar,
ao_serial2_putchar,
#if USE_SERIAL_2_STDIN && !DELAY_SERIAL_2_STDIN
ao_add_stdio(_ao_serial2_pollchar,
ao_serial2_putchar,
ao_usart_init(&ao_stm_usart3);
stm_nvic_set_enable(STM_ISR_USART3_POS);
ao_usart_init(&ao_stm_usart3);
stm_nvic_set_enable(STM_ISR_USART3_POS);
- stm_nvic_set_priority(STM_ISR_USART3_POS, 4);
+ stm_nvic_set_priority(STM_ISR_USART3_POS, AO_STM_NVIC_MED_PRIORITY);
#if USE_SERIAL_3_STDIN && !DELAY_SERIAL_3_STDIN
ao_add_stdio(_ao_serial3_pollchar,
ao_serial3_putchar,
#if USE_SERIAL_3_STDIN && !DELAY_SERIAL_3_STDIN
ao_add_stdio(_ao_serial3_pollchar,
ao_serial3_putchar,
stm_systick.csr = ((1 << STM_SYSTICK_CSR_ENABLE) |
(1 << STM_SYSTICK_CSR_TICKINT) |
(STM_SYSTICK_CSR_CLKSOURCE_HCLK_8 << STM_SYSTICK_CSR_CLKSOURCE));
stm_systick.csr = ((1 << STM_SYSTICK_CSR_ENABLE) |
(1 << STM_SYSTICK_CSR_TICKINT) |
(STM_SYSTICK_CSR_CLKSOURCE_HCLK_8 << STM_SYSTICK_CSR_CLKSOURCE));
+ stm_nvic.shpr15_12 |= AO_STM_NVIC_CLOCK_PRIORITY << 24;
ao_arch_block_interrupts();
/* Route interrupts */
ao_arch_block_interrupts();
/* Route interrupts */
- stm_nvic_set_priority(STM_ISR_USB_LP_POS, 3);
+ stm_nvic_set_priority(STM_ISR_USB_LP_POS, AO_STM_NVIC_LOW_PRIORITY);
stm_nvic_set_enable(STM_ISR_USB_LP_POS);
ao_usb_configuration = 0;
stm_nvic_set_enable(STM_ISR_USB_LP_POS);
ao_usb_configuration = 0;