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   1 /*
   2  * Copyright © 2012 Keith Packard <keithp@keithp.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful, but
  10  * WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  12  * General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along
  15  * with this program; if not, write to the Free Software Foundation, Inc.,
  16  * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  17  */
  18
  19 #include "ao.h"
  20
  21 #define NUM_DMA 7
  22
  23 struct ao_dma_config {
  24         void            (*isr)(int index);
  25 };
  26
  27 uint8_t ao_dma_done[NUM_DMA];
  28
  29 static struct ao_dma_config ao_dma_config[NUM_DMA];
  30 static uint8_t ao_dma_allocated[NUM_DMA];
  31 static uint8_t ao_dma_mutex[NUM_DMA];
  32 static uint8_t ao_dma_active;
  33
  34 static void
  35 ao_dma_isr(uint8_t index) {
  36         /* Get channel interrupt bits */
  37         uint32_t        isr = stm_dma.isr & (STM_DMA_ISR_MASK <<
  38                                              STM_DMA_ISR(index));
  39
  40         /* Ack them */
  41         stm_dma.ifcr = isr;
  42         if (ao_dma_config[index].isr)
  43                 (*ao_dma_config[index].isr)(index);
  44         else {
  45                 ao_dma_done[index] = 1;
  46                 ao_wakeup(&ao_dma_done[index]);
  47         }
  48 }
  49
  50 void stm_dma1_channel1_isr(void) { ao_dma_isr(STM_DMA_INDEX(1)); }
  51 void stm_dma1_channel2_isr(void) { ao_dma_isr(STM_DMA_INDEX(2)); }
  52 void stm_dma1_channel3_isr(void) { ao_dma_isr(STM_DMA_INDEX(3)); }
  53 void stm_dma1_channel4_isr(void) { ao_dma_isr(STM_DMA_INDEX(4)); }
  54 void stm_dma1_channel5_isr(void) { ao_dma_isr(STM_DMA_INDEX(5)); }
  55 void stm_dma1_channel6_isr(void) { ao_dma_isr(STM_DMA_INDEX(6)); }
  56 void stm_dma1_channel7_isr(void) { ao_dma_isr(STM_DMA_INDEX(7)); }
  57
  58 void
  59 ao_dma_set_transfer(uint8_t             index,
  60                     volatile void       *peripheral,
  61                     void                *memory,
  62                     uint16_t            count,
  63                     uint32_t            ccr)
  64 {
  65         if (ao_dma_allocated[index]) {
  66                 if (ao_dma_mutex[index])
  67                         ao_panic(AO_PANIC_DMA);
  68                 ao_dma_mutex[index] = 0xff;
  69         } else
  70                 ao_mutex_get(&ao_dma_mutex[index]);
  71         ao_arch_critical(
  72                 if (ao_dma_active++ == 0)
  73                         stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_DMA1EN);
  74                 );
  75         stm_dma.channel[index].ccr = ccr | (1 << STM_DMA_CCR_TCIE);
  76         stm_dma.channel[index].cndtr = count;
  77         stm_dma.channel[index].cpar = peripheral;
  78         stm_dma.channel[index].cmar = memory;
  79         ao_dma_config[index].isr = NULL;
  80 }
  81
  82 void
  83 ao_dma_set_isr(uint8_t index, void (*isr)(int))
  84 {
  85         ao_dma_config[index].isr = isr;
  86 }
  87
  88 void
  89 ao_dma_start(uint8_t index)
  90 {
  91         ao_dma_done[index] = 0;
  92         stm_dma.channel[index].ccr |= (1 << STM_DMA_CCR_EN);
  93 }
  94
  95 void
  96 ao_dma_done_transfer(uint8_t index)
  97 {
  98         stm_dma.channel[index].ccr &= ~(1 << STM_DMA_CCR_EN);
  99         ao_arch_critical(
 100                 if (--ao_dma_active == 0)
 101                         stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_DMA1EN);
 102                 );
 103         if (ao_dma_allocated[index])
 104                 ao_dma_mutex[index] = 0;
 105         else
 106                 ao_mutex_put(&ao_dma_mutex[index]);
 107 }
 108
 109 void
 110 ao_dma_alloc(uint8_t index)
 111 {
 112         if (ao_dma_allocated[index])
 113                 ao_panic(AO_PANIC_DMA);
 114         ao_dma_allocated[index] = 1;
 115 }
 116
 117 #if DEBUG
 118 void
 119 ao_dma_dump_cmd(void)
 120 {
 121         int i;
 122
 123         ao_arch_critical(
 124                 if (ao_dma_active++ == 0)
 125                         stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_DMA1EN);
 126                 );
 127         printf ("isr %08x ifcr%08x\n", stm_dma.isr, stm_dma.ifcr);
 128         for (i = 0; i < NUM_DMA; i++)
 129                 printf("%d: done %d allocated %d mutex %2d ccr %04x cndtr %04x cpar %08x cmar %08x isr %08x\n",
 130                        i,
 131                        ao_dma_done[i],
 132                        ao_dma_allocated[i],
 133                        ao_dma_mutex[i],
 134                        stm_dma.channel[i].ccr,
 135                        stm_dma.channel[i].cndtr,
 136                        stm_dma.channel[i].cpar,
 137                        stm_dma.channel[i].cmar,
 138                        ao_dma_config[i].isr);
 139         ao_arch_critical(
 140                 if (--ao_dma_active == 0)
 141                         stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_DMA1EN);
 142                 );
 143 }
 144
 145 static const struct ao_cmds ao_dma_cmds[] = {
 146         { ao_dma_dump_cmd,      "D\0Dump DMA status" },
 147         { 0, NULL }
 148 };
 149 #endif
 150
 151 void
 152 ao_dma_init(void)
 153 {
 154         int     index;
 155
 156         for (index = 0; index < STM_NUM_DMA; index++) {
 157                 stm_nvic_set_enable(STM_ISR_DMA1_CHANNEL1_POS + index);
 158                 stm_nvic_set_priority(STM_ISR_DMA1_CHANNEL1_POS + index,
 159                                       AO_STM_NVIC_MED_PRIORITY);
 160                 ao_dma_allocated[index] = 0;
 161                 ao_dma_mutex[index] = 0;
 162         }
 163 #if DEBUG
 164         ao_cmd_register(&ao_dma_cmds[0]);
 165 #endif
 166 }