Decrease ADC clock to pclk/4 (12MHz)

ADC isn't supposed to run faster than 14MHz

Signed-off-by: Keith Packard <keithp@keithp.com>

diff --git a/src/stmf0/ao_adc_stm.c b/src/stmf0/ao_adc_stm.c
index 4ba99ad76855005cba92fe909ad3b45cedb6cbca..b276c4876826a1ff744543de78b17eaed18d3628 100644 (file)
--- a/src/stmf0/ao_adc_stm.c
+++ b/src/stmf0/ao_adc_stm.c
@@ -285,7 +285,7 @@ ao_adc_init(void)
                         (1 << STM_ADC_CFGR1_DMAEN));                             /* enable DMA */
 
        /* Set the clock */
-       stm_adc.cfgr2 = STM_ADC_CFGR2_CKMODE_PCLK_2 << STM_ADC_CFGR2_CKMODE;
+       stm_adc.cfgr2 = STM_ADC_CFGR2_CKMODE_PCLK_4 << STM_ADC_CFGR2_CKMODE;
 
        /* Shortest sample time */
        stm_adc.smpr = STM_ADC_SMPR_SMP_239_5 << STM_ADC_SMPR_SMP;