first cut at turnon scripts for EasyTimer v2

[fw/altos] / src / stm / ao_timer.c

diff --git a/src/stm/ao_timer.c b/src/stm/ao_timer.c
index 5cf1e4a87dd37ab88be0c562e38ff1b78f699384..481b81ef1142b244500f544bc46975594fddc091 100644 (file)
--- a/src/stm/ao_timer.c
+++ b/src/stm/ao_timer.c
@@ -3,7 +3,8 @@
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful, but
  * WITHOUT ANY WARRANTY; without even the implied warranty of
@@ -17,11 +18,16 @@
 
 #include "ao.h"
 #include <ao_task.h>
+#if HAS_FAKE_FLIGHT
+#include <ao_fake_flight.h>
+#endif
 
 #ifndef HAS_TICK
 #define HAS_TICK 1
 #endif
 
+#if HAS_TICK || defined(AO_TIMER_HOOK)
+
 #if HAS_TICK
 volatile AO_TICK_TYPE ao_tick_count;
 
@@ -31,27 +37,53 @@ ao_time(void)
        return ao_tick_count;
 }
 
+uint64_t
+ao_time_ns(void)
+{
+       AO_TICK_TYPE    before, after;
+       uint32_t        cvr;
+
+       do {
+               before = ao_tick_count;
+               cvr = stm_systick.cvr;
+               after = ao_tick_count;
+       } while (before != after);
+
+       return (uint64_t) after * (1000000000ULL / AO_HERTZ) +
+               (uint64_t) cvr * (1000000000ULL / AO_SYSTICK);
+}
+
+#endif
+
 #if AO_DATA_ALL
-volatile __data uint8_t        ao_data_interval = 1;
-volatile __data uint8_t        ao_data_count;
+volatile uint8_t       ao_data_interval = 1;
+volatile uint8_t       ao_data_count;
 #endif
 
 void stm_systick_isr(void)
 {
+       ao_validate_cur_stack();
        if (stm_systick.csr & (1 << STM_SYSTICK_CSR_COUNTFLAG)) {
+#if HAS_TICK
                ++ao_tick_count;
-#if HAS_TASK_QUEUE
-               if (ao_task_alarm_tick && (int16_t) (ao_tick_count - ao_task_alarm_tick) >= 0)
-                       ao_task_check_alarm((uint16_t) ao_tick_count);
 #endif
+               ao_task_check_alarm();
 #if AO_DATA_ALL
-               if (++ao_data_count == ao_data_interval) {
+               if (++ao_data_count == ao_data_interval && ao_data_interval) {
                        ao_data_count = 0;
-                       ao_adc_poll();
+#if HAS_FAKE_FLIGHT
+                       if (ao_fake_flight_active)
+                               ao_fake_flight_poll();
+                       else
+#endif
+                               ao_adc_poll();
 #if (AO_DATA_ALL & ~(AO_DATA_ADC))
                        ao_wakeup((void *) &ao_data_count);
 #endif
                }
+#endif
+#ifdef AO_TIMER_HOOK
+               AO_TIMER_HOOK;
 #endif
        }
 }
@@ -77,6 +109,7 @@ ao_timer_init(void)
        stm_systick.csr = ((1 << STM_SYSTICK_CSR_ENABLE) |
                           (1 << STM_SYSTICK_CSR_TICKINT) |
                           (STM_SYSTICK_CSR_CLKSOURCE_HCLK_8 << STM_SYSTICK_CSR_CLKSOURCE));
+       stm_nvic.shpr15_12 |= (uint32_t) AO_STM_NVIC_CLOCK_PRIORITY << 24;
 }
 
 #endif
@@ -90,7 +123,15 @@ ao_clock_init(void)
        /* Switch to MSI while messing about */
        stm_rcc.cr |= (1 << STM_RCC_CR_MSION);
        while (!(stm_rcc.cr & (1 << STM_RCC_CR_MSIRDY)))
-               asm("nop");
+               ao_arch_nop();
+
+       stm_rcc.cfgr = (stm_rcc.cfgr & ~(uint32_t) (STM_RCC_CFGR_SW_MASK << STM_RCC_CFGR_SW)) |
+               (STM_RCC_CFGR_SW_MSI << STM_RCC_CFGR_SW);
+
+       /* wait for system to switch to MSI */
+       while ((stm_rcc.cfgr & (STM_RCC_CFGR_SWS_MASK << STM_RCC_CFGR_SWS)) !=
+              (STM_RCC_CFGR_SWS_MSI << STM_RCC_CFGR_SWS))
+               ao_arch_nop();
 
        /* reset SW, HPRE, PPRE1, PPRE2, MCOSEL and MCOPRE */
        stm_rcc.cfgr &= (uint32_t)0x88FFC00C;
@@ -108,7 +149,7 @@ ao_clock_init(void)
 #if AO_HSE_BYPASS
        stm_rcc.cr |= (1 << STM_RCC_CR_HSEBYP);
 #else
-       stm_rcc.cr &= ~(1 << STM_RCC_CR_HSEBYP);
+       stm_rcc.cr &= ~(uint32_t) (1 << STM_RCC_CR_HSEBYP);
 #endif
        /* Enable HSE clock */
        stm_rcc.cr |= (1 << STM_RCC_CR_HSEON);
@@ -127,7 +168,7 @@ ao_clock_init(void)
 #define STM_RCC_CFGR_PLLSRC_TARGET_CLOCK       (0 << STM_RCC_CFGR_PLLSRC)
 #endif
 
-#if !AO_HSE || HAS_ADC
+#if !AO_HSE || HAS_ADC || HAS_ADC_SINGLE
        /* Enable HSI RC clock 16MHz */
        stm_rcc.cr |= (1 << STM_RCC_CR_HSION);
        while (!(stm_rcc.cr & (1 << STM_RCC_CR_HSIRDY)))
@@ -141,7 +182,6 @@ ao_clock_init(void)
        stm_flash.acr |= (1 << STM_FLASH_ACR_PRFEN);
 
        /* Enable 1 wait state so the CPU can run at 32MHz */
-       /* (haven't managed to run the CPU at 32MHz yet, it's at 16MHz) */
        stm_flash.acr |= (1 << STM_FLASH_ACR_LATENCY);
 
        /* Enable power interface clock */
@@ -185,8 +225,8 @@ ao_clock_init(void)
        stm_rcc.cfgr = cfgr;
 
        /* Disable the PLL */
-       stm_rcc.cr &= ~(1 << STM_RCC_CR_PLLON);
-       while (stm_rcc.cr & (1 << STM_RCC_CR_PLLRDY))
+       stm_rcc.cr &= ~(1UL << STM_RCC_CR_PLLON);
+       while (stm_rcc.cr & (1UL << STM_RCC_CR_PLLRDY))
                asm("nop");
        
        /* PLLVCO to 96MHz (for USB) -> PLLMUL = 6, PLLDIV = 4 */
@@ -198,7 +238,7 @@ ao_clock_init(void)
        cfgr |= (AO_RCC_CFGR_PLLDIV << STM_RCC_CFGR_PLLDIV);
 
        /* PLL source */
-       cfgr &= ~(1 << STM_RCC_CFGR_PLLSRC);
+       cfgr &= ~(1UL << STM_RCC_CFGR_PLLSRC);
        cfgr |= STM_RCC_CFGR_PLLSRC_TARGET_CLOCK;
 
        stm_rcc.cfgr = cfgr;