*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
};
extern struct lpc_ioconf lpc_ioconf;
+#define lpc_ioconf (*(struct lpc_ioconf *) 0x40044000)
#define LPC_IOCONF_FUNC 0
/* PIO0_1 */
#define LPC_IOCONF_FUNC_PIO0_1 0
#define LPC_IOCONF_FUNC_CLKOUT 1
-#define LPC_IOCONF_FUNC_CT32B0_MAT2 2
+#define LPC_IOCONF_FUNC_PIO0_1_CT32B0_MAT2 2
#define LPC_IOCONF_FUNC_USB_FTOGGLE 3
/* PIO0_2 */
#define LPC_IOCONF_FUNC_PIO0_2 0
#define LPC_IOCONF_FUNC_SSEL0 1
-#define LPC_IOCONF_FUNC_CT16B0_CAP0 2
+#define LPC_IOCONF_FUNC_PIO0_2_CT16B0_CAP0 2
/* PIO0_3 */
#define LPC_IOCONF_FUNC_PIO0_3 0
#define LPC_IOCONF_FUNC_USB_VBUS 1
-/* PIO0_4
+/* PIO0_4 */
#define LPC_IOCONF_FUNC_PIO0_4 0
#define LPC_IOCONF_FUNC_I2C_SCL 1
/* PIO0_8 */
#define LPC_IOCONF_FUNC_PIO0_8 0
#define LPC_IOCONF_FUNC_MISO0 1
-#define LPC_IOCONF_FUNC_CT16B0_MAT0 2
+#define LPC_IOCONF_FUNC_PIO0_8_CT16B0_MAT0 2
/* PIO0_9 */
#define LPC_IOCONF_FUNC_PIO0_9 0
#define LPC_IOCONF_FUNC_MOSI0 1
-#define LPC_IOCONF_FUNC_CT16B0_MAT1 2
+#define LPC_IOCONF_FUNC_PIO0_9_CT16B0_MAT1 2
/* PIO0_10 */
#define LPC_IOCONF_FUNC_SWCLK 0
#define LPC_IOCONF_FUNC_PIO0_10 1
#define LPC_IOCONF_FUNC_PIO0_10_SCK0 2
-#define LPC_IOCONF_FUNC_CT16B0_MAT2 3
+#define LPC_IOCONF_FUNC_PIO0_10_CT16B0_MAT2 3
/* PIO0_11 */
#define LPC_IOCONF_FUNC_TDI 0
#define LPC_IOCONF_FUNC_PIO0_11 1
#define LPC_IOCONF_FUNC_AD0 2
-#define LPC_IOCONF_FUNC_CT32B0_MAT3 3
+#define LPC_IOCONF_FUNC_PIO0_11_CT32B0_MAT3 3
/* PIO0_12 */
#define LPC_IOCONF_FUNC_TMS 0
#define LPC_IOCONF_FUNC_PIO0_12 1
#define LPC_IOCONF_FUNC_AD1 2
-#define LPC_IOCONF_FUNC_CT32B1_CAP0 3
+#define LPC_IOCONF_FUNC_PIO0_12_CT32B1_CAP0 3
/* PIO0_13 */
#define LPC_IOCONF_FUNC_TD0 0
#define LPC_IOCONF_FUNC_PIO0_13 1
#define LPC_IOCONF_FUNC_AD2 2
-#define LPC_IOCONF_FUNC_CT32B1_MAT0 3
+#define LPC_IOCONF_FUNC_PIO0_13_CT32B1_MAT0 3
/* PIO0_14 */
#define LPC_IOCONF_FUNC_TRST 0
#define LPC_IOCONF_FUNC_SWDIO 0
#define LPC_IOCONF_FUNC_PIO0_15 1
#define LPC_IOCONF_FUNC_AD4 2
-#define LPC_IOCONF_FUNC_CT32B1_MAT2 3
+#define LPC_IOCONF_FUNC_PIO0_15_CT32B1_MAT2 3
/* PIO0_16 */
#define LPC_IOCONF_FUNC_PIO0_16 0
#define LPC_IOCONF_FUNC_AD5 1
-#define LPC_IOCONF_FUNC_CT32B1_MAT3 2
+#define LPC_IOCONF_FUNC_PIO0_16_CT32B1_MAT3 2
/* PIO0_17 */
#define LPC_IOCONF_FUNC_PIO0_17 0
/* PIO0_20 */
#define LPC_IOCONF_FUNC_PIO0_20 0
-#define LPC_IOCONF_FUNC_CT16B1_CAP0 1
+#define LPC_IOCONF_FUNC_PIO0_20_CT16B1_CAP0 1
/* PIO0_21 */
#define LPC_IOCONF_FUNC_PIO0_21 0
-#define LPC_IOCONF_FUNC_CT16B1_MAT0 1
+#define LPC_IOCONF_FUNC_PIO0_21_CT16B1_MAT0 1
#define LPC_IOCONF_FUNC_PIO0_21_MOSI1 2
/* PIO0_22 */
#define LPC_IOCONF_FUNC_PIO0_22 0
#define LPC_IOCONF_FUNC_AD6 1
-#define LPC_IOCONF_FUNC_CT16B1_MAT1 2
+#define LPC_IOCONF_FUNC_PIO0_22_CT16B1_MAT1 2
#define LPC_IOCONF_FUNC_PIO0_22_MISO1 3
/* PIO0_23 */
/* PIO1_0 */
#define LPC_IOCONF_FUNC_PIO1_0 0
-#define LPC_IOCONF_FUNC_CT32B1_MAT1 1
+#define LPC_IOCONF_FUNC_PIO1_0_CT32B1_MAT1 1
/* PIO1_1 */
#define LPC_IOCONF_FUNC_PIO1_1 0
-#define LPC_IOCONF_FUNC_CT32B1_MAT1 1
+#define LPC_IOCONF_FUNC_PIO1_1_CT32B1_MAT1 1
/* PIO1_2 */
#define LPC_IOCONF_FUNC_PIO1_2 0
/* PIO1_5 */
#define LPC_IOCONF_FUNC_PIO1_5 0
-#define LPC_IOCONF_FUNC_CT32B1_CAP1 1
+#define LPC_IOCONF_FUNC_PIO1_5_CT32B1_CAP1 1
/* PIO1_6 */
#define LPC_IOCONF_FUNC_PIO1_6 0
/* PIO1_13 */
#define LPC_IOCONF_FUNC_PIO1_13 0
#define LPC_IOCONF_FUNC_DTR 1
-#define LPC_IOCONF_FUNC_CT16B0_MAT0 2
+#define LPC_IOCONF_FUNC_PIO1_13_CT16B0_MAT0 2
#define LPC_IOCONF_FUNC_PIO1_13_TXD 3
/* PIO1_14 */
#define LPC_IOCONF_FUNC_PIO1_14 0
#define LPC_IOCONF_FUNC_DSR 1
-#define LPC_IOCONF_FUNC_CT16B0_MAT1 2
-#define LPC_IOCONF_FUNC_PIO1_13_RXD 3
+#define LPC_IOCONF_FUNC_PIO1_14_CT16B0_MAT1 2
+#define LPC_IOCONF_FUNC_PIO1_14_RXD 3
/* PIO1_15 */
#define LPC_IOCONF_FUNC_PIO1_15 0
/* PIO1_16 */
#define LPC_IOCONF_FUNC_PIO1_16 0
#define LPC_IOCONF_FUNC_RI 1
-#define LPC_IOCONF_FUNC_CT16B0_CAP0 2
+#define LPC_IOCONF_FUNC_PIO1_16_CT16B0_CAP0 2
/* PIO1_17 */
#define LPC_IOCONF_FUNC_PIO1_17 0
-#define LPC_IOCONF_FUNC_CT16B0_CAP1 1
+#define LPC_IOCONF_FUNC_PIO1_17_CT16B0_CAP1 1
#define LPC_IOCONF_FUNC_PIO1_17_RXD 2
/* PIO1_18 */
#define LPC_IOCONF_FUNC_PIO1_18 0
-#define LPC_IOCONF_FUNC_CT16B1_CAP1 1
+#define LPC_IOCONF_FUNC_PIO1_18_CT16B1_CAP1 1
#define LPC_IOCONF_FUNC_PIO1_18_TXD 2
/* PIO1_19 */
/* PIO1_31 */
#define LPC_IOCONF_FUNC_PIO1_31 0
-#define LPC_IOCONF_FUNC_MASK 0x7
+#define LPC_IOCONF_FUNC_MASK 0x7UL
#define ao_lpc_alternate(func) (((func) << LPC_IOCONF_FUNC) | \
(LPC_IOCONF_MODE_INACTIVE << LPC_IOCONF_MODE) | \
#define LPC_IOCONF_MODE_PULL_DOWN 1
#define LPC_IOCONF_MODE_PULL_UP 2
#define LPC_IOCONF_MODE_REPEATER 3
-#define LPC_IOCONF_MODE_MASK 3
+#define LPC_IOCONF_MODE_MASK 3UL
#define LPC_IOCONF_HYS 5
vuint32_t mainclksel; /* 0x70 */
vuint32_t mainclkuen;
vuint32_t sysahbclkdiv;
- uint32_t r7c;
+ uint32_t r7c;
vuint32_t sysahbclkctrl; /* 0x80 */
uint32_t r84[3];
uint32_t rcc;
uint32_t rd0[4];
-
+
vuint32_t clkoutsel; /* 0xe0 */
vuint32_t clkoutuen;
vuint32_t clkoutdiv;
uint32_t rec;
-
+
uint32_t rf0[4]; /* 0xf0 */
-
+
vuint32_t pioporcap0; /* 0x100 */
vuint32_t pioporcap1;
uint32_t r102[2];
uint32_t r120[4]; /* 0x120 */
uint32_t r130[4]; /* 0x130 */
uint32_t r140[4]; /* 0x140 */
-
+
vuint32_t bodctrl; /* 0x150 */
vuint32_t systckcal;
uint32_t r158[2];
uint32_t r240[12 * 4]; /* 0x240 */
uint32_t r300[15 * 4]; /* 0x300 */
-
+
uint32_t r3f0; /* 0x3f0 */
vuint32_t device_id;
};
extern struct lpc_scb lpc_scb;
+#define lpc_scb (*(struct lpc_scb *) 0x40048000)
+
+#define LPC_SCB_SYSMEMREMAP_MAP 0
+# define LPC_SCB_SYSMEMREMAP_MAP_BOOT_LOADER 0
+# define LPC_SCB_SYSMEMREMAP_MAP_RAM 1
+# define LPC_SCB_SYSMEMREMAP_MAP_FLASH 2
#define LPC_SCB_PRESETCTRL_SSP0_RST_N 0
#define LPC_SCB_PRESETCTRL_I2C_RST_N 1
#define LPC_SCB_SYSPLLCTRL_PSEL_2 1
#define LPC_SCB_SYSPLLCTRL_PSEL_4 2
#define LPC_SCB_SYSPLLCTRL_PSEL_8 3
-#define LPC_SCB_SYSPLLCTRL_PSEL_MASK 3
+#define LPC_SCB_SYSPLLCTRL_PSEL_MASK 3UL
#define LPC_SCB_SYSPLLSTAT_LOCK 0
#define LPC_SCB_USBPLLCTRL_PSEL_2 1
#define LPC_SCB_USBPLLCTRL_PSEL_4 2
#define LPC_SCB_USBPLLCTRL_PSEL_8 3
-#define LPC_SCB_USBPLLCTRL_PSEL_MASK 3
+#define LPC_SCB_USBPLLCTRL_PSEL_MASK 3UL
#define LPC_SCB_USBPLLSTAT_LOCK 0
#define LPC_SCB_SYSOSCCTRL_FREQRANGE_15_25 1
#define LPC_SCB_WDTOSCCTRL_DIVSEL 0
-#define LPC_SCB_WDTOSCCTRL_DIVSEL_MASK 0x1f
+#define LPC_SCB_WDTOSCCTRL_DIVSEL_MASK 0x1fUL
#define LPC_SCB_WDTOSCCTRL_FREQSEL 5
#define LPC_SCB_WDTOSCCTRL_FREQSEL_0_6 1
#define LPC_SCB_WDTOSCCTRL_FREQSEL_1_05 2
#define LPC_SCB_WDTOSCCTRL_FREQSEL_4_2 0x0d
#define LPC_SCB_WDTOSCCTRL_FREQSEL_4_4 0x0e
#define LPC_SCB_WDTOSCCTRL_FREQSEL_4_6 0x0f
-#define LPC_SCB_WDTOSCCTRL_FREQSEL_MASK 0x0f
+#define LPC_SCB_WDTOSCCTRL_FREQSEL_MASK 0x0fUL
#define LPC_SCB_SYSRSTSTAT_POR 0
#define LPC_SCB_SYSRSTSTAT_EXTRST 1
#define LPC_SCB_SYSPLLCLKSEL_SEL 0
#define LPC_SCB_SYSPLLCLKSEL_SEL_IRC 0
#define LPC_SCB_SYSPLLCLKSEL_SEL_SYSOSC 1
-#define LPC_SCB_SYSPLLCLKSEL_SEL_MASK 3
+#define LPC_SCB_SYSPLLCLKSEL_SEL_MASK 3UL
#define LPC_SCB_SYSPLLCLKUEN_ENA 0
#define LPC_SCB_USBPLLCLKSEL_SEL 0
#define LPC_SCB_USBPLLCLKSEL_SEL_IRC 0
#define LPC_SCB_USBPLLCLKSEL_SEL_SYSOSC 1
-#define LPC_SCB_USBPLLCLKSEL_SEL_MASK 3
+#define LPC_SCB_USBPLLCLKSEL_SEL_MASK 3UL
#define LPC_SCB_USBPLLCLKUEN_ENA 0
#define LPC_SCB_MAINCLKSEL_SEL_PLL_INPUT 1
#define LPC_SCB_MAINCLKSEL_SEL_WATCHDOG 2
#define LPC_SCB_MAINCLKSEL_SEL_PLL_OUTPUT 3
-#define LPC_SCB_MAINCLKSEL_SEL_MASK 3
+#define LPC_SCB_MAINCLKSEL_SEL_MASK 3UL
#define LPC_SCB_MAINCLKUEN_ENA 0
};
extern struct lpc_flash lpc_flash;
+#define lpc_flash (*(struct lpc_flash *) 0x4003c000)
struct lpc_gpio_pin {
vuint32_t isel; /* 0x00 */
};
extern struct lpc_gpio_pin lpc_gpio_pin;
+#define lpc_gpio_pin (*(struct lpc_gpio_pin *) 0x4004c000)
struct lpc_gpio_group0 {
};
vuint32_t word[0x40]; /* 0x1000 */
uint8_t r1100[0x2000 - 0x1100];
-
+
vuint32_t dir[2]; /* 0x2000 */
uint8_t r2008[0x2080 - 0x2008];
};
extern struct lpc_gpio lpc_gpio;
+#define lpc_gpio (*(struct lpc_gpio *) 0x50000000)
struct lpc_systick {
uint8_t r0000[0x10]; /* 0x0000 */
};
extern struct lpc_systick lpc_systick;
+#define lpc_systick (*(struct lpc_systick *) 0xe000e000)
#define LPC_SYSTICK_CSR_ENABLE 0
#define LPC_SYSTICK_CSR_TICKINT 1
};
extern struct lpc_usart lpc_usart;
+#define lpc_usart (*(struct lpc_usart *) 0x40008000)
#define LPC_USART_IER_RBRINTEN 0
#define LPC_USART_IER_THREINTEN 1
#define LPC_USART_IIR_INTID_CTI 6
#define LPC_USART_IIR_INTID_THRE 1
#define LPC_USART_IIR_INTID_MS 0
-#define LPC_USART_IIR_INTID_MASK 7
+#define LPC_USART_IIR_INTID_MASK 7UL
#define LPC_USART_IIR_FIFOEN 6
#define LPC_USART_IIR_ABEOINT 8
#define LPC_USART_IIR_ABTOINT 9
#define LPC_USART_LCR_WLS_6 1
#define LPC_USART_LCR_WLS_7 2
#define LPC_USART_LCR_WLS_8 3
-#define LPC_USART_LCR_WLS_MASK 3
+#define LPC_USART_LCR_WLS_MASK 3UL
#define LPC_USART_LCR_SBS 2
#define LPC_USART_LCR_SBS_1 0
#define LPC_USART_LCR_SBS_2 1
-#define LPC_USART_LCR_SBS_MASK 1
+#define LPC_USART_LCR_SBS_MASK 1UL
#define LPC_USART_LCR_PE 3
#define LPC_USART_LCR_PS 4
#define LPC_USART_LCR_PS_ODD 0
#define LPC_USART_LCR_PS_EVEN 1
#define LPC_USART_LCR_PS_ONE 2
#define LPC_USART_LCR_PS_ZERO 3
-#define LPC_USART_LCR_PS_MASK 3
+#define LPC_USART_LCR_PS_MASK 3UL
#define LPC_USART_LCR_BC 6
#define LPC_USART_LCR_DLAB 7
vuint32_t introuting;
uint32_t r30;
vuint32_t eptoggle;
-} lpc_usb;
+};
extern struct lpc_usb lpc_usb;
+#define lpc_usb (*(struct lpc_usb *) 0x40080000)
#define LPC_USB_DEVCMDSTAT_DEV_ADDR 0
-#define LPC_USB_DEVCMDSTAT_DEV_ADDR_MASK 0x7f
+#define LPC_USB_DEVCMDSTAT_DEV_ADDR_MASK 0x7fUL
#define LPC_USB_DEVCMDSTAT_DEV_EN 7
#define LPC_USB_DEVCMDSTAT_SETUP 8
#define LPC_USB_DEVCMDSTAT_PLL_ON 9
#define LPC_USB_DEVCMDSTAT_VBUSDEBOUNCED 28
#define LPC_USB_INFO_FRAME_NR 0
-#define LPC_USB_INFO_FRAME_NR_MASK 0x3ff
+#define LPC_USB_INFO_FRAME_NR_MASK 0x3ffUL
#define LPC_USB_INFO_ERR_CODE 11
#define LPC_USB_INFO_ERR_CODE_NO_ERROR 0
#define LPC_USB_INFO_ERR_CODE_PID_ENCODING_ERROR 1
#define LPC_USB_INFO_ERR_CODE_BITSTUFF_ERROR 0xd
#define LPC_USB_INFO_ERR_CODE_SYNC_ERROR 0xe
#define LPC_USB_INFO_ERR_CODE_WRONG_DATA_TOGGLE 0xf
-#define LPC_USB_INFO_ERR_CODE_MASK 0xf
+#define LPC_USB_INFO_ERR_CODE_MASK 0xfUL
#define LPC_USB_EPLISTSTART_EP_LIST 0
#define LPC_USB_DATABUFSTART_DA_BUF 0
#define LPC_USB_LPM_HIRD_HW 0
-#define LPC_USB_LPM_HIRD_HW_MASK 0xf
+#define LPC_USB_LPM_HIRD_HW_MASK 0xfUL
#define LPC_USB_LPM_HIRD_SW 4
-#define LPC_USB_LPM_HIRD_SW_MASK 0xf
+#define LPC_USB_LPM_HIRD_SW_MASK 0xfUL
#define LPC_USB_LPM_DATA_PENDING 8
#define LPC_USB_EPSKIP_SKIP 0
vuint32_t reserved_0c;
struct lpc_usb_epn epn[4];
};
+#define lpc_usb_endpoint (*(struct lpc_usb_endpoint *) 0x20004700)
/* Assigned in registers.ld to point at the base
* of USB ram
*/
extern uint8_t lpc_usb_sram[];
+#define lpc_usb_sram ((uint8_t*) 0x20004000)
#define LPC_USB_EP_ACTIVE 31
#define LPC_USB_EP_DISABLED 30
#define LPC_USB_EP_RATE_FEEDBACK 27
#define LPC_USB_EP_ENDPOINT_ISO 26
#define LPC_USB_EP_NBYTES 16
-#define LPC_USB_EP_NBYTES_MASK 0x3ff
+#define LPC_USB_EP_NBYTES_MASK 0x3ffUL
#define LPC_USB_EP_OFFSET 0
#define LPC_ISR_PIN_INT0_POS 0
};
extern struct lpc_nvic lpc_nvic;
+#define lpc_nvic (*(struct lpc_nvic *) 0xe000e100)
static inline void
lpc_nvic_set_enable(int irq) {
- lpc_nvic.iser |= (1 << irq);
+ lpc_nvic.iser = (1 << irq);
}
static inline void
lpc_nvic_clear_enable(int irq) {
- lpc_nvic.icer |= (1 << irq);
+ lpc_nvic.icer = (1 << irq);
}
static inline int
return (lpc_nvic.iser >> irq) & 1;
}
-
+
static inline void
lpc_nvic_set_pending(int irq) {
lpc_nvic.ispr = (1 << irq);
#define IRQ_PRIO_REG(irq) ((irq) >> 2)
#define IRQ_PRIO_BIT(irq) (((irq) & 3) << 3)
-#define IRQ_PRIO_MASK(irq) (0xff << IRQ_PRIO_BIT(irq))
+#define IRQ_PRIO_MASK(irq) (0xffUL << IRQ_PRIO_BIT(irq))
static inline void
lpc_nvic_set_priority(int irq, uint8_t prio) {
};
extern struct arm_scb arm_scb;
+#define arm_scb (*(struct arm_scb *) 0xe000ed00)
struct lpc_ssp {
vuint32_t cr0; /* 0x00 */
};
extern struct lpc_ssp lpc_ssp0, lpc_ssp1;
+#define lpc_ssp0 (*(struct lpc_ssp *) 0x40040000)
+#define lpc_ssp1 (*(struct lpc_ssp *) 0x40058000)
#define LPC_NUM_SPI 2
};
extern struct lpc_adc lpc_adc;
+#define lpc_adc (*(struct lpc_adc *) 0x4001c000)
#define LPC_ADC_CR_SEL 0
#define LPC_ADC_CR_CLKDIV 8
#define LPC_ADC_STAT_OVERRUN 8
#define LPC_ADC_STAT_ADINT 16
+struct lpc_ct16b {
+ vuint32_t ir; /* 0x00 */
+ vuint32_t tcr;
+ vuint32_t tc;
+ vuint32_t pr;
+
+ vuint32_t pc; /* 0x10 */
+ vuint32_t mcr;
+ vuint32_t mr[4]; /* 0x18 */
+ vuint32_t ccr; /* 0x28 */
+ vuint32_t cr0;
+
+ vuint32_t cr1_0; /* 0x30 (only for ct16b0 */
+ vuint32_t cr1_1; /* 0x34 (only for ct16b1 */
+ uint32_t r38;
+ vuint32_t emr;
+
+ uint8_t r40[0x70 - 0x40];
+
+ vuint32_t ctcr; /* 0x70 */
+ vuint32_t pwmc;
+};
+
+extern struct lpc_ct16b lpc_ct16b0, lpc_ct16b1;
+#define lpc_ct16b0 (*(struct lpc_ct16b *) 0x4000c000)
+#define lpc_ct16b1 (*(struct lpc_ct16b *) 0x40010000)
+
+#define LPC_CT16B_IR_MR0INT 0
+#define LPC_CT16B_IR_MR1INT 1
+#define LPC_CT16B_IR_MR2INT 2
+#define LPC_CT16B_IR_MR3INT 3
+#define LPC_CT16B_IR_CR0INT 4
+#define LPC_CT16B0_IR_CR1INT 6
+#define LPC_CT16B1_IR_CR1INT 5
+
+#define LPC_CT16B_TCR_CEN 0
+#define LPC_CT16B_TCR_CRST 1
+
+#define LPC_CT16B_MCR_MR0I 0
+#define LPC_CT16B_MCR_MR0R 1
+#define LPC_CT16B_MCR_MR0S 2
+#define LPC_CT16B_MCR_MR1I 3
+#define LPC_CT16B_MCR_MR1R 4
+#define LPC_CT16B_MCR_MR1S 5
+#define LPC_CT16B_MCR_MR2I 6
+#define LPC_CT16B_MCR_MR2R 7
+#define LPC_CT16B_MCR_MR2S 8
+#define LPC_CT16B_MCR_MR3I 9
+#define LPC_CT16B_MCR_MR3R 10
+#define LPC_CT16B_MCR_MR3S 11
+
+#define LPC_CT16B_CCR_CAP0RE 0
+#define LPC_CT16B_CCR_CAP0FE 1
+#define LPC_CT16B_CCR_CAP0I 2
+#define LPC_CT16B0_CCR_CAP1RE 6
+#define LPC_CT16B0_CCR_CAP1FE 7
+#define LPC_CT16B0_CCR_CAP1I 8
+#define LPC_CT16B1_CCR_CAP1RE 3
+#define LPC_CT16B1_CCR_CAP1FE 4
+#define LPC_CT16B1_CCR_CAP1I 5
+
+#define LPC_CT16B_EMR_EM0 0
+#define LPC_CT16B_EMR_EM1 1
+#define LPC_CT16B_EMR_EM2 2
+#define LPC_CT16B_EMR_EM3 3
+#define LPC_CT16B_EMR_EMC0 4
+#define LPC_CT16B_EMR_EMC1 6
+#define LPC_CT16B_EMR_EMC2 8
+#define LPC_CT16B_EMR_EMC3 10
+
+#define LPC_CT16B_EMR_EMC_NOTHING 0
+#define LPC_CT16B_EMR_EMC_CLEAR 1
+#define LPC_CT16B_EMR_EMC_SET 2
+#define LPC_CT16B_EMR_EMC_TOGGLE 3
+
+#define LPC_CT16B_CCR_CTM 0
+#define LPC_CT16B_CCR_CTM_TIMER 0
+#define LPC_CT16B_CCR_CTM_COUNTER_RISING 1
+#define LPC_CT16B_CCR_CTM_COUNTER_FALLING 2
+#define LPC_CT16B_CCR_CTM_COUNTER_BOTH 3
+#define LPC_CT16B_CCR_CIS 2
+#define LPC_CT16B_CCR_CIS_CAP0 0
+#define LPC_CT16B0_CCR_CIS_CAP1 2
+#define LPC_CT16B1_CCR_CIS_CAP1 1
+#define LPC_CT16B_CCR_ENCC 4
+#define LPC_CT16B_CCR_SELCC 5
+#define LPC_CT16B_CCR_SELCC_RISING_CAP0 0
+#define LPC_CT16B_CCR_SELCC_FALLING_CAP0 1
+#define LPC_CT16B0_CCR_SELCC_RISING_CAP1 4
+#define LPC_CT16B0_CCR_SELCC_FALLING_CAP1 5
+#define LPC_CT16B1_CCR_SELCC_RISING_CAP1 2
+#define LPC_CT16B1_CCR_SELCC_FALLING_CAP1 3
+#define LPC_CT16B_CCR_
+
+#define LPC_CT16B_PWMC_PWMEN0 0
+#define LPC_CT16B_PWMC_PWMEN1 1
+#define LPC_CT16B_PWMC_PWMEN2 2
+#define LPC_CT16B_PWMC_PWMEN3 3
+
struct lpc_ct32b {
vuint32_t ir; /* 0x00 */
vuint32_t tcr;
vuint32_t tc;
vuint32_t pr;
-
+
vuint32_t pc; /* 0x10 */
vuint32_t mcr;
vuint32_t mr[4]; /* 0x18 */
vuint32_t ccr; /* 0x28 */
vuint32_t cr0;
-
+
vuint32_t cr1_0; /* 0x30 (only for ct32b0 */
vuint32_t cr1_1; /* 0x34 (only for ct32b1 */
uint32_t r38;
};
extern struct lpc_ct32b lpc_ct32b0, lpc_ct32b1;
+#define lpc_ct32b0 (*(struct lpc_ct32b *) 0x40014000)
+#define lpc_ct32b1 (*(struct lpc_ct32b *) 0x40018000)
#define LPC_CT32B_TCR_CEN 0
#define LPC_CT32B_TCR_CRST 1
#define LPC_CT32B_EMR_EMC_SET 2
#define LPC_CT32B_EMR_EMC_TOGGLE 3
+#define isr_decl(name) \
+ void lpc_ ## name ## _isr(void)
+
+isr_decl(halt);
+isr_decl(ignore);
+
+isr_decl(nmi);
+isr_decl(hardfault);
+isr_decl(memmanage);
+isr_decl(busfault);
+isr_decl(usagefault);
+isr_decl(svc);
+isr_decl(debugmon);
+isr_decl(pendsv);
+isr_decl(systick);
+
+isr_decl(pin_int0); /* IRQ0 */
+isr_decl(pin_int1);
+isr_decl(pin_int2);
+isr_decl(pin_int3);
+isr_decl(pin_int4); /* IRQ4 */
+isr_decl(pin_int5);
+isr_decl(pin_int6);
+isr_decl(pin_int7);
+
+isr_decl(gint0); /* IRQ8 */
+isr_decl(gint1);
+isr_decl(ssp1);
+isr_decl(i2c);
+
+isr_decl(ct16b0); /* IRQ16 */
+isr_decl(ct16b1);
+isr_decl(ct32b0);
+isr_decl(ct32b1);
+isr_decl(ssp0); /* IRQ20 */
+isr_decl(usart);
+isr_decl(usb_irq);
+isr_decl(usb_fiq);
+
+isr_decl(adc); /* IRQ24 */
+isr_decl(wwdt);
+isr_decl(bod);
+isr_decl(flash);
+
+isr_decl(usb_wakeup);
+
#endif /* _LPC_H_ */
projects / fw / altos / blobdiff