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   1 /*
   2  * Copyright © 2015 Keith Packard <keithp@keithp.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; version 2 of the License.
   7  *
   8  * This program is distributed in the hope that it will be useful, but
   9  * WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  11  * General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along
  14  * with this program; if not, write to the Free Software Foundation, Inc.,
  15  * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  16  */
  17
  18 #ifndef _STM32F0_H_
  19 #define _STM32F0_H_
  20
  21 #include <stdint.h>
  22
  23 typedef volatile uint32_t       vuint32_t;
  24 typedef volatile void *         vvoid_t;
  25 typedef volatile uint16_t       vuint16_t;
  26 typedef volatile uint8_t        vuint8_t;
  27
  28 struct stm_gpio {
  29         vuint32_t       moder;
  30         vuint32_t       otyper;
  31         vuint32_t       ospeedr;
  32         vuint32_t       pupdr;
  33
  34         vuint32_t       idr;
  35         vuint32_t       odr;
  36         vuint32_t       bsrr;
  37         vuint32_t       lckr;
  38
  39         vuint32_t       afrl;
  40         vuint32_t       afrh;
  41         vuint32_t       brr;
  42 };
  43
  44 #define STM_MODER_SHIFT(pin)            ((pin) << 1)
  45 #define STM_MODER_MASK                  3
  46 #define STM_MODER_INPUT                 0
  47 #define STM_MODER_OUTPUT                1
  48 #define STM_MODER_ALTERNATE             2
  49 #define STM_MODER_ANALOG                3
  50
  51 static inline void
  52 stm_moder_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
  53         gpio->moder = ((gpio->moder &
  54                         ~(STM_MODER_MASK << STM_MODER_SHIFT(pin))) |
  55                        value << STM_MODER_SHIFT(pin));
  56 }
  57
  58 static inline uint32_t
  59 stm_moder_get(struct stm_gpio *gpio, int pin) {
  60         return (gpio->moder >> STM_MODER_SHIFT(pin)) & STM_MODER_MASK;
  61 }
  62
  63 #define STM_OTYPER_SHIFT(pin)           (pin)
  64 #define STM_OTYPER_MASK                 1
  65 #define STM_OTYPER_PUSH_PULL            0
  66 #define STM_OTYPER_OPEN_DRAIN           1
  67
  68 static inline void
  69 stm_otyper_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
  70         gpio->otyper = ((gpio->otyper &
  71                          ~(STM_OTYPER_MASK << STM_OTYPER_SHIFT(pin))) |
  72                         value << STM_OTYPER_SHIFT(pin));
  73 }
  74
  75 static inline uint32_t
  76 stm_otyper_get(struct stm_gpio *gpio, int pin) {
  77         return (gpio->otyper >> STM_OTYPER_SHIFT(pin)) & STM_OTYPER_MASK;
  78 }
  79
  80 #define STM_OSPEEDR_SHIFT(pin)          ((pin) << 1)
  81 #define STM_OSPEEDR_MASK                3
  82 #define STM_OSPEEDR_LOW                 0       /* 2MHz */
  83 #define STM_OSPEEDR_MEDIUM              1       /* 10MHz */
  84 #define STM_OSPEEDR_HIGH                3       /* 10-50MHz */
  85
  86 static inline void
  87 stm_ospeedr_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
  88         gpio->ospeedr = ((gpio->ospeedr &
  89                         ~(STM_OSPEEDR_MASK << STM_OSPEEDR_SHIFT(pin))) |
  90                        value << STM_OSPEEDR_SHIFT(pin));
  91 }
  92
  93 static inline uint32_t
  94 stm_ospeedr_get(struct stm_gpio *gpio, int pin) {
  95         return (gpio->ospeedr >> STM_OSPEEDR_SHIFT(pin)) & STM_OSPEEDR_MASK;
  96 }
  97
  98 #define STM_PUPDR_SHIFT(pin)            ((pin) << 1)
  99 #define STM_PUPDR_MASK                  3
 100 #define STM_PUPDR_NONE                  0
 101 #define STM_PUPDR_PULL_UP               1
 102 #define STM_PUPDR_PULL_DOWN             2
 103 #define STM_PUPDR_RESERVED              3
 104
 105 static inline void
 106 stm_pupdr_set(struct stm_gpio *gpio, int pin, uint32_t value) {
 107         gpio->pupdr = ((gpio->pupdr &
 108                         ~(STM_PUPDR_MASK << STM_PUPDR_SHIFT(pin))) |
 109                        value << STM_PUPDR_SHIFT(pin));
 110 }
 111
 112 static inline uint32_t
 113 stm_pupdr_get(struct stm_gpio *gpio, int pin) {
 114         return (gpio->pupdr >> STM_PUPDR_SHIFT(pin)) & STM_PUPDR_MASK;
 115 }
 116
 117 #define STM_AFR_SHIFT(pin)              ((pin) << 2)
 118 #define STM_AFR_MASK                    0xf
 119 #define STM_AFR_NONE                    0
 120 #define STM_AFR_AF0                     0x0
 121 #define STM_AFR_AF1                     0x1
 122 #define STM_AFR_AF2                     0x2
 123 #define STM_AFR_AF3                     0x3
 124 #define STM_AFR_AF4                     0x4
 125 #define STM_AFR_AF5                     0x5
 126 #define STM_AFR_AF6                     0x6
 127 #define STM_AFR_AF7                     0x7
 128
 129 static inline void
 130 stm_afr_set(struct stm_gpio *gpio, int pin, uint32_t value) {
 131         /*
 132          * Set alternate pin mode too
 133          */
 134         stm_moder_set(gpio, pin, STM_MODER_ALTERNATE);
 135         if (pin < 8)
 136                 gpio->afrl = ((gpio->afrl &
 137                                ~(STM_AFR_MASK << STM_AFR_SHIFT(pin))) |
 138                               value << STM_AFR_SHIFT(pin));
 139         else {
 140                 pin -= 8;
 141                 gpio->afrh = ((gpio->afrh &
 142                                ~(STM_AFR_MASK << STM_AFR_SHIFT(pin))) |
 143                               value << STM_AFR_SHIFT(pin));
 144         }
 145 }
 146
 147 static inline uint32_t
 148 stm_afr_get(struct stm_gpio *gpio, int pin) {
 149         if (pin < 8)
 150                 return (gpio->afrl >> STM_AFR_SHIFT(pin)) & STM_AFR_MASK;
 151         else {
 152                 pin -= 8;
 153                 return (gpio->afrh >> STM_AFR_SHIFT(pin)) & STM_AFR_MASK;
 154         }
 155 }
 156
 157 static inline void
 158 stm_gpio_set(struct stm_gpio *gpio, int pin, uint8_t value) {
 159         /* Use the bit set/reset register to do this atomically */
 160         gpio->bsrr = ((uint32_t) (value ^ 1) << (pin + 16)) | ((uint32_t) value << pin);
 161 }
 162
 163 static inline uint8_t
 164 stm_gpio_get(struct stm_gpio *gpio, int pin) {
 165         return (gpio->idr >> pin) & 1;
 166 }
 167
 168 static inline uint16_t
 169 stm_gpio_get_all(struct stm_gpio *gpio) {
 170         return gpio->idr;
 171 }
 172
 173 /*
 174  * We can't define these in registers.ld or our fancy
 175  * ao_enable_gpio macro will expand into a huge pile of code
 176  * as the compiler won't do correct constant folding and
 177  * dead-code elimination
 178  */
 179
 180 extern struct stm_gpio stm_gpioa;
 181 extern struct stm_gpio stm_gpiob;
 182 extern struct stm_gpio stm_gpioc;
 183 extern struct stm_gpio stm_gpiof;
 184
 185 #define stm_gpiof  (*((struct stm_gpio *) 0x48001400))
 186 #define stm_gpioc  (*((struct stm_gpio *) 0x48000800))
 187 #define stm_gpiob  (*((struct stm_gpio *) 0x48000400))
 188 #define stm_gpioa  (*((struct stm_gpio *) 0x48000000))
 189
 190 /* Flash interface */
 191
 192 struct stm_flash {
 193         vuint32_t       acr;
 194         vuint32_t       keyr;
 195         vuint32_t       optkeyr;
 196         vuint32_t       sr;
 197
 198         vuint32_t       cr;
 199         vuint32_t       ar;
 200         vuint32_t       unused_0x18;
 201         vuint32_t       obr;
 202
 203         vuint32_t       wrpr;
 204 };
 205
 206 extern struct stm_flash stm_flash;
 207
 208 #define STM_FLASH_ACR_PRFTBS    (5)
 209 #define STM_FLASH_ACR_PRFTBE    (4)
 210 #define STM_FLASH_ACR_LATENCY   (0)
 211 #define  STM_FLASH_ACR_LATENCY_0                0
 212 #define  STM_FLASH_ACR_LATENCY_1                1
 213
 214 #define STM_FLASH_PECR_OBL_LAUNCH       18
 215 #define STM_FLASH_PECR_ERRIE            17
 216 #define STM_FLASH_PECR_EOPIE            16
 217 #define STM_FLASH_PECR_FPRG             10
 218 #define STM_FLASH_PECR_ERASE            9
 219 #define STM_FLASH_PECR_FTDW             8
 220 #define STM_FLASH_PECR_DATA             4
 221 #define STM_FLASH_PECR_PROG             3
 222 #define STM_FLASH_PECR_OPTLOCK          2
 223 #define STM_FLASH_PECR_PRGLOCK          1
 224 #define STM_FLASH_PECR_PELOCK           0
 225
 226 #define STM_FLASH_SR_EOP                5
 227 #define STM_FLASH_SR_WRPRTERR           4
 228 #define STM_FLASH_SR_PGERR              2
 229 #define STM_FLASH_SR_BSY                0
 230
 231 #define STM_FLASH_CR_OBL_LAUNCH         13
 232 #define STM_FLASH_CR_EOPIE              12
 233 #define STM_FLASH_CR_ERRIE              10
 234 #define STM_FLASH_CR_OPTWRE             9
 235 #define STM_FLASH_CR_LOCK               7
 236 #define STM_FLASH_CR_STRT               6
 237 #define STM_FLASH_CR_OPTER              5
 238 #define STM_FLASH_CR_OPTPG              4
 239 #define STM_FLASH_CR_MER                2
 240 #define STM_FLASH_CR_PER                1
 241 #define STM_FLASH_CR_PG                 0
 242
 243 #define STM_FLASH_OBR_DATA1             24
 244 #define STM_FLASH_OBR_DATA0             16
 245 #define STM_FLASH_OBR_BOOT_SEL          15
 246 #define STM_FLASH_OBR_RAM_PARITY_CHECK  14
 247 #define STM_FLASH_OBR_VDDA_MONITOR      13
 248 #define STM_FLASH_OBR_NBOOT1            12
 249 #define STM_FLASH_OBR_NBOOT0            11
 250 #define STM_FLASH_OBR_NRST_STDBY        10
 251 #define STM_FLASH_OBR_NRST_STOP         9
 252 #define STM_FLASH_OBR_WDG_SW            8
 253 #define STM_FLASH_OBR_RDPRT             1
 254 #define  STM_FLASH_OBR_RDPRT_LEVEL0             0
 255 #define  STM_FLASH_OBR_RDPRT_LEVEL1             1
 256 #define  STM_FLASH_OBR_RDPRT_LEVEL2             3
 257 #define STM_FLASH_OBR_OPTERR            0
 258
 259 #define STM_FLASH_KEYR_KEY1     0x45670123
 260 #define STM_FLASH_KEYR_KEY2     0xcdef89ab
 261
 262 struct stm_rcc {
 263         vuint32_t       cr;
 264         vuint32_t       cfgr;
 265         vuint32_t       cir;
 266         vuint32_t       apb2rstr;
 267
 268         vuint32_t       apb1rstr;
 269         vuint32_t       ahbenr;
 270         vuint32_t       apb2enr;
 271         vuint32_t       apb1enr;
 272
 273         vuint32_t       bdcr;
 274         vuint32_t       csr;
 275         vuint32_t       ahbrstr;
 276         vuint32_t       cfgr2;
 277
 278         vuint32_t       cfgr3;
 279         vuint32_t       cr2;
 280 };
 281
 282 extern struct stm_rcc stm_rcc;
 283
 284 /* Nominal high speed internal oscillator frequency is 16MHz */
 285 #define STM_HSI_FREQ            16000000
 286
 287 #define STM_RCC_CR_PLLRDY       (25)
 288 #define STM_RCC_CR_PLLON        (24)
 289 #define STM_RCC_CR_CSSON        (19)
 290 #define STM_RCC_CR_HSEBYP       (18)
 291 #define STM_RCC_CR_HSERDY       (17)
 292 #define STM_RCC_CR_HSEON        (16)
 293 #define STM_RCC_CR_HSICAL       (8)
 294 #define STM_RCC_CR_HSITRIM      (3)
 295 #define STM_RCC_CR_HSIRDY       (1)
 296 #define STM_RCC_CR_HSION        (0)
 297
 298 #define STM_RCC_CFGR_PLL_NODIV  (31)
 299 #define  STM_RCC_CFGR_PLL_NODIV_DIV_1   1
 300 #define  STM_RCC_CFGR_PLL_NODIV_DIV_2   0
 301
 302 #define STM_RCC_CFGR_MCOPRE     (28)
 303 #define  STM_RCC_CFGR_MCOPRE_DIV_1      0
 304 #define  STM_RCC_CFGR_MCOPRE_DIV_2      1
 305 #define  STM_RCC_CFGR_MCOPRE_DIV_4      2
 306 #define  STM_RCC_CFGR_MCOPRE_DIV_8      3
 307 #define  STM_RCC_CFGR_MCOPRE_DIV_16     4
 308 #define  STM_RCC_CFGR_MCOPRE_DIV_32     5
 309 #define  STM_RCC_CFGR_MCOPRE_DIV_64     6
 310 #define  STM_RCC_CFGR_MCOPRE_DIV_128    7
 311 #define  STM_RCC_CFGR_MCOPRE_DIV_MASK   7
 312
 313 #define STM_RCC_CFGR_MCO        (24)
 314 # define STM_RCC_CFGR_MCO_DISABLE       0
 315
 316 #define STM_RCC_CFGR_PLLMUL     (18)
 317 #define  STM_RCC_CFGR_PLLMUL_2          0
 318 #define  STM_RCC_CFGR_PLLMUL_3          1
 319 #define  STM_RCC_CFGR_PLLMUL_4          2
 320 #define  STM_RCC_CFGR_PLLMUL_5          3
 321 #define  STM_RCC_CFGR_PLLMUL_6          4
 322 #define  STM_RCC_CFGR_PLLMUL_7          5
 323 #define  STM_RCC_CFGR_PLLMUL_8          6
 324 #define  STM_RCC_CFGR_PLLMUL_9          7
 325 #define  STM_RCC_CFGR_PLLMUL_10         8
 326 #define  STM_RCC_CFGR_PLLMUL_11         9
 327 #define  STM_RCC_CFGR_PLLMUL_12         10
 328 #define  STM_RCC_CFGR_PLLMUL_13         11
 329 #define  STM_RCC_CFGR_PLLMUL_14         12
 330 #define  STM_RCC_CFGR_PLLMUL_15         13
 331 #define  STM_RCC_CFGR_PLLMUL_16         14
 332 #define  STM_RCC_CFGR_PLLMUL_MASK       0xf
 333
 334 #define STM_RCC_CFGR_PLLXTPRE   (17)
 335
 336 #define STM_RCC_CFGR_PLLSRC     (15)
 337 # define STM_RCC_CFGR_PLLSRC_HSI_DIV_2  0
 338 # define STM_RCC_CFGR_PLLSRC_HSI        1
 339 # define STM_RCC_CFGR_PLLSRC_HSE        2
 340 # define STM_RCC_CFGR_PLLSRC_HSI48      3
 341
 342 #define STM_RCC_CFGR_ADCPRE     (14)
 343
 344 #define STM_RCC_CFGR_PPRE       (8)
 345 #define  STM_RCC_CFGR_PPRE_DIV_1        0
 346 #define  STM_RCC_CFGR_PPRE_DIV_2        4
 347 #define  STM_RCC_CFGR_PPRE_DIV_4        5
 348 #define  STM_RCC_CFGR_PPRE_DIV_8        6
 349 #define  STM_RCC_CFGR_PPRE_DIV_16       7
 350 #define  STM_RCC_CFGR_PPRE_MASK         7
 351
 352 #define STM_RCC_CFGR_HPRE       (4)
 353 #define  STM_RCC_CFGR_HPRE_DIV_1        0
 354 #define  STM_RCC_CFGR_HPRE_DIV_2        8
 355 #define  STM_RCC_CFGR_HPRE_DIV_4        9
 356 #define  STM_RCC_CFGR_HPRE_DIV_8        0xa
 357 #define  STM_RCC_CFGR_HPRE_DIV_16       0xb
 358 #define  STM_RCC_CFGR_HPRE_DIV_64       0xc
 359 #define  STM_RCC_CFGR_HPRE_DIV_128      0xd
 360 #define  STM_RCC_CFGR_HPRE_DIV_256      0xe
 361 #define  STM_RCC_CFGR_HPRE_DIV_512      0xf
 362 #define  STM_RCC_CFGR_HPRE_MASK         0xf
 363
 364 #define STM_RCC_CFGR_SWS        (2)
 365 #define  STM_RCC_CFGR_SWS_HSI           0
 366 #define  STM_RCC_CFGR_SWS_HSE           1
 367 #define  STM_RCC_CFGR_SWS_PLL           2
 368 #define  STM_RCC_CFGR_SWS_HSI48         3
 369 #define  STM_RCC_CFGR_SWS_MASK          3
 370
 371 #define STM_RCC_CFGR_SW         (0)
 372 #define  STM_RCC_CFGR_SW_HSI            0
 373 #define  STM_RCC_CFGR_SW_HSE            1
 374 #define  STM_RCC_CFGR_SW_PLL            2
 375 #define  STM_RCC_CFGR_SW_HSI48          3
 376 #define  STM_RCC_CFGR_SW_MASK           3
 377
 378 #define STM_RCC_APB2RSTR_DBGMCURST      22
 379 #define STM_RCC_APB2RSTR_TIM17RST       18
 380 #define STM_RCC_APB2RSTR_TIM16RST       17
 381 #define STM_RCC_APB2RSTR_TIM15RST       16
 382 #define STM_RCC_APB2RSTR_USART1RST      14
 383 #define STM_RCC_APB2RSTR_SPI1RST        12
 384 #define STM_RCC_APB2RSTR_TIM1RST        11
 385 #define STM_RCC_APB2RSTR_ADCRST         9
 386 #define STM_RCC_APB2RSTR_USART8RST      7
 387 #define STM_RCC_APB2RSTR_USART7RST      6
 388 #define STM_RCC_APB2RSTR_USART6RST      5
 389 #define STM_RCC_APB2RSTR_SYSCFGRST      1
 390
 391 #define STM_RCC_APB1RSTR_CECRST         30
 392 #define STM_RCC_APB1RSTR_DACRST         29
 393 #define STM_RCC_APB1RSTR_PWRRST         28
 394 #define STM_RCC_APB1RSTR_CRSRST         27
 395 #define STM_RCC_APB1RSTR_CANRST         25
 396 #define STM_RCC_APB1RSTR_USBRST         23
 397 #define STM_RCC_APB1RSTR_I2C2RST        22
 398 #define STM_RCC_APB1RSTR_I1C1RST        21
 399 #define STM_RCC_APB1RSTR_USART5RST      20
 400 #define STM_RCC_APB1RSTR_USART4RST      19
 401 #define STM_RCC_APB1RSTR_USART3RST      18
 402 #define STM_RCC_APB1RSTR_USART2RST      17
 403 #define STM_RCC_APB1RSTR_SPI2RST        14
 404 #define STM_RCC_APB1RSTR_WWDGRST        11
 405 #define STM_RCC_APB1RSTR_TIM14RST       8
 406 #define STM_RCC_APB1RSTR_TIM7RST        5
 407 #define STM_RCC_APB1RSTR_TIM6RST        4
 408 #define STM_RCC_APB1RSTR_TIM3RST        1
 409 #define STM_RCC_APB1RSTR_TIM2RST        0
 410
 411 #define STM_RCC_AHBENR_TSCEN    24
 412 #define STM_RCC_AHBENR_IOPFEN   22
 413 #define STM_RCC_AHBENR_IOPEEN   21
 414 #define STM_RCC_AHBENR_IOPDEN   20
 415 #define STM_RCC_AHBENR_IOPCEN   19
 416 #define STM_RCC_AHBENR_IOPBEN   18
 417 #define STM_RCC_AHBENR_IOPAEN   17
 418 #define STM_RCC_AHBENR_CRCEN    6
 419 #define STM_RCC_AHBENR_FLITFEN  4
 420 #define STM_RCC_AHBENR_SRAMEN   2
 421 #define STM_RCC_AHBENR_DMA2EN   1
 422 #define STM_RCC_AHBENR_DMAEN    0
 423
 424 #define STM_RCC_APB2ENR_DBGMCUEN        22
 425 #define STM_RCC_APB2ENR_TIM17EN         18
 426 #define STM_RCC_APB2ENR_TIM16EN         17
 427 #define STM_RCC_APB2ENR_TIM15EN         16
 428 #define STM_RCC_APB2ENR_USART1EN        14
 429 #define STM_RCC_APB2ENR_SPI1EN          12
 430 #define STM_RCC_APB2ENR_TIM1EN          11
 431 #define STM_RCC_APB2ENR_ADCEN           9
 432 #define STM_RCC_APB2ENR_USART8EN        7
 433 #define STM_RCC_APB2ENR_USART7EN        6
 434 #define STM_RCC_APB2ENR_USART6EN        5
 435 #define STM_RCC_APB2ENR_SYSCFGCOMPEN    0
 436
 437 #define STM_RCC_APB1ENR_CECEN           30
 438 #define STM_RCC_APB1ENR_DACEN           29
 439 #define STM_RCC_APB1ENR_PWREN           28
 440 #define STM_RCC_APB1ENR_CRSEN           27
 441 #define STM_RCC_APB1ENR_CANEN           25
 442 #define STM_RCC_APB1ENR_USBEN           23
 443 #define STM_RCC_APB1ENR_I2C2EN          22
 444 #define STM_RCC_APB1ENR_IC21EN          21
 445 #define STM_RCC_APB1ENR_USART5EN        20
 446 #define STM_RCC_APB1ENR_USART4EN        19
 447 #define STM_RCC_APB1ENR_USART3EN        18
 448 #define STM_RCC_APB1ENR_USART2EN        17
 449 #define STM_RCC_APB1ENR_SPI2EN          14
 450 #define STM_RCC_APB1ENR_WWDGEN          11
 451 #define STM_RCC_APB1ENR_TIM14EN         8
 452 #define STM_RCC_APB1ENR_TIM7EN          5
 453 #define STM_RCC_APB1ENR_TIM6EN          4
 454 #define STM_RCC_APB1ENR_TIM3EN          1
 455 #define STM_RCC_APB1ENR_TIM2EN          0
 456
 457 #define STM_RCC_CSR_LPWRRSTF            (31)
 458 #define STM_RCC_CSR_WWDGRSTF            (30)
 459 #define STM_RCC_CSR_IWDGRSTF            (29)
 460 #define STM_RCC_CSR_SFTRSTF             (28)
 461 #define STM_RCC_CSR_PORRSTF             (27)
 462 #define STM_RCC_CSR_PINRSTF             (26)
 463 #define STM_RCC_CSR_OBLRSTF             (25)
 464 #define STM_RCC_CSR_RMVF                (24)
 465 #define STM_RCC_CSR_V18PWRRSTF          (23)
 466 #define STM_RCC_CSR_LSIRDY              (1)
 467 #define STM_RCC_CSR_LSION               (0)
 468
 469 #define STM_RCC_CR2_HSI48CAL            24
 470 #define STM_RCC_CR2_HSI48RDY            17
 471 #define STM_RCC_CR2_HSI48ON             16
 472 #define STM_RCC_CR2_HSI14CAL            8
 473 #define STM_RCC_CR2_HSI14TRIM           3
 474 #define STM_RCC_CR2_HSI14DIS            2
 475 #define STM_RCC_CR2_HSI14RDY            1
 476 #define STM_RCC_CR2_HSI14ON             0
 477
 478 #define STM_RCC_CFGR2_PREDIV            0
 479 #define  STM_RCC_CFGR2_PREDIV_1                 0x0
 480 #define  STM_RCC_CFGR2_PREDIV_2                 0x1
 481 #define  STM_RCC_CFGR2_PREDIV_3                 0x2
 482 #define  STM_RCC_CFGR2_PREDIV_4                 0x3
 483 #define  STM_RCC_CFGR2_PREDIV_5                 0x4
 484 #define  STM_RCC_CFGR2_PREDIV_6                 0x5
 485 #define  STM_RCC_CFGR2_PREDIV_7                 0x6
 486 #define  STM_RCC_CFGR2_PREDIV_8                 0x7
 487 #define  STM_RCC_CFGR2_PREDIV_9                 0x8
 488 #define  STM_RCC_CFGR2_PREDIV_10                0x9
 489 #define  STM_RCC_CFGR2_PREDIV_11                0xa
 490 #define  STM_RCC_CFGR2_PREDIV_12                0xb
 491 #define  STM_RCC_CFGR2_PREDIV_13                0xc
 492 #define  STM_RCC_CFGR2_PREDIV_14                0xd
 493 #define  STM_RCC_CFGR2_PREDIV_15                0xe
 494 #define  STM_RCC_CFGR2_PREDIV_16                0xf
 495
 496 #define STM_RCC_CFGR3_USART3SW          18
 497 #define STM_RCC_CFGR3_USART2SW          16
 498 #define STM_RCC_CFGR3_ADCSW             8
 499 #define STM_RCC_CFGR3_USBSW             7
 500 #define STM_RCC_CFGR3_CECSW             6
 501 #define STM_RCC_CFGR3_I2C1SW            4
 502 #define STM_RCC_CFGR3_USART1SW          0
 503
 504 struct stm_crs {
 505         vuint32_t       cr;
 506         vuint32_t       cfgr;
 507         vuint32_t       isr;
 508         vuint32_t       icr;
 509 };
 510
 511 extern struct stm_crs stm_crs;
 512
 513 #define STM_CRS_CR_TRIM         8
 514 #define STM_CRS_CR_SWSYNC       7
 515 #define STM_CRS_CR_AUTOTRIMEN   6
 516 #define STM_CRS_CR_CEN          5
 517 #define STM_CRS_CR_ESYNCIE      3
 518 #define STM_CRS_CR_ERRIE        2
 519 #define STM_CRS_CR_SYNCWARNIE   1
 520 #define STM_CRS_CR_SYNCOKIE     0
 521
 522 #define STM_CRS_CFGR_SYNCPOL    31
 523 #define STM_CRS_CFGR_SYNCSRC    28
 524 #define  STM_CRS_CFGR_SYNCSRC_GPIO      0
 525 #define  STM_CRS_CFGR_SYNCSRC_LSE       1
 526 #define  STM_CRS_CFGR_SYNCSRC_USB       2
 527 #define STM_CRS_CFGR_SYNCDIV    24
 528 #define  STM_CRS_CFGR_SYNCDIV_1         0
 529 #define  STM_CRS_CFGR_SYNCDIV_2         1
 530 #define  STM_CRS_CFGR_SYNCDIV_4         2
 531 #define  STM_CRS_CFGR_SYNCDIV_8         3
 532 #define  STM_CRS_CFGR_SYNCDIV_16        4
 533 #define  STM_CRS_CFGR_SYNCDIV_32        5
 534 #define  STM_CRS_CFGR_SYNCDIV_64        6
 535 #define  STM_CRS_CFGR_SYNCDIV_128       7
 536 #define STM_CRS_CFGR_FELIM      16
 537 #define STM_CRS_CFGR_RELOAD     0
 538
 539 #define STM_CRS_ISR_FECAP       16
 540 #define STM_CRS_ISR_FEDIR       15
 541 #define STM_CRS_ISR_TRIMOVF     10
 542 #define STM_CRS_ISR_SYNCMISS    9
 543 #define STM_CRS_ISR_SYNCERR     8
 544 #define STM_CRS_ISR_ESYNCF      3
 545 #define STM_CRS_ISR_ERRF        2
 546 #define STM_CRS_ISR_SYNCWARNF   1
 547 #define STM_CRS_ISR_SYNCOKF     0
 548
 549 #define STM_CRS_ICR_ESYNCC      3
 550 #define STM_CRS_ICR_ERRC        2
 551 #define STM_CRS_ICR_SYNCWARNC   1
 552 #define STM_CRS_ICR_SYNCOKC     0
 553
 554 struct stm_pwr {
 555         vuint32_t       cr;
 556         vuint32_t       csr;
 557 };
 558
 559 extern struct stm_pwr stm_pwr;
 560
 561 #define STM_PWR_CR_DBP          (8)
 562
 563 #define STM_PWR_CR_PLS          (5)
 564 #define  STM_PWR_CR_PLS_2_0     0
 565 #define  STM_PWR_CR_PLS_2_1     1
 566 #define  STM_PWR_CR_PLS_2_2     2
 567 #define  STM_PWR_CR_PLS_2_3     3
 568 #define  STM_PWR_CR_PLS_2_4     4
 569 #define  STM_PWR_CR_PLS_2_5     5
 570 #define  STM_PWR_CR_PLS_2_6     6
 571 #define  STM_PWR_CR_PLS_EXT     7
 572 #define  STM_PWR_CR_PLS_MASK    7
 573
 574 #define STM_PWR_CR_PVDE         (4)
 575 #define STM_PWR_CR_CSBF         (3)
 576 #define STM_PWR_CR_CWUF         (2)
 577 #define STM_PWR_CR_PDDS         (1)
 578 #define STM_PWR_CR_LPSDSR       (0)
 579
 580 #define STM_PWR_CSR_EWUP3       (10)
 581 #define STM_PWR_CSR_EWUP2       (9)
 582 #define STM_PWR_CSR_EWUP1       (8)
 583 #define STM_PWR_CSR_REGLPF      (5)
 584 #define STM_PWR_CSR_VOSF        (4)
 585 #define STM_PWR_CSR_VREFINTRDYF (3)
 586 #define STM_PWR_CSR_PVDO        (2)
 587 #define STM_PWR_CSR_SBF         (1)
 588 #define STM_PWR_CSR_WUF         (0)
 589
 590 struct stm_crc {
 591         union {
 592                 vuint32_t       u32;
 593                 vuint16_t       u16;
 594                 vuint8_t        u8;
 595         }               dr;
 596         vuint32_t       idr;
 597         vuint32_t       cr;
 598         uint32_t        _0c;
 599
 600         vuint32_t       init;
 601         vuint32_t       pol;
 602 };
 603
 604 extern struct stm_crc   stm_crc;
 605
 606 #define stm_crc (*((struct stm_crc *) 0x40023000))
 607
 608 #define STM_CRC_CR_REV_OUT      7
 609 #define STM_CRC_CR_REV_IN       5
 610 #define  STM_CRC_CR_REV_IN_NONE         0
 611 #define  STM_CRC_CR_REV_IN_BY_BYTE      1
 612 #define  STM_CRC_CR_REV_IN_BY_HALF_WORD 2
 613 #define  STM_CRC_CR_REV_IN_BY_WORD      3
 614 #define STM_CRC_CR_POLYSIZE     3
 615 #define  STM_CRC_CR_POLYSIZE_32         0
 616 #define  STM_CRC_CR_POLYSIZE_16         1
 617 #define  STM_CRC_CR_POLYSIZE_8          2
 618 #define  STM_CRC_CR_POLYSIZE_7          3
 619 #define STM_CRC_CR_RESET        0
 620
 621 /* The SYSTICK starts at 0xe000e010 */
 622
 623 struct stm_systick {
 624         vuint32_t       csr;
 625         vuint32_t       rvr;
 626         vuint32_t       cvr;
 627         vuint32_t       calib;
 628 };
 629
 630 extern struct stm_systick stm_systick;
 631
 632 #define STM_SYSTICK_CSR_ENABLE          0
 633 #define STM_SYSTICK_CSR_TICKINT         1
 634 #define STM_SYSTICK_CSR_CLKSOURCE       2
 635 #define  STM_SYSTICK_CSR_CLKSOURCE_EXTERNAL             0
 636 #define  STM_SYSTICK_CSR_CLKSOURCE_HCLK_8               1
 637 #define STM_SYSTICK_CSR_COUNTFLAG       16
 638
 639 /* The NVIC starts at 0xe000e100, so add that to the offsets to find the absolute address */
 640
 641 struct stm_nvic {
 642         vuint32_t       iser;           /* 0x000 0xe000e100 Set Enable Register */
 643
 644         uint8_t         _unused020[0x080 - 0x004];
 645
 646         vuint32_t       icer;           /* 0x080 0xe000e180 Clear Enable Register */
 647
 648         uint8_t         _unused0a0[0x100 - 0x084];
 649
 650         vuint32_t       ispr;           /* 0x100 0xe000e200 Set Pending Register */
 651
 652         uint8_t         _unused120[0x180 - 0x104];
 653
 654         vuint32_t       icpr;           /* 0x180 0xe000e280 Clear Pending Register */
 655
 656         uint8_t         _unused1a0[0x300 - 0x184];
 657
 658         vuint32_t       ipr[8];         /* 0x300 0xe000e400 Priority Register */
 659 };
 660
 661 extern struct stm_nvic stm_nvic;
 662
 663 #define IRQ_MASK(irq)   (1 << (irq))
 664 #define IRQ_BOOL(v,irq) (((v) >> (irq)) & 1)
 665
 666 static inline void
 667 stm_nvic_set_enable(int irq) {
 668         stm_nvic.iser = IRQ_MASK(irq);
 669 }
 670
 671 static inline void
 672 stm_nvic_clear_enable(int irq) {
 673         stm_nvic.icer = IRQ_MASK(irq);
 674 }
 675
 676 static inline int
 677 stm_nvic_enabled(int irq) {
 678         return IRQ_BOOL(stm_nvic.iser, irq);
 679 }
 680
 681 static inline void
 682 stm_nvic_set_pending(int irq) {
 683         stm_nvic.ispr = IRQ_MASK(irq);
 684 }
 685
 686 static inline void
 687 stm_nvic_clear_pending(int irq) {
 688         stm_nvic.icpr = IRQ_MASK(irq);
 689 }
 690
 691 static inline int
 692 stm_nvic_pending(int irq) {
 693         return IRQ_BOOL(stm_nvic.ispr, irq);
 694 }
 695
 696 #define IRQ_PRIO_REG(irq)       ((irq) >> 2)
 697 #define IRQ_PRIO_BIT(irq)       (((irq) & 3) << 3)
 698 #define IRQ_PRIO_MASK(irq)      (0xff << IRQ_PRIO_BIT(irq))
 699
 700 static inline void
 701 stm_nvic_set_priority(int irq, uint8_t prio) {
 702         int             n = IRQ_PRIO_REG(irq);
 703         uint32_t        v;
 704
 705         v = stm_nvic.ipr[n];
 706         v &= ~IRQ_PRIO_MASK(irq);
 707         v |= (prio) << IRQ_PRIO_BIT(irq);
 708         stm_nvic.ipr[n] = v;
 709 }
 710
 711 static inline uint8_t
 712 stm_nvic_get_priority(int irq) {
 713         return (stm_nvic.ipr[IRQ_PRIO_REG(irq)] >> IRQ_PRIO_BIT(irq)) & IRQ_PRIO_MASK(0);
 714 }
 715
 716 struct stm_scb {
 717         vuint32_t       cpuid;
 718         vuint32_t       icsr;
 719         vuint32_t       vtor;
 720         vuint32_t       aircr;
 721
 722         vuint32_t       scr;
 723         vuint32_t       ccr;
 724         vuint32_t       shpr1;
 725         vuint32_t       shpr2;
 726
 727         vuint32_t       shpr3;
 728         vuint32_t       shcrs;
 729         vuint32_t       cfsr;
 730         vuint32_t       hfsr;
 731
 732         uint32_t        unused_30;
 733         vuint32_t       mmfar;
 734         vuint32_t       bfar;
 735 };
 736
 737 extern struct stm_scb stm_scb;
 738
 739 #define STM_SCB_AIRCR_VECTKEY           16
 740 #define  STM_SCB_AIRCR_VECTKEY_KEY              0x05fa
 741 #define STM_SCB_AIRCR_PRIGROUP          8
 742 #define STM_SCB_AIRCR_SYSRESETREQ       2
 743 #define STM_SCB_AIRCR_VECTCLRACTIVE     1
 744 #define STM_SCB_AIRCR_VECTRESET         0
 745
 746 #define isr(name) void stm_ ## name ## _isr(void);
 747
 748 isr(nmi)
 749 isr(hardfault)
 750 isr(memmanage)
 751 isr(busfault)
 752 isr(usagefault)
 753 isr(svc)
 754 isr(debugmon)
 755 isr(pendsv)
 756 isr(systick)
 757 isr(wwdg)
 758 isr(pvd)
 759 isr(tamper_stamp)
 760 isr(rtc_wkup)
 761 isr(flash)
 762 isr(rcc)
 763 isr(exti0)
 764 isr(exti1)
 765 isr(exti2)
 766 isr(exti3)
 767 isr(exti4)
 768 isr(dma1_channel1)
 769 isr(dma1_channel2)
 770 isr(dma1_channel3)
 771 isr(dma1_channel4)
 772 isr(dma1_channel5)
 773 isr(dma1_channel6)
 774 isr(dma1_channel7)
 775 isr(adc1)
 776 isr(usb_hp)
 777 isr(usb_lp)
 778 isr(dac)
 779 isr(comp)
 780 isr(exti9_5)
 781 isr(lcd)
 782 isr(tim9)
 783 isr(tim10)
 784 isr(tim11)
 785 isr(tim2)
 786 isr(tim3)
 787 isr(tim4)
 788 isr(i2c1_ev)
 789 isr(i2c1_er)
 790 isr(i2c2_ev)
 791 isr(i2c2_er)
 792 isr(spi1)
 793 isr(spi2)
 794 isr(usart1)
 795 isr(usart2)
 796 isr(usart3)
 797 isr(exti15_10)
 798 isr(rtc_alarm)
 799 isr(usb_fs_wkup)
 800 isr(tim6)
 801 isr(tim7)
 802
 803 #undef isr
 804
 805 #define STM_ISR_WWDG_POS                0
 806 #define STM_ISR_PVD_VDDIO2_POS          1
 807 #define STM_ISR_RTC_POS                 2
 808 #define STM_ISR_FLASH_POS               3
 809 #define STM_ISR_RCC_CRS_POS             4
 810 #define STM_ISR_EXTI0_1_POS             5
 811 #define STM_ISR_EXTI2_3_POS             6
 812 #define STM_ISR_EXTI4_15_POS            7
 813 #define STM_ISR_TSC_POS                 8
 814 #define STM_ISR_DMA_CH1_POS             9
 815 #define STM_ISR_DMA_CH2_3_DMA2_CH1_2_POS        10
 816 #define STM_ISR_DMA_CH4_5_6_7_DMA2_CH3_4_5_POS  11
 817 #define STM_ISR_ADC_COMP_POS            12
 818 #define STM_ISR_TIM1_BRK_UP_TRG_COM_POS 13
 819 #define STM_ISR_TIM1_CC_POS             14
 820 #define STM_ISR_TIM2_POS                15
 821 #define STM_ISR_TIM3_POS                16
 822 #define STM_ISR_TIM6_DAC_POS            17
 823 #define STM_ISR_TIM7_POS                18
 824 #define STM_ISR_TIM14_POS               19
 825 #define STM_ISR_TIM15_POS               20
 826 #define STM_ISR_TIM16_POS               21
 827 #define STM_ISR_TIM17_POS               22
 828 #define STM_ISR_I2C1_POS                23
 829 #define STM_ISR_I2C2_POS                24
 830 #define STM_ISR_SPI1_POS                25
 831 #define STM_ISR_SPI2_POS                26
 832 #define STM_ISR_USART1_POS              27
 833 #define STM_ISR_USART2_POS              28
 834 #define STM_ISR_UASART3_4_5_6_7_8_POS   29
 835 #define STM_ISR_CEC_CAN_POS             30
 836 #define STM_ISR_USB_POS                 31
 837
 838 struct stm_syscfg {
 839         vuint32_t       cfgr1;
 840         vuint32_t       exticr[4];
 841         vuint32_t       cfgr2;
 842 };
 843
 844 extern struct stm_syscfg stm_syscfg;
 845
 846 #define STM_SYSCFG_CFGR1_TIM3_DMA_RMP   30
 847 #define STM_SYSCFG_CFGR1_TIM2_DMA_RMP   29
 848 #define STM_SYSCFG_CFGR1_TIM1_DMA_RMP   28
 849 #define STM_SYSCFG_CFGR1_I2C1_DMA_RMP   27
 850 #define STM_SYSCFG_CFGR1_USART3_DMA_RMP 26
 851 #define STM_SYSCFG_CFGR1_USART2_DMA_RMP 25
 852 #define STM_SYSCFG_CFGR1_SPI2_DMA_RMP   24
 853 #define STM_SYSCFG_CFGR1_I2C_PA10_FMP   23
 854 #define STM_SYSCFG_CFGR1_I2C_PA9_FMP    22
 855 #define STM_SYSCFG_CFGR1_I2C2_FMP       21
 856 #define STM_SYSCFG_CFGR1_I2C1_FMP       20
 857 #define STM_SYSCFG_CFGR1_I2C_PB9_FMP    19
 858 #define STM_SYSCFG_CFGR1_I2C_PB8_FMP    18
 859 #define STM_SYSCFG_CFGR1_I2C_PB7_FMP    17
 860 #define STM_SYSCFG_CFGR1_I2C_PB6_FMP    16
 861 #define STM_SYSCFG_CFGR1_TIM17_DMA_RMP2 14
 862 #define STM_SYSCFG_CFGR1_TIM16_DMA_RMP2 13
 863 #define STM_SYSCFG_CFGR1_TIM17_DMA_RMP  12
 864 #define STM_SYSCFG_CFGR1_TIM16_DMA_RMP  11
 865 #define STM_SYSCFG_CFGR1_USART1_RX_DMA_RMP      10
 866 #define STM_SYSCFG_CFGR1_USART1_TX_DMA_RMP      9
 867 #define STM_SYSCFG_CFGR1_ADC_DMA_RMP            8
 868 #define STM_SYSCFG_CFGR1_IRDA_ENV_SEL   6
 869 #define  STM_SYSCFG_CFGR1_IRDA_ENV_SEL_TIMER16  0
 870 #define  STM_SYSCFG_CFGR1_IRDA_ENV_SEL_USART1   1
 871 #define  STM_SYSCFG_CFGR1_IRDA_ENV_SEL_USART4   2
 872 #define STM_SYSCFG_CFGR1_PA11_PA12_RMP  4
 873 #define STM_SYSCFG_CFGR1_MEM_MODE       0
 874 #define  STM_SYSCFG_CFGR1_MEM_MODE_MAIN_FLASH   0
 875 #define  STM_SYSCFG_CFGR1_MEM_MODE_SYSTEM_FLASH 1
 876 #define  STM_SYSCFG_CFGR1_MEM_MODE_SRAM         3
 877 #define  STM_SYSCFG_CFGR1_MEM_MODE_MASK         3
 878
 879 #define STM_SYSCFG_EXTICR_PA            0
 880 #define STM_SYSCFG_EXTICR_PB            1
 881 #define STM_SYSCFG_EXTICR_PC            2
 882 #define STM_SYSCFG_EXTICR_PD            3
 883 #define STM_SYSCFG_EXTICR_PE            4
 884 #define STM_SYSCFG_EXTICR_PF            5
 885
 886 static inline void
 887 stm_exticr_set(struct stm_gpio *gpio, int pin) {
 888         uint8_t reg = pin >> 2;
 889         uint8_t shift = (pin & 3) << 2;
 890         uint8_t val = 0;
 891
 892         /* Enable SYSCFG */
 893         stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_SYSCFGCOMPEN);
 894
 895         if (gpio == &stm_gpioa)
 896                 val = STM_SYSCFG_EXTICR_PA;
 897         else if (gpio == &stm_gpiob)
 898                 val = STM_SYSCFG_EXTICR_PB;
 899         else if (gpio == &stm_gpioc)
 900                 val = STM_SYSCFG_EXTICR_PC;
 901         else if (gpio == &stm_gpiof)
 902                 val = STM_SYSCFG_EXTICR_PF;
 903
 904         stm_syscfg.exticr[reg] = (stm_syscfg.exticr[reg] & ~(0xf << shift)) | val << shift;
 905 }
 906
 907 struct stm_dma_channel {
 908         vuint32_t       ccr;
 909         vuint32_t       cndtr;
 910         vvoid_t         cpar;
 911         vvoid_t         cmar;
 912         vuint32_t       reserved;
 913 };
 914
 915 #define STM_NUM_DMA     5
 916
 917 struct stm_dma {
 918         vuint32_t               isr;
 919         vuint32_t               ifcr;
 920         struct stm_dma_channel  channel[STM_NUM_DMA];
 921 };
 922
 923 extern struct stm_dma stm_dma;
 924
 925 /* DMA channels go from 1 to 5, instead of 0 to 4 (sigh)
 926  */
 927
 928 #define STM_DMA_INDEX(channel)          ((channel) - 1)
 929
 930 #define STM_DMA_ISR(index)              ((index) << 2)
 931 #define STM_DMA_ISR_MASK                        0xf
 932 #define STM_DMA_ISR_TEIF                        3
 933 #define STM_DMA_ISR_HTIF                        2
 934 #define STM_DMA_ISR_TCIF                        1
 935 #define STM_DMA_ISR_GIF                         0
 936
 937 #define STM_DMA_IFCR(index)             ((index) << 2)
 938 #define STM_DMA_IFCR_MASK                       0xf
 939 #define STM_DMA_IFCR_CTEIF                      3
 940 #define STM_DMA_IFCR_CHTIF                      2
 941 #define STM_DMA_IFCR_CTCIF                      1
 942 #define STM_DMA_IFCR_CGIF                       0
 943
 944 #define STM_DMA_CCR_MEM2MEM             (14)
 945
 946 #define STM_DMA_CCR_PL                  (12)
 947 #define  STM_DMA_CCR_PL_LOW                     (0)
 948 #define  STM_DMA_CCR_PL_MEDIUM                  (1)
 949 #define  STM_DMA_CCR_PL_HIGH                    (2)
 950 #define  STM_DMA_CCR_PL_VERY_HIGH               (3)
 951 #define  STM_DMA_CCR_PL_MASK                    (3)
 952
 953 #define STM_DMA_CCR_MSIZE               (10)
 954 #define  STM_DMA_CCR_MSIZE_8                    (0)
 955 #define  STM_DMA_CCR_MSIZE_16                   (1)
 956 #define  STM_DMA_CCR_MSIZE_32                   (2)
 957 #define  STM_DMA_CCR_MSIZE_MASK                 (3)
 958
 959 #define STM_DMA_CCR_PSIZE               (8)
 960 #define  STM_DMA_CCR_PSIZE_8                    (0)
 961 #define  STM_DMA_CCR_PSIZE_16                   (1)
 962 #define  STM_DMA_CCR_PSIZE_32                   (2)
 963 #define  STM_DMA_CCR_PSIZE_MASK                 (3)
 964
 965 #define STM_DMA_CCR_MINC                (7)
 966 #define STM_DMA_CCR_PINC                (6)
 967 #define STM_DMA_CCR_CIRC                (5)
 968 #define STM_DMA_CCR_DIR                 (4)
 969 #define  STM_DMA_CCR_DIR_PER_TO_MEM             0
 970 #define  STM_DMA_CCR_DIR_MEM_TO_PER             1
 971 #define STM_DMA_CCR_TEIE                (3)
 972 #define STM_DMA_CCR_HTIE                (2)
 973 #define STM_DMA_CCR_TCIE                (1)
 974 #define STM_DMA_CCR_EN                  (0)
 975
 976 /* DMA channel assignments. When a peripheral has multiple channels
 977  * (indicated with _<number>), then it can be configured to either
 978  * channel using syscfg.cfgr1
 979  */
 980
 981 #define STM_DMA_CHANNEL_ADC_1           1
 982 #define STM_DMA_CHANNEL_ADC_2           2
 983
 984 #define STM_DMA_CHANNEL_SPI1_RX         2
 985 #define STM_DMA_CHANNEL_SPI1_TX         3
 986
 987 #define STM_DMA_CHANNEL_SPI2_RX         4
 988 #define STM_DMA_CHANNEL_SPI2_TX         5
 989
 990 #define STM_DMA_CHANNEL_USART1_TX_1     2
 991 #define STM_DMA_CHANNEL_USART1_RX_1     3
 992 #define STM_DMA_CHANNEL_USART1_TX_2     4
 993 #define STM_DMA_CHANNEL_USART1_RX_2     5
 994
 995 #define STM_DMA_CHANNEL_USART2_RX       4
 996 #define STM_DMA_CHANNEL_USART2_TX       5
 997
 998 #define STM_DMA_CHANNEL_I2C1_TX         2
 999 #define STM_DMA_CHANNEL_I2C1_RX         3
1000
1001 #define STM_DMA_CHANNEL_I2C2_TX         4
1002 #define STM_DMA_CHANNEL_I2C2_RX         5
1003
1004 #define STM_DMA_CHANNEL_TIM1_CH1        2
1005 #define STM_DMA_CHANNEL_TIM1_CH2        3
1006 #define STM_DMA_CHANNEL_TIM1_CH4        4
1007 #define STM_DMA_CHANNEL_TIM1_TRIG       4
1008 #define STM_DMA_CHANNEL_TIM1_COM        4
1009 #define STM_DMA_CHANNEL_TIM1_CH3        5
1010 #define STM_DMA_CHANNEL_TIM1_UP         5
1011
1012 #define STM_DMA_CHANNEL_TIM2_CH3        1
1013 #define STM_DMA_CHANNEL_TIM2_UP         2
1014 #define STM_DMA_CHANNEL_TIM2_CH2        3
1015 #define STM_DMA_CHANNEL_TIM2_CH4        4
1016 #define STM_DMA_CHANNEL_TIM2_CH1        5
1017
1018 #define STM_DMA_CHANNEL_TIM3_CH3        2
1019 #define STM_DMA_CHANNEL_TIM3_CH4        3
1020 #define STM_DMA_CHANNEL_TIM3_UP         3
1021 #define STM_DMA_CHANNEL_TIM3_CH1        4
1022 #define STM_DMA_CHANNEL_TIM3_TRIG       4
1023
1024 #define STM_DMA_CHANNEL_TIM6_UP_DAC     2
1025
1026 #define STM_DMA_CHANNEL_TIM15_CH1       5
1027 #define STM_DMA_CHANNEL_TIM15_UP        5
1028 #define STM_DMA_CHANNEL_TIM15_TRIG      5
1029 #define STM_DMA_CHANNEL_TIM15_COM       5
1030
1031 #define STM_DMA_CHANNEL_TIM16_CH1_1     3
1032 #define STM_DMA_CHANNEL_TIM16_UP_1      3
1033 #define STM_DMA_CHANNEL_TIM16_CH1_2     4
1034 #define STM_DMA_CHANNEL_TIM16_UP_2      4
1035
1036 #define STM_DMA_CHANNEL_TIM17_CH1_1     1
1037 #define STM_DMA_CHANNEL_TIM17_UP_1      1
1038 #define STM_DMA_CHANNEL_TIM17_CH1_2     2
1039 #define STM_DMA_CHANNEL_TIM17_UP_2      2
1040
1041 /*
1042  * Only spi channel 1 and 2 can use DMA
1043  */
1044 #define STM_NUM_SPI     2
1045
1046 struct stm_spi {
1047         vuint32_t       cr1;
1048         vuint32_t       cr2;
1049         vuint32_t       sr;
1050         vuint32_t       dr;
1051         vuint32_t       crcpr;
1052         vuint32_t       rxcrcr;
1053         vuint32_t       txcrcr;
1054 };
1055
1056 extern struct stm_spi stm_spi1, stm_spi2, stm_spi3;
1057
1058 /* SPI channels go from 1 to 3, instead of 0 to 2 (sigh)
1059  */
1060
1061 #define STM_SPI_INDEX(channel)          ((channel) - 1)
1062
1063 #define STM_SPI_CR1_BIDIMODE            15
1064 #define STM_SPI_CR1_BIDIOE              14
1065 #define STM_SPI_CR1_CRCEN               13
1066 #define STM_SPI_CR1_CRCNEXT             12
1067 #define STM_SPI_CR1_CRCL                11
1068 #define STM_SPI_CR1_RXONLY              10
1069 #define STM_SPI_CR1_SSM                 9
1070 #define STM_SPI_CR1_SSI                 8
1071 #define STM_SPI_CR1_LSBFIRST            7
1072 #define STM_SPI_CR1_SPE                 6
1073 #define STM_SPI_CR1_BR                  3
1074 #define  STM_SPI_CR1_BR_PCLK_2                  0
1075 #define  STM_SPI_CR1_BR_PCLK_4                  1
1076 #define  STM_SPI_CR1_BR_PCLK_8                  2
1077 #define  STM_SPI_CR1_BR_PCLK_16                 3
1078 #define  STM_SPI_CR1_BR_PCLK_32                 4
1079 #define  STM_SPI_CR1_BR_PCLK_64                 5
1080 #define  STM_SPI_CR1_BR_PCLK_128                6
1081 #define  STM_SPI_CR1_BR_PCLK_256                7
1082 #define  STM_SPI_CR1_BR_MASK                    7
1083
1084 #define STM_SPI_CR1_MSTR                2
1085 #define STM_SPI_CR1_CPOL                1
1086 #define STM_SPI_CR1_CPHA                0
1087
1088 #define STM_SPI_CR2_LDMA_TX     14
1089 #define STM_SPI_CR2_LDMA_RX     13
1090 #define STM_SPI_CR2_FRXTH       12
1091 #define STM_SPI_CR2_DS          8
1092 #define  STM_SPI_CR2_DS_4               0x3
1093 #define  STM_SPI_CR2_DS_5               0x4
1094 #define  STM_SPI_CR2_DS_6               0x5
1095 #define  STM_SPI_CR2_DS_7               0x6
1096 #define  STM_SPI_CR2_DS_8               0x7
1097 #define  STM_SPI_CR2_DS_9               0x8
1098 #define  STM_SPI_CR2_DS_10              0x9
1099 #define  STM_SPI_CR2_DS_11              0xa
1100 #define  STM_SPI_CR2_DS_12              0xb
1101 #define  STM_SPI_CR2_DS_13              0xc
1102 #define  STM_SPI_CR2_DS_14              0xd
1103 #define  STM_SPI_CR2_DS_15              0xe
1104 #define  STM_SPI_CR2_DS_16              0xf
1105 #define STM_SPI_CR2_TXEIE       7
1106 #define STM_SPI_CR2_RXNEIE      6
1107 #define STM_SPI_CR2_ERRIE       5
1108 #define STM_SPI_CR2_FRF         4
1109 # define STM_SPI_CR2_FRF_MOTOROLA       0
1110 # define STM_SPI_CR2_FRF_TI             1
1111 #define STM_SPI_CR2_NSSP        3
1112 #define STM_SPI_CR2_SSOE        2
1113 #define STM_SPI_CR2_TXDMAEN     1
1114 #define STM_SPI_CR2_RXDMAEN     0
1115
1116 #define STM_SPI_SR_FTLVL        11
1117 #define STM_SPI_SR_FRLVL        9
1118 #define STM_SPI_SR_FRE          8
1119 #define STM_SPI_SR_BSY          7
1120 #define STM_SPI_SR_OVR          6
1121 #define STM_SPI_SR_MODF         5
1122 #define STM_SPI_SR_CRCERR       4
1123 #define STM_SPI_SR_UDR          3
1124 #define STM_SPI_SR_CHSIDE       2
1125 #define STM_SPI_SR_TXE          1
1126 #define STM_SPI_SR_RXNE         0
1127
1128 struct stm_adc {
1129         vuint32_t       isr;
1130         vuint32_t       ier;
1131         vuint32_t       cr;
1132         vuint32_t       cfgr1;
1133
1134         vuint32_t       cfgr2;
1135         vuint32_t       smpr;
1136         vuint32_t       r_18;
1137         vuint32_t       r_1c;
1138
1139         vuint32_t       tr;
1140         vuint32_t       r_24;
1141         vuint32_t       chselr;
1142         vuint32_t       r_2c;
1143
1144         vuint32_t       r_30[4];
1145
1146         vuint32_t       dr;
1147
1148         uint8_t         r_44[0x308 - 0x44];
1149         vuint32_t       ccr;
1150 };
1151
1152 extern struct stm_adc stm_adc;
1153
1154 #define STM_ADC_ISR_AWD         7
1155 #define STM_ADC_ISR_OVR         4
1156 #define STM_ADC_ISR_EOSEQ       3
1157 #define STM_ADC_ISR_EOC         2
1158 #define STM_ADC_ISR_EOSMP       1
1159 #define STM_ADC_ISR_ADRDY       0
1160
1161 #define STM_ADC_IER_AWDIE       7
1162 #define STM_ADC_IER_OVRIE       4
1163 #define STM_ADC_IER_EOSEQIE     3
1164 #define STM_ADC_IER_EOCIE       2
1165 #define STM_ADC_IER_EOSMPIE     1
1166 #define STM_ADC_IER_ADRDYIE     0
1167
1168 #define STM_ADC_CR_ADCAL        31
1169 #define STM_ADC_CR_ADSTP        4
1170 #define STM_ADC_CR_ADSTART      2
1171 #define STM_ADC_CR_ADDIS        1
1172 #define STM_ADC_CR_ADEN         0
1173
1174 #define STM_ADC_CFGR1_AWDCH     26
1175 #define STM_ADC_CFGR1_AWDEN     23
1176 #define STM_ADC_CFGR1_AWDSGL    22
1177 #define STM_ADC_CFGR1_DISCEN    16
1178 #define STM_ADC_CFGR1_AUTOOFF   15
1179 #define STM_ADC_CFGR1_WAIT      14
1180 #define STM_ADC_CFGR1_CONT      13
1181 #define STM_ADC_CFGR1_OVRMOD    12
1182 #define STM_ADC_CFGR1_EXTEN     10
1183 #define  STM_ADC_CFGR1_EXTEN_DISABLE    0
1184 #define  STM_ADC_CFGR1_EXTEN_RISING     1
1185 #define  STM_ADC_CFGR1_EXTEN_FALLING    2
1186 #define  STM_ADC_CFGR1_EXTEN_BOTH       3
1187 #define  STM_ADC_CFGR1_EXTEN_MASK       3
1188
1189 #define STM_ADC_CFGR1_EXTSEL    6
1190 #define STM_ADC_CFGR1_ALIGN     5
1191 #define STM_ADC_CFGR1_RES       3
1192 #define  STM_ADC_CFGR1_RES_12           0
1193 #define  STM_ADC_CFGR1_RES_10           1
1194 #define  STM_ADC_CFGR1_RES_8            2
1195 #define  STM_ADC_CFGR1_RES_6            3
1196 #define  STM_ADC_CFGR1_RES_MASK         3
1197 #define STM_ADC_CFGR1_SCANDIR   2
1198 #define  STM_ADC_CFGR1_SCANDIR_UP       0
1199 #define  STM_ADC_CFGR1_SCANDIR_DOWN     1
1200 #define STM_ADC_CFGR1_DMACFG    1
1201 #define  STM_ADC_CFGR1_DMACFG_ONESHOT   0
1202 #define  STM_ADC_CFGR1_DMACFG_CIRCULAR  1
1203 #define STM_ADC_CFGR1_DMAEN     0
1204
1205 #define STM_ADC_CFGR2_CKMODE    30
1206 #define  STM_ADC_CFGR2_CKMODE_ADCCLK    0
1207 #define  STM_ADC_CFGR2_CKMODE_PCLK_2    1
1208 #define  STM_ADC_CFGR2_CKMODE_PCLK_4    2
1209
1210 #define STM_ADC_SMPR_SMP        0
1211 #define  STM_ADC_SMPR_SMP_1_5           0
1212 #define  STM_ADC_SMPR_SMP_7_5           1
1213 #define  STM_ADC_SMPR_SMP_13_5          2
1214 #define  STM_ADC_SMPR_SMP_28_5          3
1215 #define  STM_ADC_SMPR_SMP_41_5          4
1216 #define  STM_ADC_SMPR_SMP_55_5          5
1217 #define  STM_ADC_SMPR_SMP_71_5          6
1218 #define  STM_ADC_SMPR_SMP_239_5         7
1219
1220 #define STM_ADC_TR_HT           16
1221 #define STM_ADC_TR_LT           0
1222
1223 #define STM_ADC_CCR_VBATEN      24
1224 #define STM_ADC_CCR_TSEN        23
1225 #define STM_ADC_CCR_VREFEN      22
1226
1227 struct stm_cal {
1228         uint16_t        ts_cal_cold;    /* 30°C */
1229         uint16_t        vrefint_cal;
1230         uint16_t        unused_c0;
1231         uint16_t        ts_cal_hot;     /* 110°C */
1232 };
1233
1234 extern struct stm_cal   stm_cal;
1235
1236 #define stm_temp_cal_cold       30
1237 #define stm_temp_cal_hot        110
1238
1239 struct stm_dbgmcu {
1240         uint32_t        idcode;
1241 };
1242
1243 extern struct stm_dbgmcu        stm_dbgmcu;
1244
1245 static inline uint16_t
1246 stm_dev_id(void) {
1247         return stm_dbgmcu.idcode & 0xfff;
1248 }
1249
1250 struct stm_flash_size {
1251         uint16_t        f_size;
1252 };
1253
1254 extern struct stm_flash_size    stm_flash_size_04x;
1255
1256 /* Returns flash size in bytes */
1257 extern uint32_t
1258 stm_flash_size(void);
1259
1260 struct stm_device_id {
1261         uint32_t        u_id0;
1262         uint32_t        u_id1;
1263         uint32_t        u_id2;
1264 };
1265
1266 extern struct stm_device_id     stm_device_id;
1267
1268 #define STM_NUM_I2C     2
1269
1270 #define STM_I2C_INDEX(channel)  ((channel) - 1)
1271
1272 struct stm_i2c {
1273         vuint32_t       cr1;
1274         vuint32_t       cr2;
1275         vuint32_t       oar1;
1276         vuint32_t       oar2;
1277         vuint32_t       dr;
1278         vuint32_t       sr1;
1279         vuint32_t       sr2;
1280         vuint32_t       ccr;
1281         vuint32_t       trise;
1282 };
1283
1284 extern struct stm_i2c stm_i2c1, stm_i2c2;
1285
1286 #define STM_I2C_CR1_SWRST       15
1287 #define STM_I2C_CR1_ALERT       13
1288 #define STM_I2C_CR1_PEC         12
1289 #define STM_I2C_CR1_POS         11
1290 #define STM_I2C_CR1_ACK         10
1291 #define STM_I2C_CR1_STOP        9
1292 #define STM_I2C_CR1_START       8
1293 #define STM_I2C_CR1_NOSTRETCH   7
1294 #define STM_I2C_CR1_ENGC        6
1295 #define STM_I2C_CR1_ENPEC       5
1296 #define STM_I2C_CR1_ENARP       4
1297 #define STM_I2C_CR1_SMBTYPE     3
1298 #define STM_I2C_CR1_SMBUS       1
1299 #define STM_I2C_CR1_PE          0
1300
1301 #define STM_I2C_CR2_LAST        12
1302 #define STM_I2C_CR2_DMAEN       11
1303 #define STM_I2C_CR2_ITBUFEN     10
1304 #define STM_I2C_CR2_ITEVTEN     9
1305 #define STM_I2C_CR2_ITERREN     8
1306 #define STM_I2C_CR2_FREQ        0
1307 #define  STM_I2C_CR2_FREQ_2_MHZ         2
1308 #define  STM_I2C_CR2_FREQ_4_MHZ         4
1309 #define  STM_I2C_CR2_FREQ_8_MHZ         8
1310 #define  STM_I2C_CR2_FREQ_16_MHZ        16
1311 #define  STM_I2C_CR2_FREQ_32_MHZ        32
1312 #define  STM_I2C_CR2_FREQ_MASK          0x3f
1313
1314 #define STM_I2C_SR1_SMBALERT    15
1315 #define STM_I2C_SR1_TIMEOUT     14
1316 #define STM_I2C_SR1_PECERR      12
1317 #define STM_I2C_SR1_OVR         11
1318 #define STM_I2C_SR1_AF          10
1319 #define STM_I2C_SR1_ARLO        9
1320 #define STM_I2C_SR1_BERR        8
1321 #define STM_I2C_SR1_TXE         7
1322 #define STM_I2C_SR1_RXNE        6
1323 #define STM_I2C_SR1_STOPF       4
1324 #define STM_I2C_SR1_ADD10       3
1325 #define STM_I2C_SR1_BTF         2
1326 #define STM_I2C_SR1_ADDR        1
1327 #define STM_I2C_SR1_SB          0
1328
1329 #define STM_I2C_SR2_PEC         8
1330 #define  STM_I2C_SR2_PEC_MASK   0xff00
1331 #define STM_I2C_SR2_DUALF       7
1332 #define STM_I2C_SR2_SMBHOST     6
1333 #define STM_I2C_SR2_SMBDEFAULT  5
1334 #define STM_I2C_SR2_GENCALL     4
1335 #define STM_I2C_SR2_TRA         2
1336 #define STM_I2C_SR2_BUSY        1
1337 #define STM_I2C_SR2_MSL         0
1338
1339 #define STM_I2C_CCR_FS          15
1340 #define STM_I2C_CCR_DUTY        14
1341 #define STM_I2C_CCR_CCR         0
1342 #define  STM_I2C_CCR_MASK       0x7ff
1343
1344 struct stm_tim23 {
1345         vuint32_t       cr1;
1346         vuint32_t       cr2;
1347         vuint32_t       smcr;
1348         vuint32_t       dier;
1349
1350         vuint32_t       sr;
1351         vuint32_t       egr;
1352         vuint32_t       ccmr1;
1353         vuint32_t       ccmr2;
1354
1355         vuint32_t       ccer;
1356         vuint32_t       cnt;
1357         vuint32_t       psc;
1358         vuint32_t       arr;
1359
1360         uint32_t        reserved_30;
1361         vuint32_t       ccr1;
1362         vuint32_t       ccr2;
1363         vuint32_t       ccr3;
1364
1365         vuint32_t       ccr4;
1366         uint32_t        reserved_44;
1367         vuint32_t       dcr;
1368         vuint32_t       dmar;
1369 };
1370
1371 extern struct stm_tim23 stm_tim2, stm_tim3;
1372
1373 #define stm_tim3        (*(struct stm_tim23 *) 0x40000400)
1374 #define stm_tim2        (*(struct stm_tim23 *) 0x40000000)
1375
1376 #define STM_TIM23_CR1_CKD       8
1377 #define  STM_TIM23_CR1_CKD_1            0
1378 #define  STM_TIM23_CR1_CKD_2            1
1379 #define  STM_TIM23_CR1_CKD_4            2
1380 #define  STM_TIM23_CR1_CKD_MASK 3
1381 #define STM_TIM23_CR1_ARPE      7
1382 #define STM_TIM23_CR1_CMS       5
1383 #define  STM_TIM23_CR1_CMS_EDGE         0
1384 #define  STM_TIM23_CR1_CMS_CENTER_1     1
1385 #define  STM_TIM23_CR1_CMS_CENTER_2     2
1386 #define  STM_TIM23_CR1_CMS_CENTER_3     3
1387 #define  STM_TIM23_CR1_CMS_MASK         3
1388 #define STM_TIM23_CR1_DIR       4
1389 #define  STM_TIM23_CR1_DIR_UP           0
1390 #define  STM_TIM23_CR1_DIR_DOWN         1
1391 #define STM_TIM23_CR1_OPM       3
1392 #define STM_TIM23_CR1_URS       2
1393 #define STM_TIM23_CR1_UDIS      1
1394 #define STM_TIM23_CR1_CEN       0
1395
1396 #define STM_TIM23_CR2_TI1S      7
1397 #define STM_TIM23_CR2_MMS       4
1398 #define  STM_TIM23_CR2_MMS_RESET                0
1399 #define  STM_TIM23_CR2_MMS_ENABLE               1
1400 #define  STM_TIM23_CR2_MMS_UPDATE               2
1401 #define  STM_TIM23_CR2_MMS_COMPARE_PULSE        3
1402 #define  STM_TIM23_CR2_MMS_COMPARE_OC1REF       4
1403 #define  STM_TIM23_CR2_MMS_COMPARE_OC2REF       5
1404 #define  STM_TIM23_CR2_MMS_COMPARE_OC3REF       6
1405 #define  STM_TIM23_CR2_MMS_COMPARE_OC4REF       7
1406 #define  STM_TIM23_CR2_MMS_MASK                 7
1407 #define STM_TIM23_CR2_CCDS      3
1408
1409 #define STM_TIM23_SMCR_ETP      15
1410 #define STM_TIM23_SMCR_ECE      14
1411 #define STM_TIM23_SMCR_ETPS     12
1412 #define  STM_TIM23_SMCR_ETPS_OFF                0
1413 #define  STM_TIM23_SMCR_ETPS_DIV_2              1
1414 #define  STM_TIM23_SMCR_ETPS_DIV_4              2
1415 #define  STM_TIM23_SMCR_ETPS_DIV_8              3
1416 #define  STM_TIM23_SMCR_ETPS_MASK               3
1417 #define STM_TIM23_SMCR_ETF      8
1418 #define  STM_TIM23_SMCR_ETF_NONE                0
1419 #define  STM_TIM23_SMCR_ETF_INT_N_2             1
1420 #define  STM_TIM23_SMCR_ETF_INT_N_4             2
1421 #define  STM_TIM23_SMCR_ETF_INT_N_8             3
1422 #define  STM_TIM23_SMCR_ETF_DTS_2_N_6           4
1423 #define  STM_TIM23_SMCR_ETF_DTS_2_N_8           5
1424 #define  STM_TIM23_SMCR_ETF_DTS_4_N_6           6
1425 #define  STM_TIM23_SMCR_ETF_DTS_4_N_8           7
1426 #define  STM_TIM23_SMCR_ETF_DTS_8_N_6           8
1427 #define  STM_TIM23_SMCR_ETF_DTS_8_N_8           9
1428 #define  STM_TIM23_SMCR_ETF_DTS_16_N_5          10
1429 #define  STM_TIM23_SMCR_ETF_DTS_16_N_6          11
1430 #define  STM_TIM23_SMCR_ETF_DTS_16_N_8          12
1431 #define  STM_TIM23_SMCR_ETF_DTS_32_N_5          13
1432 #define  STM_TIM23_SMCR_ETF_DTS_32_N_6          14
1433 #define  STM_TIM23_SMCR_ETF_DTS_32_N_8          15
1434 #define  STM_TIM23_SMCR_ETF_MASK                15
1435 #define STM_TIM23_SMCR_MSM      7
1436 #define STM_TIM23_SMCR_TS       4
1437 #define  STM_TIM23_SMCR_TS_ITR0                 0
1438 #define  STM_TIM23_SMCR_TS_ITR1                 1
1439 #define  STM_TIM23_SMCR_TS_ITR2                 2
1440 #define  STM_TIM23_SMCR_TS_ITR3                 3
1441 #define  STM_TIM23_SMCR_TS_TI1F_ED              4
1442 #define  STM_TIM23_SMCR_TS_TI1FP1               5
1443 #define  STM_TIM23_SMCR_TS_TI2FP2               6
1444 #define  STM_TIM23_SMCR_TS_ETRF                 7
1445 #define  STM_TIM23_SMCR_TS_MASK                 7
1446 #define STM_TIM23_SMCR_OCCS     3
1447 #define STM_TIM23_SMCR_SMS      0
1448 #define  STM_TIM23_SMCR_SMS_DISABLE             0
1449 #define  STM_TIM23_SMCR_SMS_ENCODER_MODE_1      1
1450 #define  STM_TIM23_SMCR_SMS_ENCODER_MODE_2      2
1451 #define  STM_TIM23_SMCR_SMS_ENCODER_MODE_3      3
1452 #define  STM_TIM23_SMCR_SMS_RESET_MODE          4
1453 #define  STM_TIM23_SMCR_SMS_GATED_MODE          5
1454 #define  STM_TIM23_SMCR_SMS_TRIGGER_MODE        6
1455 #define  STM_TIM23_SMCR_SMS_EXTERNAL_CLOCK      7
1456 #define  STM_TIM23_SMCR_SMS_MASK                7
1457
1458 #define STM_TIM23_SR_CC4OF      12
1459 #define STM_TIM23_SR_CC3OF      11
1460 #define STM_TIM23_SR_CC2OF      10
1461 #define STM_TIM23_SR_CC1OF      9
1462 #define STM_TIM23_SR_TIF        6
1463 #define STM_TIM23_SR_CC4IF      4
1464 #define STM_TIM23_SR_CC3IF      3
1465 #define STM_TIM23_SR_CC2IF      2
1466 #define STM_TIM23_SR_CC1IF      1
1467 #define STM_TIM23_SR_UIF        0
1468
1469 #define STM_TIM23_EGR_TG        6
1470 #define STM_TIM23_EGR_CC4G      4
1471 #define STM_TIM23_EGR_CC3G      3
1472 #define STM_TIM23_EGR_CC2G      2
1473 #define STM_TIM23_EGR_CC1G      1
1474 #define STM_TIM23_EGR_UG        0
1475
1476 #define STM_TIM23_CCMR1_OC2CE   15
1477 #define STM_TIM23_CCMR1_OC2M    12
1478 #define  STM_TIM23_CCMR1_OC2M_FROZEN                    0
1479 #define  STM_TIM23_CCMR1_OC2M_SET_HIGH_ON_MATCH         1
1480 #define  STM_TIM23_CCMR1_OC2M_SET_LOW_ON_MATCH          2
1481 #define  STM_TIM23_CCMR1_OC2M_TOGGLE                    3
1482 #define  STM_TIM23_CCMR1_OC2M_FORCE_LOW                 4
1483 #define  STM_TIM23_CCMR1_OC2M_FORCE_HIGH                5
1484 #define  STM_TIM23_CCMR1_OC2M_PWM_MODE_1                6
1485 #define  STM_TIM23_CCMR1_OC2M_PWM_MODE_2                7
1486 #define  STM_TIM23_CCMR1_OC2M_MASK                      7
1487 #define STM_TIM23_CCMR1_OC2PE   11
1488 #define STM_TIM23_CCMR1_OC2FE   10
1489 #define STM_TIM23_CCMR1_CC2S    8
1490 #define  STM_TIM23_CCMR1_CC2S_OUTPUT                    0
1491 #define  STM_TIM23_CCMR1_CC2S_INPUT_TI2                 1
1492 #define  STM_TIM23_CCMR1_CC2S_INPUT_TI1                 2
1493 #define  STM_TIM23_CCMR1_CC2S_INPUT_TRC                 3
1494 #define  STM_TIM23_CCMR1_CC2S_MASK                      3
1495
1496 #define STM_TIM23_CCMR1_OC1CE   7
1497 #define STM_TIM23_CCMR1_OC1M    4
1498 #define  STM_TIM23_CCMR1_OC1M_FROZEN                    0
1499 #define  STM_TIM23_CCMR1_OC1M_SET_HIGH_ON_MATCH         1
1500 #define  STM_TIM23_CCMR1_OC1M_SET_LOW_ON_MATCH          2
1501 #define  STM_TIM23_CCMR1_OC1M_TOGGLE                    3
1502 #define  STM_TIM23_CCMR1_OC1M_FORCE_LOW                 4
1503 #define  STM_TIM23_CCMR1_OC1M_FORCE_HIGH                5
1504 #define  STM_TIM23_CCMR1_OC1M_PWM_MODE_1                6
1505 #define  STM_TIM23_CCMR1_OC1M_PWM_MODE_2                7
1506 #define  STM_TIM23_CCMR1_OC1M_MASK                      7
1507 #define STM_TIM23_CCMR1_OC1PE   11
1508 #define STM_TIM23_CCMR1_OC1FE   2
1509 #define STM_TIM23_CCMR1_CC1S    0
1510 #define  STM_TIM23_CCMR1_CC1S_OUTPUT                    0
1511 #define  STM_TIM23_CCMR1_CC1S_INPUT_TI1                 1
1512 #define  STM_TIM23_CCMR1_CC1S_INPUT_TI2                 2
1513 #define  STM_TIM23_CCMR1_CC1S_INPUT_TRC                 3
1514 #define  STM_TIM23_CCMR1_CC1S_MASK                      3
1515
1516 #define STM_TIM23_CCMR2_OC4CE   15
1517 #define STM_TIM23_CCMR2_OC4M    12
1518 #define  STM_TIM23_CCMR2_OC4M_FROZEN                    0
1519 #define  STM_TIM23_CCMR2_OC4M_SET_HIGH_ON_MATCH 1
1520 #define  STM_TIM23_CCMR2_OC4M_SET_LOW_ON_MATCH          2
1521 #define  STM_TIM23_CCMR2_OC4M_TOGGLE                    3
1522 #define  STM_TIM23_CCMR2_OC4M_FORCE_LOW                 4
1523 #define  STM_TIM23_CCMR2_OC4M_FORCE_HIGH                5
1524 #define  STM_TIM23_CCMR2_OC4M_PWM_MODE_1                6
1525 #define  STM_TIM23_CCMR2_OC4M_PWM_MODE_2                7
1526 #define  STM_TIM23_CCMR2_OC4M_MASK                      7
1527 #define STM_TIM23_CCMR2_OC4PE   11
1528 #define STM_TIM23_CCMR2_OC4FE   10
1529 #define STM_TIM23_CCMR2_CC4S    8
1530 #define  STM_TIM23_CCMR2_CC4S_OUTPUT                    0
1531 #define  STM_TIM23_CCMR2_CC4S_INPUT_TI4                 1
1532 #define  STM_TIM23_CCMR2_CC4S_INPUT_TI3                 2
1533 #define  STM_TIM23_CCMR2_CC4S_INPUT_TRC                 3
1534 #define  STM_TIM23_CCMR2_CC4S_MASK                      3
1535
1536 #define STM_TIM23_CCMR2_OC3CE   7
1537 #define STM_TIM23_CCMR2_OC3M    4
1538 #define  STM_TIM23_CCMR2_OC3M_FROZEN                    0
1539 #define  STM_TIM23_CCMR2_OC3M_SET_HIGH_ON_MATCH         1
1540 #define  STM_TIM23_CCMR2_OC3M_SET_LOW_ON_MATCH          2
1541 #define  STM_TIM23_CCMR2_OC3M_TOGGLE                    3
1542 #define  STM_TIM23_CCMR2_OC3M_FORCE_LOW                 4
1543 #define  STM_TIM23_CCMR2_OC3M_FORCE_HIGH                5
1544 #define  STM_TIM23_CCMR2_OC3M_PWM_MODE_1                6
1545 #define  STM_TIM23_CCMR2_OC3M_PWM_MODE_2                7
1546 #define  STM_TIM23_CCMR2_OC3M_MASK                      7
1547 #define STM_TIM23_CCMR2_OC3PE   11
1548 #define STM_TIM23_CCMR2_OC3FE   2
1549 #define STM_TIM23_CCMR2_CC3S    0
1550 #define  STM_TIM23_CCMR2_CC3S_OUTPUT                    0
1551 #define  STM_TIM23_CCMR2_CC3S_INPUT_TI3                 1
1552 #define  STM_TIM23_CCMR2_CC3S_INPUT_TI4                 2
1553 #define  STM_TIM23_CCMR2_CC3S_INPUT_TRC                 3
1554 #define  STM_TIM23_CCMR2_CC3S_MASK                      3
1555
1556 #define STM_TIM23_CCER_CC4NP    15
1557 #define STM_TIM23_CCER_CC4P     13
1558 #define STM_TIM23_CCER_CC4E     12
1559 #define STM_TIM23_CCER_CC3NP    11
1560 #define STM_TIM23_CCER_CC3P     9
1561 #define STM_TIM23_CCER_CC3E     8
1562 #define STM_TIM23_CCER_CC2NP    7
1563 #define STM_TIM23_CCER_CC2P     5
1564 #define STM_TIM23_CCER_CC2E     4
1565 #define STM_TIM23_CCER_CC1NP    3
1566 #define STM_TIM23_CCER_CC1P     1
1567 #define STM_TIM23_CCER_CC1E     0
1568
1569 struct stm_usb {
1570         struct {
1571                 vuint16_t       r;
1572                 uint16_t        _;
1573         } epr[8];
1574         uint8_t         reserved_20[0x40 - 0x20];
1575         vuint16_t       cntr;
1576         uint16_t        reserved_42;
1577         vuint16_t       istr;
1578         uint16_t        reserved_46;
1579         vuint16_t       fnr;
1580         uint16_t        reserved_4a;
1581         vuint16_t       daddr;
1582         uint16_t        reserved_4e;
1583         vuint16_t       btable;
1584         uint16_t        reserved_52;
1585         vuint16_t       lpmcsr;
1586         uint16_t        reserved_56;
1587         vuint16_t       bcdr;
1588         uint16_t        reserved_5a;
1589 };
1590
1591 extern struct stm_usb stm_usb;
1592
1593 #define STM_USB_EPR_CTR_RX      15
1594 #define  STM_USB_EPR_CTR_RX_WRITE_INVARIANT             1
1595 #define STM_USB_EPR_DTOG_RX     14
1596 #define STM_USB_EPR_DTOG_RX_WRITE_INVARIANT             0
1597 #define STM_USB_EPR_STAT_RX     12
1598 #define  STM_USB_EPR_STAT_RX_DISABLED                   0
1599 #define  STM_USB_EPR_STAT_RX_STALL                      1
1600 #define  STM_USB_EPR_STAT_RX_NAK                        2
1601 #define  STM_USB_EPR_STAT_RX_VALID                      3
1602 #define  STM_USB_EPR_STAT_RX_MASK                       3
1603 #define  STM_USB_EPR_STAT_RX_WRITE_INVARIANT            0
1604 #define STM_USB_EPR_SETUP       11
1605 #define STM_USB_EPR_EP_TYPE     9
1606 #define  STM_USB_EPR_EP_TYPE_BULK                       0
1607 #define  STM_USB_EPR_EP_TYPE_CONTROL                    1
1608 #define  STM_USB_EPR_EP_TYPE_ISO                        2
1609 #define  STM_USB_EPR_EP_TYPE_INTERRUPT                  3
1610 #define  STM_USB_EPR_EP_TYPE_MASK                       3
1611 #define STM_USB_EPR_EP_KIND     8
1612 #define  STM_USB_EPR_EP_KIND_DBL_BUF                    1       /* Bulk */
1613 #define  STM_USB_EPR_EP_KIND_STATUS_OUT                 1       /* Control */
1614 #define STM_USB_EPR_CTR_TX      7
1615 #define  STM_USB_CTR_TX_WRITE_INVARIANT                 1
1616 #define STM_USB_EPR_DTOG_TX     6
1617 #define  STM_USB_EPR_DTOG_TX_WRITE_INVARIANT            0
1618 #define STM_USB_EPR_STAT_TX     4
1619 #define  STM_USB_EPR_STAT_TX_DISABLED                   0
1620 #define  STM_USB_EPR_STAT_TX_STALL                      1
1621 #define  STM_USB_EPR_STAT_TX_NAK                        2
1622 #define  STM_USB_EPR_STAT_TX_VALID                      3
1623 #define  STM_USB_EPR_STAT_TX_WRITE_INVARIANT            0
1624 #define  STM_USB_EPR_STAT_TX_MASK                       3
1625 #define STM_USB_EPR_EA          0
1626 #define  STM_USB_EPR_EA_MASK                            0xf
1627
1628 #define STM_USB_CNTR_CTRM       15
1629 #define STM_USB_CNTR_PMAOVRM    14
1630 #define STM_USB_CNTR_ERRM       13
1631 #define STM_USB_CNTR_WKUPM      12
1632 #define STM_USB_CNTR_SUSPM      11
1633 #define STM_USB_CNTR_RESETM     10
1634 #define STM_USB_CNTR_SOFM       9
1635 #define STM_USB_CNTR_ESOFM      8
1636 #define STM_USB_CNTR_RESUME     4
1637 #define STM_USB_CNTR_FSUSP      3
1638 #define STM_USB_CNTR_LP_MODE    2
1639 #define STM_USB_CNTR_PDWN       1
1640 #define STM_USB_CNTR_FRES       0
1641
1642 #define STM_USB_ISTR_CTR        15
1643 #define STM_USB_ISTR_PMAOVR     14
1644 #define STM_USB_ISTR_ERR        13
1645 #define STM_USB_ISTR_WKUP       12
1646 #define STM_USB_ISTR_SUSP       11
1647 #define STM_USB_ISTR_RESET      10
1648 #define STM_USB_ISTR_SOF        9
1649 #define STM_USB_ISTR_ESOF       8
1650 #define STM_USB_L1REQ           7
1651 #define STM_USB_ISTR_DIR        4
1652 #define STM_USB_ISTR_EP_ID      0
1653 #define  STM_USB_ISTR_EP_ID_MASK                0xf
1654
1655 #define STM_USB_FNR_RXDP        15
1656 #define STM_USB_FNR_RXDM        14
1657 #define STM_USB_FNR_LCK         13
1658 #define STM_USB_FNR_LSOF        11
1659 #define  STM_USB_FNR_LSOF_MASK                  0x3
1660 #define STM_USB_FNR_FN          0
1661 #define  STM_USB_FNR_FN_MASK                    0x7ff
1662
1663 #define STM_USB_DADDR_EF        7
1664 #define STM_USB_DADDR_ADD       0
1665 #define  STM_USB_DADDR_ADD_MASK                 0x7f
1666
1667 #define STM_USB_BCDR_DPPU       15
1668 #define STM_USB_BCDR_PS2DET     7
1669 #define STM_USB_BCDR_SDET       6
1670 #define STM_USB_BCDR_PDET       5
1671 #define STM_USB_BCDR_DCDET      4
1672 #define STM_USB_BCDR_SDEN       3
1673 #define STM_USB_BCDR_PDEN       2
1674 #define STM_USB_BCDR_DCDEN      1
1675 #define STM_USB_BCDR_BCDEN      0
1676
1677 union stm_usb_bdt {
1678         struct {
1679                 vuint16_t       addr_tx;
1680                 vuint16_t       count_tx;
1681                 vuint16_t       addr_rx;
1682                 vuint16_t       count_rx;
1683         } single;
1684         struct {
1685                 vuint16_t       addr;
1686                 vuint16_t       count;
1687         } double_tx[2];
1688         struct {
1689                 vuint16_t       addr;
1690                 vuint16_t       count;
1691         } double_rx[2];
1692 };
1693
1694 #define STM_USB_BDT_COUNT_RX_BL_SIZE    15
1695 #define STM_USB_BDT_COUNT_RX_NUM_BLOCK  10
1696 #define  STM_USB_BDT_COUNT_RX_NUM_BLOCK_MASK    0x1f
1697 #define STM_USB_BDT_COUNT_RX_COUNT_RX   0
1698 #define  STM_USB_BDT_COUNT_RX_COUNT_RX_MASK     0x1ff
1699
1700 #define STM_USB_BDT_SIZE        8
1701
1702 extern uint8_t stm_usb_sram[];
1703
1704 struct stm_exti {
1705         vuint32_t       imr;
1706         vuint32_t       emr;
1707         vuint32_t       rtsr;
1708         vuint32_t       ftsr;
1709
1710         vuint32_t       swier;
1711         vuint32_t       pr;
1712 };
1713
1714 extern struct stm_exti stm_exti;
1715
1716 #endif /* _STM32F0_H_ */