git.gag.com Git - fw/altos/blob - src/stmf0/stm32f0.h

   1 /*
   2  * Copyright © 2015 Keith Packard <keithp@keithp.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful, but
  10  * WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  12  * General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along
  15  * with this program; if not, write to the Free Software Foundation, Inc.,
  16  * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  17  */
  18
  19 #ifndef _STM32F0_H_
  20 #define _STM32F0_H_
  21
  22 #include <stdint.h>
  23
  24 typedef volatile uint32_t       vuint32_t;
  25 typedef volatile void *         vvoid_t;
  26 typedef volatile uint16_t       vuint16_t;
  27 typedef volatile uint8_t        vuint8_t;
  28
  29 struct stm_gpio {
  30         vuint32_t       moder;
  31         vuint32_t       otyper;
  32         vuint32_t       ospeedr;
  33         vuint32_t       pupdr;
  34
  35         vuint32_t       idr;
  36         vuint32_t       odr;
  37         vuint32_t       bsrr;
  38         vuint32_t       lckr;
  39
  40         vuint32_t       afrl;
  41         vuint32_t       afrh;
  42         vuint32_t       brr;
  43 };
  44
  45 #define STM_MODER_SHIFT(pin)            ((pin) << 1)
  46 #define STM_MODER_MASK                  3UL
  47 #define STM_MODER_INPUT                 0
  48 #define STM_MODER_OUTPUT                1
  49 #define STM_MODER_ALTERNATE             2
  50 #define STM_MODER_ANALOG                3
  51
  52 static inline void
  53 stm_moder_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
  54         gpio->moder = ((gpio->moder &
  55                         ~(STM_MODER_MASK << STM_MODER_SHIFT(pin))) |
  56                        value << STM_MODER_SHIFT(pin));
  57 }
  58
  59 static inline uint32_t
  60 stm_moder_get(struct stm_gpio *gpio, int pin) {
  61         return (gpio->moder >> STM_MODER_SHIFT(pin)) & STM_MODER_MASK;
  62 }
  63
  64 #define STM_OTYPER_SHIFT(pin)           (pin)
  65 #define STM_OTYPER_MASK                 1UL
  66 #define STM_OTYPER_PUSH_PULL            0
  67 #define STM_OTYPER_OPEN_DRAIN           1
  68
  69 static inline void
  70 stm_otyper_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
  71         gpio->otyper = ((gpio->otyper &
  72                          ~(STM_OTYPER_MASK << STM_OTYPER_SHIFT(pin))) |
  73                         value << STM_OTYPER_SHIFT(pin));
  74 }
  75
  76 static inline uint32_t
  77 stm_otyper_get(struct stm_gpio *gpio, int pin) {
  78         return (gpio->otyper >> STM_OTYPER_SHIFT(pin)) & STM_OTYPER_MASK;
  79 }
  80
  81 #define STM_OSPEEDR_SHIFT(pin)          ((pin) << 1)
  82 #define STM_OSPEEDR_MASK                3UL
  83 #define STM_OSPEEDR_LOW                 0       /* 2MHz */
  84 #define STM_OSPEEDR_MEDIUM              1       /* 10MHz */
  85 #define STM_OSPEEDR_HIGH                3       /* 10-50MHz */
  86
  87 static inline void
  88 stm_ospeedr_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
  89         gpio->ospeedr = ((gpio->ospeedr &
  90                         ~(STM_OSPEEDR_MASK << STM_OSPEEDR_SHIFT(pin))) |
  91                        value << STM_OSPEEDR_SHIFT(pin));
  92 }
  93
  94 static inline uint32_t
  95 stm_ospeedr_get(struct stm_gpio *gpio, int pin) {
  96         return (gpio->ospeedr >> STM_OSPEEDR_SHIFT(pin)) & STM_OSPEEDR_MASK;
  97 }
  98
  99 #define STM_PUPDR_SHIFT(pin)            ((pin) << 1)
 100 #define STM_PUPDR_MASK                  3UL
 101 #define STM_PUPDR_NONE                  0
 102 #define STM_PUPDR_PULL_UP               1
 103 #define STM_PUPDR_PULL_DOWN             2
 104 #define STM_PUPDR_RESERVED              3
 105
 106 static inline void
 107 stm_pupdr_set(struct stm_gpio *gpio, int pin, uint32_t value) {
 108         gpio->pupdr = ((gpio->pupdr &
 109                         ~(STM_PUPDR_MASK << STM_PUPDR_SHIFT(pin))) |
 110                        value << STM_PUPDR_SHIFT(pin));
 111 }
 112
 113 static inline uint32_t
 114 stm_pupdr_get(struct stm_gpio *gpio, int pin) {
 115         return (gpio->pupdr >> STM_PUPDR_SHIFT(pin)) & STM_PUPDR_MASK;
 116 }
 117
 118 #define STM_AFR_SHIFT(pin)              ((pin) << 2)
 119 #define STM_AFR_MASK                    0xfUL
 120 #define STM_AFR_NONE                    0
 121 #define STM_AFR_AF0                     0x0
 122 #define STM_AFR_AF1                     0x1
 123 #define STM_AFR_AF2                     0x2
 124 #define STM_AFR_AF3                     0x3
 125 #define STM_AFR_AF4                     0x4
 126 #define STM_AFR_AF5                     0x5
 127 #define STM_AFR_AF6                     0x6
 128 #define STM_AFR_AF7                     0x7
 129
 130 static inline void
 131 stm_afr_set(struct stm_gpio *gpio, int pin, uint32_t value) {
 132         /*
 133          * Set alternate pin mode too
 134          */
 135         stm_moder_set(gpio, pin, STM_MODER_ALTERNATE);
 136         if (pin < 8)
 137                 gpio->afrl = ((gpio->afrl &
 138                                ~(STM_AFR_MASK << STM_AFR_SHIFT(pin))) |
 139                               value << STM_AFR_SHIFT(pin));
 140         else {
 141                 pin -= 8;
 142                 gpio->afrh = ((gpio->afrh &
 143                                ~(STM_AFR_MASK << STM_AFR_SHIFT(pin))) |
 144                               value << STM_AFR_SHIFT(pin));
 145         }
 146 }
 147
 148 static inline uint32_t
 149 stm_afr_get(struct stm_gpio *gpio, int pin) {
 150         if (pin < 8)
 151                 return (gpio->afrl >> STM_AFR_SHIFT(pin)) & STM_AFR_MASK;
 152         else {
 153                 pin -= 8;
 154                 return (gpio->afrh >> STM_AFR_SHIFT(pin)) & STM_AFR_MASK;
 155         }
 156 }
 157
 158 static inline void
 159 stm_gpio_set(struct stm_gpio *gpio, int pin, uint8_t value) {
 160         /* Use the bit set/reset register to do this atomically */
 161         gpio->bsrr = ((uint32_t) (value ^ 1) << (pin + 16)) | ((uint32_t) value << pin);
 162 }
 163
 164 static inline uint8_t
 165 stm_gpio_get(struct stm_gpio *gpio, int pin) {
 166         return (gpio->idr >> pin) & 1;
 167 }
 168
 169 static inline uint16_t
 170 stm_gpio_get_all(struct stm_gpio *gpio) {
 171         return (uint16_t) gpio->idr;
 172 }
 173
 174 /*
 175  * We can't define these in registers.ld or our fancy
 176  * ao_enable_gpio macro will expand into a huge pile of code
 177  * as the compiler won't do correct constant folding and
 178  * dead-code elimination
 179  */
 180
 181 extern struct stm_gpio stm_gpioa;
 182 extern struct stm_gpio stm_gpiob;
 183 extern struct stm_gpio stm_gpioc;
 184 extern struct stm_gpio stm_gpiof;
 185
 186 #define stm_gpiof  (*((struct stm_gpio *) 0x48001400))
 187 #define stm_gpioc  (*((struct stm_gpio *) 0x48000800))
 188 #define stm_gpiob  (*((struct stm_gpio *) 0x48000400))
 189 #define stm_gpioa  (*((struct stm_gpio *) 0x48000000))
 190
 191 /* Flash interface */
 192
 193 struct stm_flash {
 194         vuint32_t       acr;
 195         vuint32_t       keyr;
 196         vuint32_t       optkeyr;
 197         vuint32_t       sr;
 198
 199         vuint32_t       cr;
 200         vuint32_t       ar;
 201         vuint32_t       unused_0x18;
 202         vuint32_t       obr;
 203
 204         vuint32_t       wrpr;
 205 };
 206
 207 extern struct stm_flash stm_flash;
 208
 209 #define STM_FLASH_ACR_PRFTBS    (5)
 210 #define STM_FLASH_ACR_PRFTBE    (4)
 211 #define STM_FLASH_ACR_LATENCY   (0)
 212 #define  STM_FLASH_ACR_LATENCY_0                0
 213 #define  STM_FLASH_ACR_LATENCY_1                1
 214
 215 #define STM_FLASH_SR_EOP                5
 216 #define STM_FLASH_SR_WRPRTERR           4
 217 #define STM_FLASH_SR_PGERR              2
 218 #define STM_FLASH_SR_BSY                0
 219
 220 #define STM_FLASH_CR_OBL_LAUNCH         13
 221 #define STM_FLASH_CR_EOPIE              12
 222 #define STM_FLASH_CR_ERRIE              10
 223 #define STM_FLASH_CR_OPTWRE             9
 224 #define STM_FLASH_CR_LOCK               7
 225 #define STM_FLASH_CR_STRT               6
 226 #define STM_FLASH_CR_OPTER              5
 227 #define STM_FLASH_CR_OPTPG              4
 228 #define STM_FLASH_CR_MER                2
 229 #define STM_FLASH_CR_PER                1
 230 #define STM_FLASH_CR_PG                 0
 231
 232 #define STM_FLASH_OBR_DATA1             24
 233 #define STM_FLASH_OBR_DATA0             16
 234 #define STM_FLASH_OBR_BOOT_SEL          15
 235 #define STM_FLASH_OBR_RAM_PARITY_CHECK  14
 236 #define STM_FLASH_OBR_VDDA_MONITOR      13
 237 #define STM_FLASH_OBR_NBOOT1            12
 238 #define STM_FLASH_OBR_NBOOT0            11
 239 #define STM_FLASH_OBR_NRST_STDBY        10
 240 #define STM_FLASH_OBR_NRST_STOP         9
 241 #define STM_FLASH_OBR_WDG_SW            8
 242 #define STM_FLASH_OBR_RDPRT             1
 243 #define  STM_FLASH_OBR_RDPRT_LEVEL0             0
 244 #define  STM_FLASH_OBR_RDPRT_LEVEL1             1
 245 #define  STM_FLASH_OBR_RDPRT_LEVEL2             3
 246 #define STM_FLASH_OBR_OPTERR            0
 247
 248 #define STM_FLASH_KEYR_KEY1     0x45670123
 249 #define STM_FLASH_KEYR_KEY2     0xcdef89ab
 250
 251 struct stm_rcc {
 252         vuint32_t       cr;
 253         vuint32_t       cfgr;
 254         vuint32_t       cir;
 255         vuint32_t       apb2rstr;
 256
 257         vuint32_t       apb1rstr;
 258         vuint32_t       ahbenr;
 259         vuint32_t       apb2enr;
 260         vuint32_t       apb1enr;
 261
 262         vuint32_t       bdcr;
 263         vuint32_t       csr;
 264         vuint32_t       ahbrstr;
 265         vuint32_t       cfgr2;
 266
 267         vuint32_t       cfgr3;
 268         vuint32_t       cr2;
 269 };
 270
 271 extern struct stm_rcc stm_rcc;
 272
 273 /* Nominal high speed internal oscillator frequency is 8MHz */
 274 #define STM_HSI_FREQ            8000000
 275
 276 #define STM_RCC_CR_PLLRDY       (25)
 277 #define STM_RCC_CR_PLLON        (24)
 278 #define STM_RCC_CR_CSSON        (19)
 279 #define STM_RCC_CR_HSEBYP       (18)
 280 #define STM_RCC_CR_HSERDY       (17)
 281 #define STM_RCC_CR_HSEON        (16)
 282 #define STM_RCC_CR_HSICAL       (8)
 283 #define STM_RCC_CR_HSITRIM      (3)
 284 #define STM_RCC_CR_HSIRDY       (1)
 285 #define STM_RCC_CR_HSION        (0)
 286
 287 #define STM_RCC_CFGR_PLL_NODIV  (31)
 288 #define  STM_RCC_CFGR_PLL_NODIV_DIV_1   1
 289 #define  STM_RCC_CFGR_PLL_NODIV_DIV_2   0
 290
 291 #define STM_RCC_CFGR_MCOPRE     (28)
 292 #define  STM_RCC_CFGR_MCOPRE_DIV_1      0
 293 #define  STM_RCC_CFGR_MCOPRE_DIV_2      1
 294 #define  STM_RCC_CFGR_MCOPRE_DIV_4      2
 295 #define  STM_RCC_CFGR_MCOPRE_DIV_8      3
 296 #define  STM_RCC_CFGR_MCOPRE_DIV_16     4
 297 #define  STM_RCC_CFGR_MCOPRE_DIV_32     5
 298 #define  STM_RCC_CFGR_MCOPRE_DIV_64     6
 299 #define  STM_RCC_CFGR_MCOPRE_DIV_128    7
 300 #define  STM_RCC_CFGR_MCOPRE_DIV_MASK   7UL
 301
 302 #define STM_RCC_CFGR_MCO        (24)
 303 # define STM_RCC_CFGR_MCO_DISABLE       0
 304 # define STM_RCC_CFGR_MCO_RC            1
 305 # define STM_RCC_CFGR_MCO_LSI           2
 306 # define STM_RCC_CFGR_MCO_LSE           3
 307 # define STM_RCC_CFGR_MCO_SYSCLK        4
 308 # define STM_RCC_CFGR_MCO_HSI           5
 309 # define STM_RCC_CFGR_MCO_HSE           6
 310 # define STM_RCC_CFGR_MCO_PLLCLK        7
 311 # define STM_RCC_CFGR_MCO_HSI48         8
 312 # define STM_RCC_CFGR_MCO_MASK          (0xfUL)
 313
 314 #define STM_RCC_CFGR_PLLMUL     (18)
 315 #define  STM_RCC_CFGR_PLLMUL_2          0
 316 #define  STM_RCC_CFGR_PLLMUL_3          1
 317 #define  STM_RCC_CFGR_PLLMUL_4          2
 318 #define  STM_RCC_CFGR_PLLMUL_5          3
 319 #define  STM_RCC_CFGR_PLLMUL_6          4
 320 #define  STM_RCC_CFGR_PLLMUL_7          5
 321 #define  STM_RCC_CFGR_PLLMUL_8          6
 322 #define  STM_RCC_CFGR_PLLMUL_9          7
 323 #define  STM_RCC_CFGR_PLLMUL_10         8
 324 #define  STM_RCC_CFGR_PLLMUL_11         9
 325 #define  STM_RCC_CFGR_PLLMUL_12         10
 326 #define  STM_RCC_CFGR_PLLMUL_13         11
 327 #define  STM_RCC_CFGR_PLLMUL_14         12
 328 #define  STM_RCC_CFGR_PLLMUL_15         13
 329 #define  STM_RCC_CFGR_PLLMUL_16         14
 330 #define  STM_RCC_CFGR_PLLMUL_MASK       0xfUL
 331
 332 #define STM_RCC_CFGR_PLLXTPRE   (17)
 333
 334 #define STM_RCC_CFGR_PLLSRC     (15)
 335 # define STM_RCC_CFGR_PLLSRC_HSI_DIV_2  0
 336 # define STM_RCC_CFGR_PLLSRC_HSI        1
 337 # define STM_RCC_CFGR_PLLSRC_HSE        2
 338 # define STM_RCC_CFGR_PLLSRC_HSI48      3
 339
 340 #define STM_RCC_CFGR_ADCPRE     (14)
 341
 342 #define STM_RCC_CFGR_PPRE       (8)
 343 #define  STM_RCC_CFGR_PPRE_DIV_1        0
 344 #define  STM_RCC_CFGR_PPRE_DIV_2        4
 345 #define  STM_RCC_CFGR_PPRE_DIV_4        5
 346 #define  STM_RCC_CFGR_PPRE_DIV_8        6
 347 #define  STM_RCC_CFGR_PPRE_DIV_16       7
 348 #define  STM_RCC_CFGR_PPRE_MASK         7UL
 349
 350 #define STM_RCC_CFGR_HPRE       (4)
 351 #define  STM_RCC_CFGR_HPRE_DIV_1        0
 352 #define  STM_RCC_CFGR_HPRE_DIV_2        8
 353 #define  STM_RCC_CFGR_HPRE_DIV_4        9
 354 #define  STM_RCC_CFGR_HPRE_DIV_8        0xa
 355 #define  STM_RCC_CFGR_HPRE_DIV_16       0xb
 356 #define  STM_RCC_CFGR_HPRE_DIV_64       0xc
 357 #define  STM_RCC_CFGR_HPRE_DIV_128      0xd
 358 #define  STM_RCC_CFGR_HPRE_DIV_256      0xe
 359 #define  STM_RCC_CFGR_HPRE_DIV_512      0xf
 360 #define  STM_RCC_CFGR_HPRE_MASK         0xfUL
 361
 362 #define STM_RCC_CFGR_SWS        (2)
 363 #define  STM_RCC_CFGR_SWS_HSI           0
 364 #define  STM_RCC_CFGR_SWS_HSE           1
 365 #define  STM_RCC_CFGR_SWS_PLL           2
 366 #define  STM_RCC_CFGR_SWS_HSI48         3
 367 #define  STM_RCC_CFGR_SWS_MASK          3UL
 368
 369 #define STM_RCC_CFGR_SW         (0)
 370 #define  STM_RCC_CFGR_SW_HSI            0
 371 #define  STM_RCC_CFGR_SW_HSE            1
 372 #define  STM_RCC_CFGR_SW_PLL            2
 373 #define  STM_RCC_CFGR_SW_HSI48          3
 374 #define  STM_RCC_CFGR_SW_MASK           3UL
 375
 376 #define STM_RCC_APB2RSTR_DBGMCURST      22
 377 #define STM_RCC_APB2RSTR_TIM17RST       18
 378 #define STM_RCC_APB2RSTR_TIM16RST       17
 379 #define STM_RCC_APB2RSTR_TIM15RST       16
 380 #define STM_RCC_APB2RSTR_USART1RST      14
 381 #define STM_RCC_APB2RSTR_SPI1RST        12
 382 #define STM_RCC_APB2RSTR_TIM1RST        11
 383 #define STM_RCC_APB2RSTR_ADCRST         9
 384 #define STM_RCC_APB2RSTR_USART8RST      7
 385 #define STM_RCC_APB2RSTR_USART7RST      6
 386 #define STM_RCC_APB2RSTR_USART6RST      5
 387 #define STM_RCC_APB2RSTR_SYSCFGRST      1
 388
 389 #define STM_RCC_APB1RSTR_CECRST         30
 390 #define STM_RCC_APB1RSTR_DACRST         29
 391 #define STM_RCC_APB1RSTR_PWRRST         28
 392 #define STM_RCC_APB1RSTR_CRSRST         27
 393 #define STM_RCC_APB1RSTR_CANRST         25
 394 #define STM_RCC_APB1RSTR_USBRST         23
 395 #define STM_RCC_APB1RSTR_I2C2RST        22
 396 #define STM_RCC_APB1RSTR_I1C1RST        21
 397 #define STM_RCC_APB1RSTR_USART5RST      20
 398 #define STM_RCC_APB1RSTR_USART4RST      19
 399 #define STM_RCC_APB1RSTR_USART3RST      18
 400 #define STM_RCC_APB1RSTR_USART2RST      17
 401 #define STM_RCC_APB1RSTR_SPI2RST        14
 402 #define STM_RCC_APB1RSTR_WWDGRST        11
 403 #define STM_RCC_APB1RSTR_TIM14RST       8
 404 #define STM_RCC_APB1RSTR_TIM7RST        5
 405 #define STM_RCC_APB1RSTR_TIM6RST        4
 406 #define STM_RCC_APB1RSTR_TIM3RST        1
 407 #define STM_RCC_APB1RSTR_TIM2RST        0
 408
 409 #define STM_RCC_AHBENR_TSCEN    24
 410 #define STM_RCC_AHBENR_IOPFEN   22
 411 #define STM_RCC_AHBENR_IOPEEN   21
 412 #define STM_RCC_AHBENR_IOPDEN   20
 413 #define STM_RCC_AHBENR_IOPCEN   19
 414 #define STM_RCC_AHBENR_IOPBEN   18
 415 #define STM_RCC_AHBENR_IOPAEN   17
 416 #define STM_RCC_AHBENR_CRCEN    6
 417 #define STM_RCC_AHBENR_FLITFEN  4
 418 #define STM_RCC_AHBENR_SRAMEN   2
 419 #define STM_RCC_AHBENR_DMA2EN   1
 420 #define STM_RCC_AHBENR_DMAEN    0
 421
 422 #define STM_RCC_APB2ENR_DBGMCUEN        22
 423 #define STM_RCC_APB2ENR_TIM17EN         18
 424 #define STM_RCC_APB2ENR_TIM16EN         17
 425 #define STM_RCC_APB2ENR_TIM15EN         16
 426 #define STM_RCC_APB2ENR_USART1EN        14
 427 #define STM_RCC_APB2ENR_SPI1EN          12
 428 #define STM_RCC_APB2ENR_TIM1EN          11
 429 #define STM_RCC_APB2ENR_ADCEN           9
 430 #define STM_RCC_APB2ENR_USART8EN        7
 431 #define STM_RCC_APB2ENR_USART7EN        6
 432 #define STM_RCC_APB2ENR_USART6EN        5
 433 #define STM_RCC_APB2ENR_SYSCFGCOMPEN    0
 434
 435 #define STM_RCC_APB1ENR_CECEN           30
 436 #define STM_RCC_APB1ENR_DACEN           29
 437 #define STM_RCC_APB1ENR_PWREN           28
 438 #define STM_RCC_APB1ENR_CRSEN           27
 439 #define STM_RCC_APB1ENR_CANEN           25
 440 #define STM_RCC_APB1ENR_USBEN           23
 441 #define STM_RCC_APB1ENR_I2C2EN          22
 442 #define STM_RCC_APB1ENR_IC21EN          21
 443 #define STM_RCC_APB1ENR_USART5EN        20
 444 #define STM_RCC_APB1ENR_USART4EN        19
 445 #define STM_RCC_APB1ENR_USART3EN        18
 446 #define STM_RCC_APB1ENR_USART2EN        17
 447 #define STM_RCC_APB1ENR_SPI2EN          14
 448 #define STM_RCC_APB1ENR_WWDGEN          11
 449 #define STM_RCC_APB1ENR_TIM14EN         8
 450 #define STM_RCC_APB1ENR_TIM7EN          5
 451 #define STM_RCC_APB1ENR_TIM6EN          4
 452 #define STM_RCC_APB1ENR_TIM3EN          1
 453 #define STM_RCC_APB1ENR_TIM2EN          0
 454
 455 #define STM_RCC_CSR_LPWRRSTF            (31)
 456 #define STM_RCC_CSR_WWDGRSTF            (30)
 457 #define STM_RCC_CSR_IWDGRSTF            (29)
 458 #define STM_RCC_CSR_SFTRSTF             (28)
 459 #define STM_RCC_CSR_PORRSTF             (27)
 460 #define STM_RCC_CSR_PINRSTF             (26)
 461 #define STM_RCC_CSR_OBLRSTF             (25)
 462 #define STM_RCC_CSR_RMVF                (24)
 463 #define STM_RCC_CSR_V18PWRRSTF          (23)
 464 #define STM_RCC_CSR_LSIRDY              (1)
 465 #define STM_RCC_CSR_LSION               (0)
 466
 467 #define STM_RCC_CR2_HSI48CAL            24
 468 #define STM_RCC_CR2_HSI48RDY            17
 469 #define STM_RCC_CR2_HSI48ON             16
 470 #define STM_RCC_CR2_HSI14CAL            8
 471 #define STM_RCC_CR2_HSI14TRIM           3
 472 #define STM_RCC_CR2_HSI14DIS            2
 473 #define STM_RCC_CR2_HSI14RDY            1
 474 #define STM_RCC_CR2_HSI14ON             0
 475
 476 #define STM_RCC_CFGR2_PREDIV            0
 477 #define  STM_RCC_CFGR2_PREDIV_1                 0x0
 478 #define  STM_RCC_CFGR2_PREDIV_2                 0x1
 479 #define  STM_RCC_CFGR2_PREDIV_3                 0x2
 480 #define  STM_RCC_CFGR2_PREDIV_4                 0x3
 481 #define  STM_RCC_CFGR2_PREDIV_5                 0x4
 482 #define  STM_RCC_CFGR2_PREDIV_6                 0x5
 483 #define  STM_RCC_CFGR2_PREDIV_7                 0x6
 484 #define  STM_RCC_CFGR2_PREDIV_8                 0x7
 485 #define  STM_RCC_CFGR2_PREDIV_9                 0x8
 486 #define  STM_RCC_CFGR2_PREDIV_10                0x9
 487 #define  STM_RCC_CFGR2_PREDIV_11                0xa
 488 #define  STM_RCC_CFGR2_PREDIV_12                0xb
 489 #define  STM_RCC_CFGR2_PREDIV_13                0xc
 490 #define  STM_RCC_CFGR2_PREDIV_14                0xd
 491 #define  STM_RCC_CFGR2_PREDIV_15                0xe
 492 #define  STM_RCC_CFGR2_PREDIV_16                0xf
 493
 494 #define STM_RCC_CFGR3_USART3SW          18
 495 #define STM_RCC_CFGR3_USART2SW          16
 496 #define STM_RCC_CFGR3_ADCSW             8
 497 #define STM_RCC_CFGR3_USBSW             7
 498 #define STM_RCC_CFGR3_CECSW             6
 499 #define STM_RCC_CFGR3_I2C1SW            4
 500 #define STM_RCC_CFGR3_USART1SW          0
 501
 502 struct stm_crs {
 503         vuint32_t       cr;
 504         vuint32_t       cfgr;
 505         vuint32_t       isr;
 506         vuint32_t       icr;
 507 };
 508
 509 extern struct stm_crs stm_crs;
 510
 511 #define STM_CRS_CR_TRIM         8
 512 #define STM_CRS_CR_SWSYNC       7
 513 #define STM_CRS_CR_AUTOTRIMEN   6
 514 #define STM_CRS_CR_CEN          5
 515 #define STM_CRS_CR_ESYNCIE      3
 516 #define STM_CRS_CR_ERRIE        2
 517 #define STM_CRS_CR_SYNCWARNIE   1
 518 #define STM_CRS_CR_SYNCOKIE     0
 519
 520 #define STM_CRS_CFGR_SYNCPOL    31
 521 #define STM_CRS_CFGR_SYNCSRC    28
 522 #define  STM_CRS_CFGR_SYNCSRC_GPIO      0
 523 #define  STM_CRS_CFGR_SYNCSRC_LSE       1
 524 #define  STM_CRS_CFGR_SYNCSRC_USB       2
 525 #define STM_CRS_CFGR_SYNCDIV    24
 526 #define  STM_CRS_CFGR_SYNCDIV_1         0
 527 #define  STM_CRS_CFGR_SYNCDIV_2         1
 528 #define  STM_CRS_CFGR_SYNCDIV_4         2
 529 #define  STM_CRS_CFGR_SYNCDIV_8         3
 530 #define  STM_CRS_CFGR_SYNCDIV_16        4
 531 #define  STM_CRS_CFGR_SYNCDIV_32        5
 532 #define  STM_CRS_CFGR_SYNCDIV_64        6
 533 #define  STM_CRS_CFGR_SYNCDIV_128       7
 534 #define STM_CRS_CFGR_FELIM      16
 535 #define STM_CRS_CFGR_RELOAD     0
 536
 537 #define STM_CRS_ISR_FECAP       16
 538 #define STM_CRS_ISR_FEDIR       15
 539 #define STM_CRS_ISR_TRIMOVF     10
 540 #define STM_CRS_ISR_SYNCMISS    9
 541 #define STM_CRS_ISR_SYNCERR     8
 542 #define STM_CRS_ISR_ESYNCF      3
 543 #define STM_CRS_ISR_ERRF        2
 544 #define STM_CRS_ISR_SYNCWARNF   1
 545 #define STM_CRS_ISR_SYNCOKF     0
 546
 547 #define STM_CRS_ICR_ESYNCC      3
 548 #define STM_CRS_ICR_ERRC        2
 549 #define STM_CRS_ICR_SYNCWARNC   1
 550 #define STM_CRS_ICR_SYNCOKC     0
 551
 552 struct stm_pwr {
 553         vuint32_t       cr;
 554         vuint32_t       csr;
 555 };
 556
 557 extern struct stm_pwr stm_pwr;
 558
 559 #define stm_pwr (*(struct stm_pwr *) 0x40007000)
 560
 561 #define STM_PWR_CR_DBP          (8)
 562
 563 #define STM_PWR_CR_PLS          (5)
 564 #define  STM_PWR_CR_PLS_2_0     0
 565 #define  STM_PWR_CR_PLS_2_1     1
 566 #define  STM_PWR_CR_PLS_2_2     2
 567 #define  STM_PWR_CR_PLS_2_3     3
 568 #define  STM_PWR_CR_PLS_2_4     4
 569 #define  STM_PWR_CR_PLS_2_5     5
 570 #define  STM_PWR_CR_PLS_2_6     6
 571 #define  STM_PWR_CR_PLS_EXT     7
 572 #define  STM_PWR_CR_PLS_MASK    7
 573
 574 #define STM_PWR_CR_PVDE         (4)
 575 #define STM_PWR_CR_CSBF         (3)
 576 #define STM_PWR_CR_CWUF         (2)
 577 #define STM_PWR_CR_PDDS         (1)
 578 #define STM_PWR_CR_LPDS         (0)
 579
 580 #define STM_PWR_CSR_EWUP3       (10)
 581 #define STM_PWR_CSR_EWUP2       (9)
 582 #define STM_PWR_CSR_EWUP1       (8)
 583 #define STM_PWR_CSR_REGLPF      (5)
 584 #define STM_PWR_CSR_VOSF        (4)
 585 #define STM_PWR_CSR_VREFINTRDYF (3)
 586 #define STM_PWR_CSR_PVDO        (2)
 587 #define STM_PWR_CSR_SBF         (1)
 588 #define STM_PWR_CSR_WUF         (0)
 589
 590 struct stm_crc {
 591         union {
 592                 vuint32_t       u32;
 593                 vuint16_t       u16;
 594                 vuint8_t        u8;
 595         }               dr;
 596         vuint32_t       idr;
 597         vuint32_t       cr;
 598         uint32_t        _0c;
 599
 600         vuint32_t       init;
 601         vuint32_t       pol;
 602 };
 603
 604 extern struct stm_crc   stm_crc;
 605
 606 #define stm_crc (*((struct stm_crc *) 0x40023000))
 607
 608 #define STM_CRC_CR_REV_OUT      7
 609 #define STM_CRC_CR_REV_IN       5
 610 #define  STM_CRC_CR_REV_IN_NONE         0
 611 #define  STM_CRC_CR_REV_IN_BY_BYTE      1
 612 #define  STM_CRC_CR_REV_IN_BY_HALF_WORD 2
 613 #define  STM_CRC_CR_REV_IN_BY_WORD      3
 614 #define STM_CRC_CR_POLYSIZE     3
 615 #define  STM_CRC_CR_POLYSIZE_32         0
 616 #define  STM_CRC_CR_POLYSIZE_16         1
 617 #define  STM_CRC_CR_POLYSIZE_8          2
 618 #define  STM_CRC_CR_POLYSIZE_7          3
 619 #define STM_CRC_CR_RESET        0
 620
 621 /* The SYSTICK starts at 0xe000e010 */
 622
 623 struct stm_systick {
 624         vuint32_t       csr;
 625         vuint32_t       rvr;
 626         vuint32_t       cvr;
 627         vuint32_t       calib;
 628 };
 629
 630 extern struct stm_systick stm_systick;
 631
 632 #define STM_SYSTICK_CSR_ENABLE          0
 633 #define STM_SYSTICK_CSR_TICKINT         1
 634 #define STM_SYSTICK_CSR_CLKSOURCE       2
 635 #define  STM_SYSTICK_CSR_CLKSOURCE_EXTERNAL             0
 636 #define  STM_SYSTICK_CSR_CLKSOURCE_HCLK_8               1
 637 #define STM_SYSTICK_CSR_COUNTFLAG       16
 638
 639 /* The NVIC starts at 0xe000e100, so add that to the offsets to find the absolute address */
 640
 641 struct stm_nvic {
 642         vuint32_t       iser;           /* 0x000 0xe000e100 Set Enable Register */
 643
 644         uint8_t         _unused020[0x080 - 0x004];
 645
 646         vuint32_t       icer;           /* 0x080 0xe000e180 Clear Enable Register */
 647
 648         uint8_t         _unused0a0[0x100 - 0x084];
 649
 650         vuint32_t       ispr;           /* 0x100 0xe000e200 Set Pending Register */
 651
 652         uint8_t         _unused120[0x180 - 0x104];
 653
 654         vuint32_t       icpr;           /* 0x180 0xe000e280 Clear Pending Register */
 655
 656         uint8_t         _unused1a0[0x300 - 0x184];
 657
 658         vuint32_t       ipr[8];         /* 0x300 0xe000e400 Priority Register */
 659 };
 660
 661 extern struct stm_nvic stm_nvic;
 662
 663 #define IRQ_MASK(irq)   (1 << (irq))
 664 #define IRQ_BOOL(v,irq) (((v) >> (irq)) & 1)
 665
 666 static inline void
 667 stm_nvic_set_enable(int irq) {
 668         stm_nvic.iser = IRQ_MASK(irq);
 669 }
 670
 671 static inline void
 672 stm_nvic_clear_enable(int irq) {
 673         stm_nvic.icer = IRQ_MASK(irq);
 674 }
 675
 676 static inline int
 677 stm_nvic_enabled(int irq) {
 678         return IRQ_BOOL(stm_nvic.iser, irq);
 679 }
 680
 681 static inline void
 682 stm_nvic_set_pending(int irq) {
 683         stm_nvic.ispr = IRQ_MASK(irq);
 684 }
 685
 686 static inline void
 687 stm_nvic_clear_pending(int irq) {
 688         stm_nvic.icpr = IRQ_MASK(irq);
 689 }
 690
 691 static inline int
 692 stm_nvic_pending(int irq) {
 693         return IRQ_BOOL(stm_nvic.ispr, irq);
 694 }
 695
 696 #define IRQ_PRIO_REG(irq)       ((irq) >> 2)
 697 #define IRQ_PRIO_BIT(irq)       (((irq) & 3) << 3)
 698 #define IRQ_PRIO_MASK(irq)      (0xffUL << IRQ_PRIO_BIT(irq))
 699
 700 static inline void
 701 stm_nvic_set_priority(int irq, uint8_t prio) {
 702         int             n = IRQ_PRIO_REG(irq);
 703         uint32_t        v;
 704
 705         v = stm_nvic.ipr[n];
 706         v &= ~IRQ_PRIO_MASK(irq);
 707         v |= (prio) << IRQ_PRIO_BIT(irq);
 708         stm_nvic.ipr[n] = v;
 709 }
 710
 711 static inline uint8_t
 712 stm_nvic_get_priority(int irq) {
 713         return (stm_nvic.ipr[IRQ_PRIO_REG(irq)] >> IRQ_PRIO_BIT(irq)) & IRQ_PRIO_MASK(0);
 714 }
 715
 716 struct stm_scb {
 717         vuint32_t       cpuid;
 718         vuint32_t       icsr;
 719         vuint32_t       vtor;
 720         vuint32_t       aircr;
 721
 722         vuint32_t       scr;
 723         vuint32_t       ccr;
 724         vuint32_t       shpr1;
 725         vuint32_t       shpr2;
 726
 727         vuint32_t       shpr3;
 728         vuint32_t       shcrs;
 729         vuint32_t       cfsr;
 730         vuint32_t       hfsr;
 731
 732         uint32_t        unused_30;
 733         vuint32_t       mmfar;
 734         vuint32_t       bfar;
 735 };
 736
 737 extern struct stm_scb stm_scb;
 738
 739 #define stm_scb (*(struct stm_scb *) 0xe000ed00)
 740
 741 #define STM_SCB_AIRCR_VECTKEY           16
 742 #define  STM_SCB_AIRCR_VECTKEY_KEY              0x05fa
 743 #define STM_SCB_AIRCR_PRIGROUP          8
 744 #define STM_SCB_AIRCR_SYSRESETREQ       2
 745 #define STM_SCB_AIRCR_VECTCLRACTIVE     1
 746 #define STM_SCB_AIRCR_VECTRESET         0
 747
 748 #define STM_SCB_SCR_SEVONPEND           4
 749 #define STM_SCB_SCR_SLEEPDEEP           2
 750 #define STM_SCB_SCR_SLEEPONEXIT         1
 751
 752 #define STM_ISR_WWDG_POS                0
 753 #define STM_ISR_PVD_VDDIO2_POS          1
 754 #define STM_ISR_RTC_POS                 2
 755 #define STM_ISR_FLASH_POS               3
 756 #define STM_ISR_RCC_CRS_POS             4
 757 #define STM_ISR_EXTI0_1_POS             5
 758 #define STM_ISR_EXTI2_3_POS             6
 759 #define STM_ISR_EXTI4_15_POS            7
 760 #define STM_ISR_TSC_POS                 8
 761 #define STM_ISR_DMA_CH1_POS             9
 762 #define STM_ISR_DMA_CH2_3_DMA2_CH1_2_POS        10
 763 #define STM_ISR_DMA_CH4_5_6_7_DMA2_CH3_4_5_POS  11
 764 #define STM_ISR_ADC_COMP_POS            12
 765 #define STM_ISR_TIM1_BRK_UP_TRG_COM_POS 13
 766 #define STM_ISR_TIM1_CC_POS             14
 767 #define STM_ISR_TIM2_POS                15
 768 #define STM_ISR_TIM3_POS                16
 769 #define STM_ISR_TIM6_DAC_POS            17
 770 #define STM_ISR_TIM7_POS                18
 771 #define STM_ISR_TIM14_POS               19
 772 #define STM_ISR_TIM15_POS               20
 773 #define STM_ISR_TIM16_POS               21
 774 #define STM_ISR_TIM17_POS               22
 775 #define STM_ISR_I2C1_POS                23
 776 #define STM_ISR_I2C2_POS                24
 777 #define STM_ISR_SPI1_POS                25
 778 #define STM_ISR_SPI2_POS                26
 779 #define STM_ISR_USART1_POS              27
 780 #define STM_ISR_USART2_POS              28
 781 #define STM_ISR_UASART3_4_5_6_7_8_POS   29
 782 #define STM_ISR_CEC_CAN_POS             30
 783 #define STM_ISR_USB_POS                 31
 784
 785 struct stm_syscfg {
 786         vuint32_t       cfgr1;
 787         uint32_t        reserved_04;
 788         vuint32_t       exticr[4];
 789         vuint32_t       cfgr2;
 790         uint8_t         reserved_1c[0x80-0x1c];
 791         vuint32_t       itline[31];
 792 };
 793
 794 extern struct stm_syscfg stm_syscfg;
 795
 796 #define STM_SYSCFG_CFGR1_TIM3_DMA_RMP   30
 797 #define STM_SYSCFG_CFGR1_TIM2_DMA_RMP   29
 798 #define STM_SYSCFG_CFGR1_TIM1_DMA_RMP   28
 799 #define STM_SYSCFG_CFGR1_I2C1_DMA_RMP   27
 800 #define STM_SYSCFG_CFGR1_USART3_DMA_RMP 26
 801 #define STM_SYSCFG_CFGR1_USART2_DMA_RMP 25
 802 #define STM_SYSCFG_CFGR1_SPI2_DMA_RMP   24
 803 #define STM_SYSCFG_CFGR1_I2C_PA10_FMP   23
 804 #define STM_SYSCFG_CFGR1_I2C_PA9_FMP    22
 805 #define STM_SYSCFG_CFGR1_I2C2_FMP       21
 806 #define STM_SYSCFG_CFGR1_I2C1_FMP       20
 807 #define STM_SYSCFG_CFGR1_I2C_PB9_FMP    19
 808 #define STM_SYSCFG_CFGR1_I2C_PB8_FMP    18
 809 #define STM_SYSCFG_CFGR1_I2C_PB7_FMP    17
 810 #define STM_SYSCFG_CFGR1_I2C_PB6_FMP    16
 811 #define STM_SYSCFG_CFGR1_TIM17_DMA_RMP2 14
 812 #define STM_SYSCFG_CFGR1_TIM16_DMA_RMP2 13
 813 #define STM_SYSCFG_CFGR1_TIM17_DMA_RMP  12
 814 #define STM_SYSCFG_CFGR1_TIM16_DMA_RMP  11
 815 #define STM_SYSCFG_CFGR1_USART1_RX_DMA_RMP      10
 816 #define STM_SYSCFG_CFGR1_USART1_TX_DMA_RMP      9
 817 #define STM_SYSCFG_CFGR1_ADC_DMA_RMP            8
 818 #define STM_SYSCFG_CFGR1_IRDA_ENV_SEL   6
 819 #define  STM_SYSCFG_CFGR1_IRDA_ENV_SEL_TIMER16  0
 820 #define  STM_SYSCFG_CFGR1_IRDA_ENV_SEL_USART1   1
 821 #define  STM_SYSCFG_CFGR1_IRDA_ENV_SEL_USART4   2
 822 #define STM_SYSCFG_CFGR1_PA11_PA12_RMP  4
 823 #define STM_SYSCFG_CFGR1_MEM_MODE       0
 824 #define  STM_SYSCFG_CFGR1_MEM_MODE_MAIN_FLASH   0
 825 #define  STM_SYSCFG_CFGR1_MEM_MODE_SYSTEM_FLASH 1
 826 #define  STM_SYSCFG_CFGR1_MEM_MODE_SRAM         3
 827 #define  STM_SYSCFG_CFGR1_MEM_MODE_MASK         3UL
 828
 829 #define STM_SYSCFG_EXTICR_PA            0
 830 #define STM_SYSCFG_EXTICR_PB            1
 831 #define STM_SYSCFG_EXTICR_PC            2
 832 #define STM_SYSCFG_EXTICR_PD            3
 833 #define STM_SYSCFG_EXTICR_PE            4
 834 #define STM_SYSCFG_EXTICR_PF            5
 835
 836 static inline void
 837 stm_exticr_set(struct stm_gpio *gpio, int pin) {
 838         uint8_t reg = (uint8_t) pin >> 2;
 839         uint8_t shift = ((uint8_t) pin & 3) << 2;
 840         uint8_t val = 0;
 841
 842         /* Enable SYSCFG */
 843         stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_SYSCFGCOMPEN);
 844
 845         if (gpio == &stm_gpioa)
 846                 val = STM_SYSCFG_EXTICR_PA;
 847         else if (gpio == &stm_gpiob)
 848                 val = STM_SYSCFG_EXTICR_PB;
 849         else if (gpio == &stm_gpioc)
 850                 val = STM_SYSCFG_EXTICR_PC;
 851         else if (gpio == &stm_gpiof)
 852                 val = STM_SYSCFG_EXTICR_PF;
 853
 854         stm_syscfg.exticr[reg] = (stm_syscfg.exticr[reg] & ~(0xfUL << shift)) | val << shift;
 855 }
 856
 857 struct stm_dma_channel {
 858         vuint32_t       ccr;
 859         vuint32_t       cndtr;
 860         vvoid_t         cpar;
 861         vvoid_t         cmar;
 862         vuint32_t       reserved;
 863 };
 864
 865 #define STM_NUM_DMA     5
 866
 867 struct stm_dma {
 868         vuint32_t               isr;
 869         vuint32_t               ifcr;
 870         struct stm_dma_channel  channel[STM_NUM_DMA];
 871 };
 872
 873 extern struct stm_dma stm_dma;
 874
 875 /* DMA channels go from 1 to 5, instead of 0 to 4 (sigh)
 876  */
 877
 878 #define STM_DMA_INDEX(channel)          ((channel) - 1)
 879
 880 #define STM_DMA_ISR(index)              ((index) << 2)
 881 #define STM_DMA_ISR_MASK                        0xfUL
 882 #define STM_DMA_ISR_TEIF                        3
 883 #define STM_DMA_ISR_HTIF                        2
 884 #define STM_DMA_ISR_TCIF                        1
 885 #define STM_DMA_ISR_GIF                         0
 886
 887 #define STM_DMA_IFCR(index)             ((index) << 2)
 888 #define STM_DMA_IFCR_MASK                       0xfUL
 889 #define STM_DMA_IFCR_CTEIF                      3
 890 #define STM_DMA_IFCR_CHTIF                      2
 891 #define STM_DMA_IFCR_CTCIF                      1
 892 #define STM_DMA_IFCR_CGIF                       0
 893
 894 #define STM_DMA_CCR_MEM2MEM             (14)
 895
 896 #define STM_DMA_CCR_PL                  (12)
 897 #define  STM_DMA_CCR_PL_LOW                     (0)
 898 #define  STM_DMA_CCR_PL_MEDIUM                  (1)
 899 #define  STM_DMA_CCR_PL_HIGH                    (2)
 900 #define  STM_DMA_CCR_PL_VERY_HIGH               (3)
 901 #define  STM_DMA_CCR_PL_MASK                    (3UL)
 902
 903 #define STM_DMA_CCR_MSIZE               (10)
 904 #define  STM_DMA_CCR_MSIZE_8                    (0)
 905 #define  STM_DMA_CCR_MSIZE_16                   (1)
 906 #define  STM_DMA_CCR_MSIZE_32                   (2)
 907 #define  STM_DMA_CCR_MSIZE_MASK                 (3UL)
 908
 909 #define STM_DMA_CCR_PSIZE               (8)
 910 #define  STM_DMA_CCR_PSIZE_8                    (0)
 911 #define  STM_DMA_CCR_PSIZE_16                   (1)
 912 #define  STM_DMA_CCR_PSIZE_32                   (2)
 913 #define  STM_DMA_CCR_PSIZE_MASK                 (3UL)
 914
 915 #define STM_DMA_CCR_MINC                (7)
 916 #define STM_DMA_CCR_PINC                (6)
 917 #define STM_DMA_CCR_CIRC                (5)
 918 #define STM_DMA_CCR_DIR                 (4)
 919 #define  STM_DMA_CCR_DIR_PER_TO_MEM             0
 920 #define  STM_DMA_CCR_DIR_MEM_TO_PER             1
 921 #define STM_DMA_CCR_TEIE                (3)
 922 #define STM_DMA_CCR_HTIE                (2)
 923 #define STM_DMA_CCR_TCIE                (1)
 924 #define STM_DMA_CCR_EN                  (0)
 925
 926 /* DMA channel assignments. When a peripheral has multiple channels
 927  * (indicated with _<number>), then it can be configured to either
 928  * channel using syscfg.cfgr1
 929  */
 930
 931 #define STM_DMA_CHANNEL_ADC_1           1
 932 #define STM_DMA_CHANNEL_ADC_2           2
 933
 934 #define STM_DMA_CHANNEL_SPI1_RX         2
 935 #define STM_DMA_CHANNEL_SPI1_TX         3
 936
 937 #define STM_DMA_CHANNEL_SPI2_RX         4
 938 #define STM_DMA_CHANNEL_SPI2_TX         5
 939
 940 #define STM_DMA_CHANNEL_USART1_TX_1     2
 941 #define STM_DMA_CHANNEL_USART1_RX_1     3
 942 #define STM_DMA_CHANNEL_USART1_TX_2     4
 943 #define STM_DMA_CHANNEL_USART1_RX_2     5
 944
 945 #define STM_DMA_CHANNEL_USART2_RX       4
 946 #define STM_DMA_CHANNEL_USART2_TX       5
 947
 948 #define STM_DMA_CHANNEL_I2C1_TX         2
 949 #define STM_DMA_CHANNEL_I2C1_RX         3
 950
 951 #define STM_DMA_CHANNEL_I2C2_TX         4
 952 #define STM_DMA_CHANNEL_I2C2_RX         5
 953
 954 #define STM_DMA_CHANNEL_TIM1_CH1        2
 955 #define STM_DMA_CHANNEL_TIM1_CH2        3
 956 #define STM_DMA_CHANNEL_TIM1_CH4        4
 957 #define STM_DMA_CHANNEL_TIM1_TRIG       4
 958 #define STM_DMA_CHANNEL_TIM1_COM        4
 959 #define STM_DMA_CHANNEL_TIM1_CH3        5
 960 #define STM_DMA_CHANNEL_TIM1_UP         5
 961
 962 #define STM_DMA_CHANNEL_TIM2_CH3        1
 963 #define STM_DMA_CHANNEL_TIM2_UP         2
 964 #define STM_DMA_CHANNEL_TIM2_CH2        3
 965 #define STM_DMA_CHANNEL_TIM2_CH4        4
 966 #define STM_DMA_CHANNEL_TIM2_CH1        5
 967
 968 #define STM_DMA_CHANNEL_TIM3_CH3        2
 969 #define STM_DMA_CHANNEL_TIM3_CH4        3
 970 #define STM_DMA_CHANNEL_TIM3_UP         3
 971 #define STM_DMA_CHANNEL_TIM3_CH1        4
 972 #define STM_DMA_CHANNEL_TIM3_TRIG       4
 973
 974 #define STM_DMA_CHANNEL_TIM6_UP_DAC     2
 975
 976 #define STM_DMA_CHANNEL_TIM15_CH1       5
 977 #define STM_DMA_CHANNEL_TIM15_UP        5
 978 #define STM_DMA_CHANNEL_TIM15_TRIG      5
 979 #define STM_DMA_CHANNEL_TIM15_COM       5
 980
 981 #define STM_DMA_CHANNEL_TIM16_CH1_1     3
 982 #define STM_DMA_CHANNEL_TIM16_UP_1      3
 983 #define STM_DMA_CHANNEL_TIM16_CH1_2     4
 984 #define STM_DMA_CHANNEL_TIM16_UP_2      4
 985
 986 #define STM_DMA_CHANNEL_TIM17_CH1_1     1
 987 #define STM_DMA_CHANNEL_TIM17_UP_1      1
 988 #define STM_DMA_CHANNEL_TIM17_CH1_2     2
 989 #define STM_DMA_CHANNEL_TIM17_UP_2      2
 990
 991 /*
 992  * Only spi channel 1 and 2 can use DMA
 993  */
 994 #define STM_NUM_SPI     2
 995
 996 struct stm_spi {
 997         vuint32_t       cr1;
 998         vuint32_t       cr2;
 999         vuint32_t       sr;
1000         vuint32_t       dr;
1001         vuint32_t       crcpr;
1002         vuint32_t       rxcrcr;
1003         vuint32_t       txcrcr;
1004 };
1005
1006 extern struct stm_spi stm_spi1, stm_spi2, stm_spi3;
1007
1008 /* SPI channels go from 1 to 3, instead of 0 to 2 (sigh)
1009  */
1010
1011 #define STM_SPI_INDEX(channel)          ((channel) - 1)
1012
1013 #define STM_SPI_CR1_BIDIMODE            15
1014 #define STM_SPI_CR1_BIDIOE              14
1015 #define STM_SPI_CR1_CRCEN               13
1016 #define STM_SPI_CR1_CRCNEXT             12
1017 #define STM_SPI_CR1_CRCL                11
1018 #define STM_SPI_CR1_RXONLY              10
1019 #define STM_SPI_CR1_SSM                 9
1020 #define STM_SPI_CR1_SSI                 8
1021 #define STM_SPI_CR1_LSBFIRST            7
1022 #define STM_SPI_CR1_SPE                 6
1023 #define STM_SPI_CR1_BR                  3
1024 #define  STM_SPI_CR1_BR_PCLK_2                  0
1025 #define  STM_SPI_CR1_BR_PCLK_4                  1
1026 #define  STM_SPI_CR1_BR_PCLK_8                  2
1027 #define  STM_SPI_CR1_BR_PCLK_16                 3
1028 #define  STM_SPI_CR1_BR_PCLK_32                 4
1029 #define  STM_SPI_CR1_BR_PCLK_64                 5
1030 #define  STM_SPI_CR1_BR_PCLK_128                6
1031 #define  STM_SPI_CR1_BR_PCLK_256                7
1032 #define  STM_SPI_CR1_BR_MASK                    7UL
1033
1034 #define STM_SPI_CR1_MSTR                2
1035 #define STM_SPI_CR1_CPOL                1
1036 #define STM_SPI_CR1_CPHA                0
1037
1038 #define STM_SPI_CR2_LDMA_TX     14
1039 #define STM_SPI_CR2_LDMA_RX     13
1040 #define STM_SPI_CR2_FRXTH       12
1041 #define STM_SPI_CR2_DS          8
1042 #define  STM_SPI_CR2_DS_4               0x3
1043 #define  STM_SPI_CR2_DS_5               0x4
1044 #define  STM_SPI_CR2_DS_6               0x5
1045 #define  STM_SPI_CR2_DS_7               0x6
1046 #define  STM_SPI_CR2_DS_8               0x7
1047 #define  STM_SPI_CR2_DS_9               0x8
1048 #define  STM_SPI_CR2_DS_10              0x9
1049 #define  STM_SPI_CR2_DS_11              0xa
1050 #define  STM_SPI_CR2_DS_12              0xb
1051 #define  STM_SPI_CR2_DS_13              0xc
1052 #define  STM_SPI_CR2_DS_14              0xd
1053 #define  STM_SPI_CR2_DS_15              0xe
1054 #define  STM_SPI_CR2_DS_16              0xf
1055 #define STM_SPI_CR2_TXEIE       7
1056 #define STM_SPI_CR2_RXNEIE      6
1057 #define STM_SPI_CR2_ERRIE       5
1058 #define STM_SPI_CR2_FRF         4
1059 # define STM_SPI_CR2_FRF_MOTOROLA       0
1060 # define STM_SPI_CR2_FRF_TI             1
1061 #define STM_SPI_CR2_NSSP        3
1062 #define STM_SPI_CR2_SSOE        2
1063 #define STM_SPI_CR2_TXDMAEN     1
1064 #define STM_SPI_CR2_RXDMAEN     0
1065
1066 #define STM_SPI_SR_FTLVL        11
1067 #define STM_SPI_SR_FRLVL        9
1068 #define STM_SPI_SR_FRE          8
1069 #define STM_SPI_SR_BSY          7
1070 #define STM_SPI_SR_OVR          6
1071 #define STM_SPI_SR_MODF         5
1072 #define STM_SPI_SR_CRCERR       4
1073 #define STM_SPI_SR_UDR          3
1074 #define STM_SPI_SR_CHSIDE       2
1075 #define STM_SPI_SR_TXE          1
1076 #define STM_SPI_SR_RXNE         0
1077
1078 struct stm_adc {
1079         vuint32_t       isr;
1080         vuint32_t       ier;
1081         vuint32_t       cr;
1082         vuint32_t       cfgr1;
1083
1084         vuint32_t       cfgr2;
1085         vuint32_t       smpr;
1086         vuint32_t       r_18;
1087         vuint32_t       r_1c;
1088
1089         vuint32_t       tr;
1090         vuint32_t       r_24;
1091         vuint32_t       chselr;
1092         vuint32_t       r_2c;
1093
1094         vuint32_t       r_30[4];
1095
1096         vuint32_t       dr;
1097
1098         uint8_t         r_44[0x308 - 0x44];
1099         vuint32_t       ccr;
1100 };
1101
1102 extern struct stm_adc stm_adc;
1103
1104 #define STM_ADC_ISR_AWD         7
1105 #define STM_ADC_ISR_OVR         4
1106 #define STM_ADC_ISR_EOSEQ       3
1107 #define STM_ADC_ISR_EOC         2
1108 #define STM_ADC_ISR_EOSMP       1
1109 #define STM_ADC_ISR_ADRDY       0
1110
1111 #define STM_ADC_IER_AWDIE       7
1112 #define STM_ADC_IER_OVRIE       4
1113 #define STM_ADC_IER_EOSEQIE     3
1114 #define STM_ADC_IER_EOCIE       2
1115 #define STM_ADC_IER_EOSMPIE     1
1116 #define STM_ADC_IER_ADRDYIE     0
1117
1118 #define STM_ADC_CR_ADCAL        31
1119 #define STM_ADC_CR_ADSTP        4
1120 #define STM_ADC_CR_ADSTART      2
1121 #define STM_ADC_CR_ADDIS        1
1122 #define STM_ADC_CR_ADEN         0
1123
1124 #define STM_ADC_CFGR1_AWDCH     26
1125 #define STM_ADC_CFGR1_AWDEN     23
1126 #define STM_ADC_CFGR1_AWDSGL    22
1127 #define STM_ADC_CFGR1_DISCEN    16
1128 #define STM_ADC_CFGR1_AUTOOFF   15
1129 #define STM_ADC_CFGR1_WAIT      14
1130 #define STM_ADC_CFGR1_CONT      13
1131 #define STM_ADC_CFGR1_OVRMOD    12
1132 #define STM_ADC_CFGR1_EXTEN     10
1133 #define  STM_ADC_CFGR1_EXTEN_DISABLE    0
1134 #define  STM_ADC_CFGR1_EXTEN_RISING     1
1135 #define  STM_ADC_CFGR1_EXTEN_FALLING    2
1136 #define  STM_ADC_CFGR1_EXTEN_BOTH       3
1137 #define  STM_ADC_CFGR1_EXTEN_MASK       3UL
1138
1139 #define STM_ADC_CFGR1_EXTSEL    6
1140 #define STM_ADC_CFGR1_ALIGN     5
1141 #define STM_ADC_CFGR1_RES       3
1142 #define  STM_ADC_CFGR1_RES_12           0
1143 #define  STM_ADC_CFGR1_RES_10           1
1144 #define  STM_ADC_CFGR1_RES_8            2
1145 #define  STM_ADC_CFGR1_RES_6            3
1146 #define  STM_ADC_CFGR1_RES_MASK         3UL
1147 #define STM_ADC_CFGR1_SCANDIR   2
1148 #define  STM_ADC_CFGR1_SCANDIR_UP       0
1149 #define  STM_ADC_CFGR1_SCANDIR_DOWN     1
1150 #define STM_ADC_CFGR1_DMACFG    1
1151 #define  STM_ADC_CFGR1_DMACFG_ONESHOT   0
1152 #define  STM_ADC_CFGR1_DMACFG_CIRCULAR  1
1153 #define STM_ADC_CFGR1_DMAEN     0
1154
1155 #define STM_ADC_CFGR2_CKMODE    30
1156 #define  STM_ADC_CFGR2_CKMODE_ADCCLK    0
1157 #define  STM_ADC_CFGR2_CKMODE_PCLK_2    1
1158 #define  STM_ADC_CFGR2_CKMODE_PCLK_4    2
1159
1160 #define STM_ADC_SMPR_SMP        0
1161 #define  STM_ADC_SMPR_SMP_1_5           0
1162 #define  STM_ADC_SMPR_SMP_7_5           1
1163 #define  STM_ADC_SMPR_SMP_13_5          2
1164 #define  STM_ADC_SMPR_SMP_28_5          3
1165 #define  STM_ADC_SMPR_SMP_41_5          4
1166 #define  STM_ADC_SMPR_SMP_55_5          5
1167 #define  STM_ADC_SMPR_SMP_71_5          6
1168 #define  STM_ADC_SMPR_SMP_239_5         7
1169
1170 #define STM_ADC_TR_HT           16
1171 #define STM_ADC_TR_LT           0
1172
1173 #define STM_ADC_CCR_VBATEN      24
1174 #define STM_ADC_CCR_TSEN        23
1175 #define STM_ADC_CCR_VREFEN      22
1176
1177 struct stm_cal {
1178         uint16_t        ts_cal_cold;    /* 30°C */
1179         uint16_t        vrefint_cal;
1180         uint16_t        unused_c0;
1181         uint16_t        ts_cal_hot;     /* 110°C */
1182 };
1183
1184 extern struct stm_cal   stm_cal;
1185
1186 #define stm_temp_cal_cold       30
1187 #define stm_temp_cal_hot        110
1188
1189 struct stm_dbgmcu {
1190         uint32_t        idcode;
1191 };
1192
1193 extern struct stm_dbgmcu        stm_dbgmcu;
1194
1195 static inline uint16_t
1196 stm_dev_id(void) {
1197         return stm_dbgmcu.idcode & 0xfff;
1198 }
1199
1200 struct stm_flash_size {
1201         uint16_t        f_size;
1202 };
1203
1204 extern struct stm_flash_size    stm_flash_size_04x;
1205
1206 /* Returns flash size in bytes */
1207 extern uint32_t
1208 stm_flash_size(void);
1209
1210 struct stm_device_id {
1211         uint32_t        u_id0;
1212         uint32_t        u_id1;
1213         uint32_t        u_id2;
1214 };
1215
1216 extern struct stm_device_id     stm_device_id;
1217
1218 #define STM_NUM_I2C     2
1219
1220 #define STM_I2C_INDEX(channel)  ((channel) - 1)
1221
1222 struct stm_i2c {
1223         vuint32_t       cr1;
1224         vuint32_t       cr2;
1225         vuint32_t       oar1;
1226         vuint32_t       oar2;
1227         vuint32_t       dr;
1228         vuint32_t       sr1;
1229         vuint32_t       sr2;
1230         vuint32_t       ccr;
1231         vuint32_t       trise;
1232 };
1233
1234 extern struct stm_i2c stm_i2c1, stm_i2c2;
1235
1236 #define STM_I2C_CR1_SWRST       15
1237 #define STM_I2C_CR1_ALERT       13
1238 #define STM_I2C_CR1_PEC         12
1239 #define STM_I2C_CR1_POS         11
1240 #define STM_I2C_CR1_ACK         10
1241 #define STM_I2C_CR1_STOP        9
1242 #define STM_I2C_CR1_START       8
1243 #define STM_I2C_CR1_NOSTRETCH   7
1244 #define STM_I2C_CR1_ENGC        6
1245 #define STM_I2C_CR1_ENPEC       5
1246 #define STM_I2C_CR1_ENARP       4
1247 #define STM_I2C_CR1_SMBTYPE     3
1248 #define STM_I2C_CR1_SMBUS       1
1249 #define STM_I2C_CR1_PE          0
1250
1251 #define STM_I2C_CR2_LAST        12
1252 #define STM_I2C_CR2_DMAEN       11
1253 #define STM_I2C_CR2_ITBUFEN     10
1254 #define STM_I2C_CR2_ITEVTEN     9
1255 #define STM_I2C_CR2_ITERREN     8
1256 #define STM_I2C_CR2_FREQ        0
1257 #define  STM_I2C_CR2_FREQ_2_MHZ         2
1258 #define  STM_I2C_CR2_FREQ_4_MHZ         4
1259 #define  STM_I2C_CR2_FREQ_8_MHZ         8
1260 #define  STM_I2C_CR2_FREQ_16_MHZ        16
1261 #define  STM_I2C_CR2_FREQ_32_MHZ        32
1262 #define  STM_I2C_CR2_FREQ_MASK          0x3fUL
1263
1264 #define STM_I2C_SR1_SMBALERT    15
1265 #define STM_I2C_SR1_TIMEOUT     14
1266 #define STM_I2C_SR1_PECERR      12
1267 #define STM_I2C_SR1_OVR         11
1268 #define STM_I2C_SR1_AF          10
1269 #define STM_I2C_SR1_ARLO        9
1270 #define STM_I2C_SR1_BERR        8
1271 #define STM_I2C_SR1_TXE         7
1272 #define STM_I2C_SR1_RXNE        6
1273 #define STM_I2C_SR1_STOPF       4
1274 #define STM_I2C_SR1_ADD10       3
1275 #define STM_I2C_SR1_BTF         2
1276 #define STM_I2C_SR1_ADDR        1
1277 #define STM_I2C_SR1_SB          0
1278
1279 #define STM_I2C_SR2_PEC         8
1280 #define  STM_I2C_SR2_PEC_MASK   0xff00UL
1281 #define STM_I2C_SR2_DUALF       7
1282 #define STM_I2C_SR2_SMBHOST     6
1283 #define STM_I2C_SR2_SMBDEFAULT  5
1284 #define STM_I2C_SR2_GENCALL     4
1285 #define STM_I2C_SR2_TRA         2
1286 #define STM_I2C_SR2_BUSY        1
1287 #define STM_I2C_SR2_MSL         0
1288
1289 #define STM_I2C_CCR_FS          15
1290 #define STM_I2C_CCR_DUTY        14
1291 #define STM_I2C_CCR_CCR         0
1292 #define  STM_I2C_CCR_MASK       0x7ffUL
1293
1294 struct stm_tim1 {
1295         vuint32_t       cr1;
1296         vuint32_t       cr2;
1297         vuint32_t       smcr;
1298         vuint32_t       dier;
1299
1300         vuint32_t       sr;
1301         vuint32_t       egr;
1302         vuint32_t       ccmr1;
1303         vuint32_t       ccmr2;
1304
1305         vuint32_t       ccer;
1306         vuint32_t       cnt;
1307         vuint32_t       psc;
1308         vuint32_t       arr;
1309
1310         vuint32_t       rcr;
1311         vuint32_t       ccr1;
1312         vuint32_t       ccr2;
1313         vuint32_t       ccr3;
1314
1315         vuint32_t       ccr4;
1316         vuint32_t       bdtr;
1317         vuint32_t       dcr;
1318         vuint32_t       dmar;
1319 };
1320
1321 #define STM_TIM1_CR1_CKD        8
1322 #define  STM_TIM1_CR1_CKD_1             0
1323 #define  STM_TIM1_CR1_CKD_2             1
1324 #define  STM_TIM1_CR1_CKD_4             2
1325
1326 #define STM_TIM1_CR1_ARPE       7
1327
1328 #define STM_TIM1_CR1_CMS        5
1329 #define  STM_TIM1_CR1_CMS_EDGE          0
1330 #define  STM_TIM1_CR1_CMS_CENTER_1      1
1331 #define  STM_TIM1_CR1_CMS_CENTER_2      2
1332 #define  STM_TIM1_CR1_CMS_CENTER_3      3
1333
1334 #define STM_TIM1_CR1_DIR        4
1335 #define  STM_TIM1_CR1_DIR_UP            0
1336 #define  STM_TIM1_CR1_DIR_DOWn          1
1337 #define STM_TIM1_CR1_OPM        3
1338 #define STM_TIM1_CR1_URS        2
1339 #define STM_TIM1_CR1_UDIS       1
1340 #define STM_TIM1_CR1_CEN        0
1341
1342 #define STM_TIM1_CR2_OIS4       14
1343 #define STM_TIM1_CR2_OIS3N      13
1344 #define STM_TIM1_CR2_OIS3       12
1345 #define STM_TIM1_CR2_OIS2N      11
1346 #define STM_TIM1_CR2_OIS2       10
1347 #define STM_TIM1_CR2_OIS1N      9
1348 #define STM_TIM1_CR2_OSI1       8
1349 #define STM_TIM1_CR2_TI1S       7
1350 #define STM_TIM1_CR2_MMS        4
1351 #define  STM_TIM1_CR2_MMS_RESET                 0
1352 #define  STM_TIM1_CR2_MMS_ENABLE                1
1353 #define  STM_TIM1_CR2_MMS_UPDATE                2
1354 #define  STM_TIM1_CR2_MMS_COMPARE_PULSE         3
1355 #define  STM_TIM1_CR2_MMS_COMPARE_OC1REF        4
1356 #define  STM_TIM1_CR2_MMS_COMPARE_OC2REF        5
1357 #define  STM_TIM1_CR2_MMS_COMPARE_OC3REF        6
1358 #define  STM_TIM1_CR2_MMS_COMPARE_OC4REF        7
1359 #define STM_TIM1_CR2_CCDS       3
1360 #define STM_TIM1_CR2_CCUS       2
1361 #define STM_TIM1_CR2_CCPC       0
1362
1363 #define STM_TIM1_SMCR_ETP       15
1364 #define STM_TIM1_SMCR_ECE       14
1365 #define STM_TIM1_SMCR_ETPS      12
1366 #define  STM_TIM1_SMCR_ETPS_OFF         0
1367 #define  STM_TIM1_SMCR_ETPS_DIV_2       1
1368 #define  STM_TIM1_SMCR_ETPS_DIV_4       2
1369 #define  STM_TIM1_SMCR_ETPS_DIV_8       3
1370
1371 #define STM_TIM1_SMCR_ETF       8
1372 #define  STM_TIM1_SMCR_ETF_NONE         0
1373 #define  STM_TIM1_SMCR_ETF_DIV_1_N_2    1
1374 #define  STM_TIM1_SMCR_ETF_DIV_1_N_4    2
1375 #define  STM_TIM1_SMCR_ETF_DIV_1_N_8    3
1376 #define  STM_TIM1_SMCR_ETF_DIV_2_N_6    4
1377 #define  STM_TIM1_SMCR_ETF_DIV_2_N_8    5
1378 #define  STM_TIM1_SMCR_ETF_DIV_4_N_6    6
1379 #define  STM_TIM1_SMCR_ETF_DIV_4_N_8    7
1380 #define  STM_TIM1_SMCR_ETF_DIV_8_N_6    8
1381 #define  STM_TIM1_SMCR_ETF_DIV_8_N_8    9
1382 #define  STM_TIM1_SMCR_ETF_DIV_16_N_5   10
1383 #define  STM_TIM1_SMCR_ETF_DIV_16_N_6   11
1384 #define  STM_TIM1_SMCR_ETF_DIV_16_N_8   12
1385 #define  STM_TIM1_SMCR_ETF_DIV_32_N_5   13
1386 #define  STM_TIM1_SMCR_ETF_DIV_32_N_6   14
1387 #define  STM_TIM1_SMCR_ETF_DIV_32_N_8   15
1388
1389 #define STM_TIM1_SMCR_MSM       7
1390 #define STM_TIM1_SMCR_TS        4
1391 #define  STM_TIM1_SMCR_TS_ITR0          0
1392 #define  STM_TIM1_SMCR_TS_ITR1          1
1393 #define  STM_TIM1_SMCR_TS_ITR2          2
1394 #define  STM_TIM1_SMCR_TS_ITR3          3
1395 #define  STM_TIM1_SMCR_TS_TI1F_ED       4
1396 #define  STM_TIM1_SMCR_TS_TI1FP1        5
1397 #define  STM_TIM1_SMCR_TS_TI2FP2        6
1398 #define  STM_TIM1_SMCR_TS_ETRF          7
1399
1400 #define STM_TIM1_SMCR_OCCS      3
1401 #define STM_TIM1_SMCR_SMS       0
1402 #define  STM_TIM1_SMCR_SMS_DISABLE      0
1403 #define  STM_TIM1_SMCR_SMS_ENCODER_1    1
1404 #define  STM_TIM1_SMCR_SMS_ENCODER_2    2
1405 #define  STM_TIM1_SMCR_SMS_ENCODER_3    3
1406 #define  STM_TIM1_SMCR_SMS_RESET        4
1407 #define  STM_TIM1_SMCR_SMS_GATED        5
1408 #define  STM_TIM1_SMCR_SMS_TRIGGER      6
1409 #define  STM_TIM1_SMCR_SMS_EXTERNAL     7
1410
1411 #define STM_TIM1_DIER_TDE       14
1412 #define STM_TIM1_DIER_COMDE     13
1413 #define STM_TIM1_DIER_CC4DE     12
1414 #define STM_TIM1_DIER_CC3DE     11
1415 #define STM_TIM1_DIER_CC2DE     10
1416 #define STM_TIM1_DIER_CC1DE     9
1417 #define STM_TIM1_DIER_UDE       8
1418 #define STM_TIM1_DIER_BIE       7
1419 #define STM_TIM1_DIER_TIE       6
1420 #define STM_TIM1_DIER_COMIE     5
1421 #define STM_TIM1_DIER_CC4IE     4
1422 #define STM_TIM1_DIER_CC3IE     3
1423 #define STM_TIM1_DIER_CC2IE     2
1424 #define STM_TIM1_DIER_CC1IE     1
1425 #define STM_TIM1_DIER_UIE       0
1426
1427 #define STM_TIM1_SR_CC4OF       12
1428 #define STM_TIM1_SR_CC3OF       11
1429 #define STM_TIM1_SR_CC2OF       10
1430 #define STM_TIM1_SR_CC1OF       9
1431 #define STM_TIM1_SR_BIF         7
1432 #define STM_TIM1_SR_TIF         6
1433 #define STM_TIM1_SR_COMIF       5
1434 #define STM_TIM1_SR_CC4IF       4
1435 #define STM_TIM1_SR_CC3IF       3
1436 #define STM_TIM1_SR_CC2IF       2
1437 #define STM_TIM1_SR_CC1IF       1
1438 #define STM_TIM1_SR_UIF         0
1439
1440 #define STM_TIM1_EGR_BG         7
1441 #define STM_TIM1_EGR_TG         6
1442 #define STM_TIM1_EGR_COMG       5
1443 #define STM_TIM1_EGR_CC4G       4
1444 #define STM_TIM1_EGR_CC3G       3
1445 #define STM_TIM1_EGR_CC2G       2
1446 #define STM_TIM1_EGR_CC1G       1
1447 #define STM_TIM1_EGR_UG         0
1448
1449 #define STM_TIM1_CCMR1_OC2CE    15
1450 #define STM_TIM1_CCMR1_OC2M     12
1451 #define STM_TIM1_CCMR1_OC2PE    11
1452 #define STM_TIM1_CCMR1_OC2FE    10
1453 #define STM_TIM1_CCMR1_CC2S     8
1454 #define STM_TIM1_CCMR1_OC1CE    7
1455 #define STM_TIM1_CCMR1_OC1M     4
1456 #define  STM_TIM1_CCMR_OCM_FROZEN               0
1457 #define  STM_TIM1_CCMR_OCM_1_HIGH_MATCH         1
1458 #define  STM_TIM1_CCMR_OCM_1_LOW_MATCH          2
1459 #define  STM_TIM1_CCMR_OCM_TOGGLE               3
1460 #define  STM_TIM1_CCMR_OCM_FORCE_LOW            4
1461 #define  STM_TIM1_CCMR_OCM_FORCE_HIGH           5
1462 #define  STM_TIM1_CCMR_OCM_PWM_MODE_1           6
1463 #define  STM_TIM1_CCMR_OCM_PWM_MODE_2           7
1464
1465 #define STM_TIM1_CCMR1_OC1PE    3
1466 #define STM_TIM1_CCMR1_OC1FE    2
1467 #define STM_TIM1_CCMR1_CC1S     0
1468 #define  STM_TIM1_CCMR_CCS_OUTPUT       0
1469 #define  STM_TIM1_CCMR_CCS_INPUT_TI1    1
1470 #define  STM_TIM1_CCMR_CCS_INPUT_TI2    2
1471 #define  STM_TIM1_CCMR_CCS_INPUT_TRC    3
1472
1473 #define STM_TIM1_CCMR1_IC2F     12
1474 #define STM_TIM1_CCMR1_IC2PSC   10
1475 #define STM_TIM1_CCMR1_CC2S     8
1476 #define STM_TIM1_CCMR1_IC1F     4
1477 #define  STM_TIM1_CCMR1_IC1F_NONE       0
1478 #define  STM_TIM1_CCMR1_IC1F_DIV_1_N_2  1
1479 #define  STM_TIM1_CCMR1_IC1F_DIV_1_N_4  2
1480 #define  STM_TIM1_CCMR1_IC1F_DIV_1_N_8  3
1481 #define  STM_TIM1_CCMR1_IC1F_DIV_2_N_6  4
1482 #define  STM_TIM1_CCMR1_IC1F_DIV_2_N_8  5
1483 #define  STM_TIM1_CCMR1_IC1F_DIV_4_N_6  6
1484 #define  STM_TIM1_CCMR1_IC1F_DIV_4_N_8  7
1485 #define  STM_TIM1_CCMR1_IC1F_DIV_8_N_6  8
1486 #define  STM_TIM1_CCMR1_IC1F_DIV_8_N_8  9
1487 #define  STM_TIM1_CCMR1_IC1F_DIV_16_N_5 10
1488 #define  STM_TIM1_CCMR1_IC1F_DIV_16_N_6 11
1489 #define  STM_TIM1_CCMR1_IC1F_DIV_16_N_8 12
1490 #define  STM_TIM1_CCMR1_IC1F_DIV_32_N_5 13
1491 #define  STM_TIM1_CCMR1_IC1F_DIV_32_N_6 14
1492 #define  STM_TIM1_CCMR1_IC1F_DIV_32_N_8 15
1493
1494 #define STM_TIM1_CCMR1_IC1PSC   2
1495 #define  STM_TIM1_CCMR1_IC1PSC_NONE     0
1496 #define  STM_TIM1_CCMR1_IC1PSC_2        1
1497 #define  STM_TIM1_CCMR1_IC1PSC_4        2
1498 #define  STM_TIM1_CCMR1_IC1PSC_8        3
1499
1500 #define STM_TIM1_CCMR1_CC1S     0
1501 #define  STM_TIM1_CCMR1_CC1S_OUTPUT     0
1502 #define  STM_TIM1_CCMR1_CC1S_TI1        1
1503 #define  STM_TIM1_CCMR1_CC1S_TI2        2
1504 #define  STM_TIM1_CCMR1_CC1S_TRC        3
1505
1506 #define STM_TIM1_CCMR2_OC4CE    15
1507 #define STM_TIM1_CCMR2_OC4M     12
1508 #define STM_TIM1_CCMR2_OC4PE    11
1509 #define STM_TIM1_CCMR2_OC4FE    10
1510 #define STM_TIM1_CCMR2_CC4S     8
1511 #define  STM_TIM1_CCMR2_CCS_OUTPUT      0
1512 #define  STM_TIM1_CCMR2_CCS_INPUT_TI3   1
1513 #define  STM_TIM1_CCMR2_CCS_INPUT_TI4   2
1514 #define  STM_TIM1_CCMR2_CCS_INPUT_TRC   3
1515 #define STM_TIM1_CCMR2_OC3CE    7
1516 #define STM_TIM1_CCMR2_OC3M     4
1517 #define STM_TIM1_CCMR2_OC3PE    3
1518 #define STM_TIM1_CCMR2_OC3FE    2
1519 #define STM_TIM1_CCMR2_CC3S     0
1520
1521 #define STM_TIM1_CCMR2_IC4F     12
1522 #define STM_TIM1_CCMR2_IC2PSC   10
1523 #define STM_TIM1_CCMR2_CC4S     8
1524 #define STM_TIM1_CCMR2_IC3F     4
1525 #define  STM_TIM1_CCMR2_IC1F_NONE       0
1526 #define  STM_TIM1_CCMR2_IC1F_DIV_1_N_2  1
1527 #define  STM_TIM1_CCMR2_IC1F_DIV_1_N_4  2
1528 #define  STM_TIM1_CCMR2_IC1F_DIV_1_N_8  3
1529 #define  STM_TIM1_CCMR2_IC1F_DIV_2_N_6  4
1530 #define  STM_TIM1_CCMR2_IC1F_DIV_2_N_8  5
1531 #define  STM_TIM1_CCMR2_IC1F_DIV_4_N_6  6
1532 #define  STM_TIM1_CCMR2_IC1F_DIV_4_N_8  7
1533 #define  STM_TIM1_CCMR2_IC1F_DIV_8_N_6  8
1534 #define  STM_TIM1_CCMR2_IC1F_DIV_8_N_8  9
1535 #define  STM_TIM1_CCMR2_IC1F_DIV_16_N_5 10
1536 #define  STM_TIM1_CCMR2_IC1F_DIV_16_N_6 11
1537 #define  STM_TIM1_CCMR2_IC1F_DIV_16_N_8 12
1538 #define  STM_TIM1_CCMR2_IC1F_DIV_32_N_5 13
1539 #define  STM_TIM1_CCMR2_IC1F_DIV_32_N_6 14
1540 #define  STM_TIM1_CCMR2_IC1F_DIV_32_N_8 15
1541
1542 #define STM_TIM1_CCER_CC4P      13
1543 #define STM_TIM1_CCER_CC4E      12
1544 #define STM_TIM1_CCER_CC3NP     11
1545 #define STM_TIM1_CCER_CC3NE     10
1546 #define STM_TIM1_CCER_CC3P      9
1547 #define STM_TIM1_CCER_CC3E      8
1548 #define STM_TIM1_CCER_CC2NP     7
1549 #define STM_TIM1_CCER_CC2NE     6
1550 #define STM_TIM1_CCER_CC2P      5
1551 #define STM_TIM1_CCER_CC2E      4
1552 #define STM_TIM1_CCER_CC1BP     3
1553 #define STM_TIM1_CCER_CC1NE     2
1554 #define STM_TIM1_CCER_CC1P      1
1555 #define STM_TIM1_CCER_CC1E      0
1556
1557 #define STM_TIM1_BDTR_MOE       15
1558 #define STM_TIM1_BDTR_AOE       14
1559 #define STM_TIM1_BDTR_BKP       13
1560 #define STM_TIM1_BDTR_BKE       12
1561 #define STM_TIM1_BDTR_OSSR      11
1562 #define STM_TIM1_BDTR_OSSI      10
1563 #define STM_TIM1_BDTR_LOCK      8
1564 #define  STM_TIM1_BDTR_LOCK_OFF         0
1565 #define  STM_TIM1_BDTR_LOCK_LEVEL_1     1
1566 #define  STM_TIM1_BDTR_LOCK_LEVEL_2     2
1567 #define  STM_TIM1_BDTR_LOCK_LEVEL_3     3
1568
1569 #define STM_TIM1_BDTR_DTG       0
1570
1571 #define STM_TIM1_DCR_DBL        8
1572 #define STM_TIM1_DCR_DBA        0
1573
1574 extern struct stm_tim1 stm_tim1;
1575
1576 #define stm_tim1        (*(struct stm_tim1 *)0x40012c00)
1577
1578 struct stm_tim23 {
1579         vuint32_t       cr1;
1580         vuint32_t       cr2;
1581         vuint32_t       smcr;
1582         vuint32_t       dier;
1583
1584         vuint32_t       sr;
1585         vuint32_t       egr;
1586         vuint32_t       ccmr1;
1587         vuint32_t       ccmr2;
1588
1589         vuint32_t       ccer;
1590         vuint32_t       cnt;
1591         vuint32_t       psc;
1592         vuint32_t       arr;
1593
1594         uint32_t        reserved_30;
1595         vuint32_t       ccr1;
1596         vuint32_t       ccr2;
1597         vuint32_t       ccr3;
1598
1599         vuint32_t       ccr4;
1600         uint32_t        reserved_44;
1601         vuint32_t       dcr;
1602         vuint32_t       dmar;
1603 };
1604
1605 extern struct stm_tim23 stm_tim2, stm_tim3;
1606
1607 #define stm_tim3        (*(struct stm_tim23 *) 0x40000400)
1608 #define stm_tim2        (*(struct stm_tim23 *) 0x40000000)
1609
1610 #define STM_TIM23_CR1_CKD       8
1611 #define  STM_TIM23_CR1_CKD_1            0
1612 #define  STM_TIM23_CR1_CKD_2            1
1613 #define  STM_TIM23_CR1_CKD_4            2
1614 #define  STM_TIM23_CR1_CKD_MASK 3UL
1615 #define STM_TIM23_CR1_ARPE      7
1616 #define STM_TIM23_CR1_CMS       5
1617 #define  STM_TIM23_CR1_CMS_EDGE         0
1618 #define  STM_TIM23_CR1_CMS_CENTER_1     1
1619 #define  STM_TIM23_CR1_CMS_CENTER_2     2
1620 #define  STM_TIM23_CR1_CMS_CENTER_3     3
1621 #define  STM_TIM23_CR1_CMS_MASK         3UL
1622 #define STM_TIM23_CR1_DIR       4
1623 #define  STM_TIM23_CR1_DIR_UP           0
1624 #define  STM_TIM23_CR1_DIR_DOWN         1
1625 #define STM_TIM23_CR1_OPM       3
1626 #define STM_TIM23_CR1_URS       2
1627 #define STM_TIM23_CR1_UDIS      1
1628 #define STM_TIM23_CR1_CEN       0
1629
1630 #define STM_TIM23_CR2_TI1S      7
1631 #define STM_TIM23_CR2_MMS       4
1632 #define  STM_TIM23_CR2_MMS_RESET                0
1633 #define  STM_TIM23_CR2_MMS_ENABLE               1
1634 #define  STM_TIM23_CR2_MMS_UPDATE               2
1635 #define  STM_TIM23_CR2_MMS_COMPARE_PULSE        3
1636 #define  STM_TIM23_CR2_MMS_COMPARE_OC1REF       4
1637 #define  STM_TIM23_CR2_MMS_COMPARE_OC2REF       5
1638 #define  STM_TIM23_CR2_MMS_COMPARE_OC3REF       6
1639 #define  STM_TIM23_CR2_MMS_COMPARE_OC4REF       7
1640 #define  STM_TIM23_CR2_MMS_MASK                 7UL
1641 #define STM_TIM23_CR2_CCDS      3
1642
1643 #define STM_TIM23_SMCR_ETP      15
1644 #define STM_TIM23_SMCR_ECE      14
1645 #define STM_TIM23_SMCR_ETPS     12
1646 #define  STM_TIM23_SMCR_ETPS_OFF                0
1647 #define  STM_TIM23_SMCR_ETPS_DIV_2              1
1648 #define  STM_TIM23_SMCR_ETPS_DIV_4              2
1649 #define  STM_TIM23_SMCR_ETPS_DIV_8              3
1650 #define  STM_TIM23_SMCR_ETPS_MASK               3UL
1651 #define STM_TIM23_SMCR_ETF      8
1652 #define  STM_TIM23_SMCR_ETF_NONE                0
1653 #define  STM_TIM23_SMCR_ETF_INT_N_2             1
1654 #define  STM_TIM23_SMCR_ETF_INT_N_4             2
1655 #define  STM_TIM23_SMCR_ETF_INT_N_8             3
1656 #define  STM_TIM23_SMCR_ETF_DTS_2_N_6           4
1657 #define  STM_TIM23_SMCR_ETF_DTS_2_N_8           5
1658 #define  STM_TIM23_SMCR_ETF_DTS_4_N_6           6
1659 #define  STM_TIM23_SMCR_ETF_DTS_4_N_8           7
1660 #define  STM_TIM23_SMCR_ETF_DTS_8_N_6           8
1661 #define  STM_TIM23_SMCR_ETF_DTS_8_N_8           9
1662 #define  STM_TIM23_SMCR_ETF_DTS_16_N_5          10
1663 #define  STM_TIM23_SMCR_ETF_DTS_16_N_6          11
1664 #define  STM_TIM23_SMCR_ETF_DTS_16_N_8          12
1665 #define  STM_TIM23_SMCR_ETF_DTS_32_N_5          13
1666 #define  STM_TIM23_SMCR_ETF_DTS_32_N_6          14
1667 #define  STM_TIM23_SMCR_ETF_DTS_32_N_8          15
1668 #define  STM_TIM23_SMCR_ETF_MASK                15
1669 #define STM_TIM23_SMCR_MSM      7
1670 #define STM_TIM23_SMCR_TS       4
1671 #define  STM_TIM23_SMCR_TS_ITR0                 0
1672 #define  STM_TIM23_SMCR_TS_ITR1                 1
1673 #define  STM_TIM23_SMCR_TS_ITR2                 2
1674 #define  STM_TIM23_SMCR_TS_ITR3                 3
1675 #define  STM_TIM23_SMCR_TS_TI1F_ED              4
1676 #define  STM_TIM23_SMCR_TS_TI1FP1               5
1677 #define  STM_TIM23_SMCR_TS_TI2FP2               6
1678 #define  STM_TIM23_SMCR_TS_ETRF                 7
1679 #define  STM_TIM23_SMCR_TS_MASK                 7
1680 #define STM_TIM23_SMCR_OCCS     3
1681 #define STM_TIM23_SMCR_SMS      0
1682 #define  STM_TIM23_SMCR_SMS_DISABLE             0
1683 #define  STM_TIM23_SMCR_SMS_ENCODER_MODE_1      1
1684 #define  STM_TIM23_SMCR_SMS_ENCODER_MODE_2      2
1685 #define  STM_TIM23_SMCR_SMS_ENCODER_MODE_3      3
1686 #define  STM_TIM23_SMCR_SMS_RESET_MODE          4
1687 #define  STM_TIM23_SMCR_SMS_GATED_MODE          5
1688 #define  STM_TIM23_SMCR_SMS_TRIGGER_MODE        6
1689 #define  STM_TIM23_SMCR_SMS_EXTERNAL_CLOCK      7
1690 #define  STM_TIM23_SMCR_SMS_MASK                7
1691
1692 #define STM_TIM23_SR_CC4OF      12
1693 #define STM_TIM23_SR_CC3OF      11
1694 #define STM_TIM23_SR_CC2OF      10
1695 #define STM_TIM23_SR_CC1OF      9
1696 #define STM_TIM23_SR_TIF        6
1697 #define STM_TIM23_SR_CC4IF      4
1698 #define STM_TIM23_SR_CC3IF      3
1699 #define STM_TIM23_SR_CC2IF      2
1700 #define STM_TIM23_SR_CC1IF      1
1701 #define STM_TIM23_SR_UIF        0
1702
1703 #define STM_TIM23_EGR_TG        6
1704 #define STM_TIM23_EGR_CC4G      4
1705 #define STM_TIM23_EGR_CC3G      3
1706 #define STM_TIM23_EGR_CC2G      2
1707 #define STM_TIM23_EGR_CC1G      1
1708 #define STM_TIM23_EGR_UG        0
1709
1710 #define STM_TIM23_CCMR1_OC2CE   15
1711 #define STM_TIM23_CCMR1_OC2M    12
1712 #define  STM_TIM23_CCMR1_OC2M_FROZEN                    0
1713 #define  STM_TIM23_CCMR1_OC2M_SET_HIGH_ON_MATCH         1
1714 #define  STM_TIM23_CCMR1_OC2M_SET_LOW_ON_MATCH          2
1715 #define  STM_TIM23_CCMR1_OC2M_TOGGLE                    3
1716 #define  STM_TIM23_CCMR1_OC2M_FORCE_LOW                 4
1717 #define  STM_TIM23_CCMR1_OC2M_FORCE_HIGH                5
1718 #define  STM_TIM23_CCMR1_OC2M_PWM_MODE_1                6
1719 #define  STM_TIM23_CCMR1_OC2M_PWM_MODE_2                7
1720 #define  STM_TIM23_CCMR1_OC2M_MASK                      7
1721 #define STM_TIM23_CCMR1_OC2PE   11
1722 #define STM_TIM23_CCMR1_OC2FE   10
1723 #define STM_TIM23_CCMR1_CC2S    8
1724 #define  STM_TIM23_CCMR1_CC2S_OUTPUT                    0
1725 #define  STM_TIM23_CCMR1_CC2S_INPUT_TI2                 1
1726 #define  STM_TIM23_CCMR1_CC2S_INPUT_TI1                 2
1727 #define  STM_TIM23_CCMR1_CC2S_INPUT_TRC                 3
1728 #define  STM_TIM23_CCMR1_CC2S_MASK                      3
1729
1730 #define STM_TIM23_CCMR1_OC1CE   7
1731 #define STM_TIM23_CCMR1_OC1M    4
1732 #define  STM_TIM23_CCMR1_OC1M_FROZEN                    0
1733 #define  STM_TIM23_CCMR1_OC1M_SET_HIGH_ON_MATCH         1
1734 #define  STM_TIM23_CCMR1_OC1M_SET_LOW_ON_MATCH          2
1735 #define  STM_TIM23_CCMR1_OC1M_TOGGLE                    3
1736 #define  STM_TIM23_CCMR1_OC1M_FORCE_LOW                 4
1737 #define  STM_TIM23_CCMR1_OC1M_FORCE_HIGH                5
1738 #define  STM_TIM23_CCMR1_OC1M_PWM_MODE_1                6
1739 #define  STM_TIM23_CCMR1_OC1M_PWM_MODE_2                7
1740 #define  STM_TIM23_CCMR1_OC1M_MASK                      7
1741 #define STM_TIM23_CCMR1_OC1PE   11
1742 #define STM_TIM23_CCMR1_OC1FE   2
1743 #define STM_TIM23_CCMR1_CC1S    0
1744 #define  STM_TIM23_CCMR1_CC1S_OUTPUT                    0
1745 #define  STM_TIM23_CCMR1_CC1S_INPUT_TI1                 1
1746 #define  STM_TIM23_CCMR1_CC1S_INPUT_TI2                 2
1747 #define  STM_TIM23_CCMR1_CC1S_INPUT_TRC                 3
1748 #define  STM_TIM23_CCMR1_CC1S_MASK                      3
1749
1750 #define STM_TIM23_CCMR2_OC4CE   15
1751 #define STM_TIM23_CCMR2_OC4M    12
1752 #define  STM_TIM23_CCMR2_OC4M_FROZEN                    0
1753 #define  STM_TIM23_CCMR2_OC4M_SET_HIGH_ON_MATCH 1
1754 #define  STM_TIM23_CCMR2_OC4M_SET_LOW_ON_MATCH          2
1755 #define  STM_TIM23_CCMR2_OC4M_TOGGLE                    3
1756 #define  STM_TIM23_CCMR2_OC4M_FORCE_LOW                 4
1757 #define  STM_TIM23_CCMR2_OC4M_FORCE_HIGH                5
1758 #define  STM_TIM23_CCMR2_OC4M_PWM_MODE_1                6
1759 #define  STM_TIM23_CCMR2_OC4M_PWM_MODE_2                7
1760 #define  STM_TIM23_CCMR2_OC4M_MASK                      7
1761 #define STM_TIM23_CCMR2_OC4PE   11
1762 #define STM_TIM23_CCMR2_OC4FE   10
1763 #define STM_TIM23_CCMR2_CC4S    8
1764 #define  STM_TIM23_CCMR2_CC4S_OUTPUT                    0
1765 #define  STM_TIM23_CCMR2_CC4S_INPUT_TI4                 1
1766 #define  STM_TIM23_CCMR2_CC4S_INPUT_TI3                 2
1767 #define  STM_TIM23_CCMR2_CC4S_INPUT_TRC                 3
1768 #define  STM_TIM23_CCMR2_CC4S_MASK                      3
1769
1770 #define STM_TIM23_CCMR2_OC3CE   7
1771 #define STM_TIM23_CCMR2_OC3M    4
1772 #define  STM_TIM23_CCMR2_OC3M_FROZEN                    0
1773 #define  STM_TIM23_CCMR2_OC3M_SET_HIGH_ON_MATCH         1
1774 #define  STM_TIM23_CCMR2_OC3M_SET_LOW_ON_MATCH          2
1775 #define  STM_TIM23_CCMR2_OC3M_TOGGLE                    3
1776 #define  STM_TIM23_CCMR2_OC3M_FORCE_LOW                 4
1777 #define  STM_TIM23_CCMR2_OC3M_FORCE_HIGH                5
1778 #define  STM_TIM23_CCMR2_OC3M_PWM_MODE_1                6
1779 #define  STM_TIM23_CCMR2_OC3M_PWM_MODE_2                7
1780 #define  STM_TIM23_CCMR2_OC3M_MASK                      7
1781 #define STM_TIM23_CCMR2_OC3PE   11
1782 #define STM_TIM23_CCMR2_OC3FE   2
1783 #define STM_TIM23_CCMR2_CC3S    0
1784 #define  STM_TIM23_CCMR2_CC3S_OUTPUT                    0
1785 #define  STM_TIM23_CCMR2_CC3S_INPUT_TI3                 1
1786 #define  STM_TIM23_CCMR2_CC3S_INPUT_TI4                 2
1787 #define  STM_TIM23_CCMR2_CC3S_INPUT_TRC                 3
1788 #define  STM_TIM23_CCMR2_CC3S_MASK                      3
1789
1790 #define STM_TIM23_CCER_CC4NP    15
1791 #define STM_TIM23_CCER_CC4P     13
1792 #define STM_TIM23_CCER_CC4E     12
1793 #define STM_TIM23_CCER_CC3NP    11
1794 #define STM_TIM23_CCER_CC3P     9
1795 #define STM_TIM23_CCER_CC3E     8
1796 #define STM_TIM23_CCER_CC2NP    7
1797 #define STM_TIM23_CCER_CC2P     5
1798 #define STM_TIM23_CCER_CC2E     4
1799 #define STM_TIM23_CCER_CC1NP    3
1800 #define STM_TIM23_CCER_CC1P     1
1801 #define STM_TIM23_CCER_CC1E     0
1802
1803 struct stm_usb {
1804         struct {
1805                 vuint16_t       r;
1806                 uint16_t        _;
1807         } epr[8];
1808         uint8_t         reserved_20[0x40 - 0x20];
1809         vuint16_t       cntr;
1810         uint16_t        reserved_42;
1811         vuint16_t       istr;
1812         uint16_t        reserved_46;
1813         vuint16_t       fnr;
1814         uint16_t        reserved_4a;
1815         vuint16_t       daddr;
1816         uint16_t        reserved_4e;
1817         vuint16_t       btable;
1818         uint16_t        reserved_52;
1819         vuint16_t       lpmcsr;
1820         uint16_t        reserved_56;
1821         vuint16_t       bcdr;
1822         uint16_t        reserved_5a;
1823 };
1824
1825 extern struct stm_usb stm_usb;
1826
1827 #define STM_USB_EPR_CTR_RX      15
1828 #define  STM_USB_EPR_CTR_RX_WRITE_INVARIANT             1
1829 #define STM_USB_EPR_DTOG_RX     14
1830 #define STM_USB_EPR_SW_BUF_TX   14
1831 #define STM_USB_EPR_DTOG_RX_WRITE_INVARIANT             0
1832 #define STM_USB_EPR_STAT_RX     12
1833 #define  STM_USB_EPR_STAT_RX_DISABLED                   0
1834 #define  STM_USB_EPR_STAT_RX_STALL                      1
1835 #define  STM_USB_EPR_STAT_RX_NAK                        2
1836 #define  STM_USB_EPR_STAT_RX_VALID                      3
1837 #define  STM_USB_EPR_STAT_RX_MASK                       3
1838 #define  STM_USB_EPR_STAT_RX_WRITE_INVARIANT            0
1839 #define STM_USB_EPR_SETUP       11
1840 #define STM_USB_EPR_EP_TYPE     9
1841 #define  STM_USB_EPR_EP_TYPE_BULK                       0
1842 #define  STM_USB_EPR_EP_TYPE_CONTROL                    1
1843 #define  STM_USB_EPR_EP_TYPE_ISO                        2
1844 #define  STM_USB_EPR_EP_TYPE_INTERRUPT                  3
1845 #define  STM_USB_EPR_EP_TYPE_MASK                       3
1846 #define STM_USB_EPR_EP_KIND     8
1847 #define  STM_USB_EPR_EP_KIND_SNGL_BUF                   0       /* Bulk */
1848 #define  STM_USB_EPR_EP_KIND_DBL_BUF                    1       /* Bulk */
1849 #define  STM_USB_EPR_EP_KIND_NO_STATUS_OUT              0       /* Control */
1850 #define  STM_USB_EPR_EP_KIND_STATUS_OUT                 1       /* Control */
1851 #define STM_USB_EPR_CTR_TX      7
1852 #define  STM_USB_CTR_TX_WRITE_INVARIANT                 1
1853 #define STM_USB_EPR_DTOG_TX     6
1854 #define STM_USB_EPR_SW_BUF_RX   6
1855 #define  STM_USB_EPR_DTOG_TX_WRITE_INVARIANT            0
1856 #define STM_USB_EPR_STAT_TX     4
1857 #define  STM_USB_EPR_STAT_TX_DISABLED                   0
1858 #define  STM_USB_EPR_STAT_TX_STALL                      1
1859 #define  STM_USB_EPR_STAT_TX_NAK                        2
1860 #define  STM_USB_EPR_STAT_TX_VALID                      3
1861 #define  STM_USB_EPR_STAT_TX_WRITE_INVARIANT            0
1862 #define  STM_USB_EPR_STAT_TX_MASK                       3
1863 #define STM_USB_EPR_EA          0
1864 #define  STM_USB_EPR_EA_MASK                            0xf
1865
1866 #define STM_USB_CNTR_CTRM       15
1867 #define STM_USB_CNTR_PMAOVRM    14
1868 #define STM_USB_CNTR_ERRM       13
1869 #define STM_USB_CNTR_WKUPM      12
1870 #define STM_USB_CNTR_SUSPM      11
1871 #define STM_USB_CNTR_RESETM     10
1872 #define STM_USB_CNTR_SOFM       9
1873 #define STM_USB_CNTR_ESOFM      8
1874 #define STM_USB_CNTR_RESUME     4
1875 #define STM_USB_CNTR_FSUSP      3
1876 #define STM_USB_CNTR_LP_MODE    2
1877 #define STM_USB_CNTR_PDWN       1
1878 #define STM_USB_CNTR_FRES       0
1879
1880 #define STM_USB_ISTR_CTR        15
1881 #define STM_USB_ISTR_PMAOVR     14
1882 #define STM_USB_ISTR_ERR        13
1883 #define STM_USB_ISTR_WKUP       12
1884 #define STM_USB_ISTR_SUSP       11
1885 #define STM_USB_ISTR_RESET      10
1886 #define STM_USB_ISTR_SOF        9
1887 #define STM_USB_ISTR_ESOF       8
1888 #define STM_USB_L1REQ           7
1889 #define STM_USB_ISTR_DIR        4
1890 #define STM_USB_ISTR_EP_ID      0
1891 #define  STM_USB_ISTR_EP_ID_MASK                0xf
1892
1893 #define STM_USB_FNR_RXDP        15
1894 #define STM_USB_FNR_RXDM        14
1895 #define STM_USB_FNR_LCK         13
1896 #define STM_USB_FNR_LSOF        11
1897 #define  STM_USB_FNR_LSOF_MASK                  0x3
1898 #define STM_USB_FNR_FN          0
1899 #define  STM_USB_FNR_FN_MASK                    0x7ff
1900
1901 #define STM_USB_DADDR_EF        7
1902 #define STM_USB_DADDR_ADD       0
1903 #define  STM_USB_DADDR_ADD_MASK                 0x7f
1904
1905 #define STM_USB_BCDR_DPPU       15
1906 #define STM_USB_BCDR_PS2DET     7
1907 #define STM_USB_BCDR_SDET       6
1908 #define STM_USB_BCDR_PDET       5
1909 #define STM_USB_BCDR_DCDET      4
1910 #define STM_USB_BCDR_SDEN       3
1911 #define STM_USB_BCDR_PDEN       2
1912 #define STM_USB_BCDR_DCDEN      1
1913 #define STM_USB_BCDR_BCDEN      0
1914
1915 union stm_usb_bdt {
1916         struct {
1917                 vuint16_t       addr_tx;
1918                 vuint16_t       count_tx;
1919                 vuint16_t       addr_rx;
1920                 vuint16_t       count_rx;
1921         } single;
1922         struct {
1923                 vuint16_t       addr;
1924                 vuint16_t       count;
1925         } double_tx[2];
1926         struct {
1927                 vuint16_t       addr;
1928                 vuint16_t       count;
1929         } double_rx[2];
1930 };
1931
1932 #define STM_USB_BDT_COUNT_RX_BL_SIZE    15
1933 #define STM_USB_BDT_COUNT_RX_NUM_BLOCK  10
1934 #define  STM_USB_BDT_COUNT_RX_NUM_BLOCK_MASK    0x1f
1935 #define STM_USB_BDT_COUNT_RX_COUNT_RX   0
1936 #define  STM_USB_BDT_COUNT_RX_COUNT_RX_MASK     0x1ff
1937
1938 #define STM_USB_BDT_SIZE        8
1939
1940 /* We'll use the first block of usb SRAM for the BDT */
1941 extern uint8_t stm_usb_sram[] __attribute__((aligned(4)));
1942 extern union stm_usb_bdt stm_usb_bdt[STM_USB_BDT_SIZE] __attribute__((aligned(4)));
1943
1944 #define stm_usb_sram    ((uint8_t *) 0x40006000)
1945 #define stm_usb_bdt     ((union stm_usb_bdt *) 0x40006000)
1946
1947 struct stm_exti {
1948         vuint32_t       imr;
1949         vuint32_t       emr;
1950         vuint32_t       rtsr;
1951         vuint32_t       ftsr;
1952
1953         vuint32_t       swier;
1954         vuint32_t       pr;
1955 };
1956
1957 extern struct stm_exti stm_exti;
1958
1959 struct stm_usart {
1960         vuint32_t       cr1;    /* control register 1 */
1961         vuint32_t       cr2;    /* control register 2 */
1962         vuint32_t       cr3;    /* control register 3 */
1963         vuint32_t       brr;    /* baud rate register */
1964
1965         vuint32_t       gtpr;   /* guard time and prescaler */
1966         vuint32_t       rtor;   /* receiver timeout register */
1967         vuint32_t       rqr;    /* request register */
1968         vuint32_t       isr;    /* interrupt and status register */
1969
1970         vuint32_t       icr;    /* interrupt flag clear register */
1971         vuint32_t       rdr;    /* receive data register */
1972         vuint32_t       tdr;    /* transmit data register */
1973 };
1974
1975 #define STM_USART_CR1_M1        28
1976 #define STM_USART_CR1_EOBIE     27
1977 #define STM_USART_CR1_RTOIE     26
1978 #define STM_USART_CR1_DEAT      21
1979 #define STM_USART_CR1_DEDT      16
1980 #define STM_USART_CR1_OVER8     15
1981 #define STM_USART_CR1_CMIE      14
1982 #define STM_USART_CR1_MME       13
1983 #define STM_USART_CR1_M0        12
1984 #define STM_USART_CR1_WAKE      11
1985 #define STM_USART_CR1_PCE       10
1986 #define STM_USART_CR1_PS        9
1987 #define STM_USART_CR1_PEIE      8
1988 #define STM_USART_CR1_TXEIE     7
1989 #define STM_USART_CR1_TCIE      6
1990 #define STM_USART_CR1_RXNEIE    5
1991 #define STM_USART_CR1_IDLEIE    4
1992 #define STM_USART_CR1_TE        3
1993 #define STM_USART_CR1_RE        2
1994 #define STM_USART_CR1_UESM      1
1995 #define STM_USART_CR1_UE        0
1996
1997 #define STM_USART_CR2_ADD       24
1998 #define STM_USART_CR2_RTOEN     23
1999 #define STM_USART_CR2_ABRMOD    21
2000 #define STM_USART_CR2_ABREN     20
2001 #define STM_USART_CR2_MSBFIRST  19
2002 #define STM_USART_CR2_DATAINV   18
2003 #define STM_USART_CR2_TXINV     17
2004 #define STM_USART_CR2_RXINV     16
2005 #define STM_USART_CR2_SWAP      15
2006 #define STM_USART_CR2_LINEN     14
2007 #define STM_USART_CR2_STOP      12
2008 #define STM_USART_CR2_CLKEN     11
2009 #define STM_USART_CR2_CPOL      10
2010 #define STM_USART_CR2_CHPA      9
2011 #define STM_USART_CR2_LBCL      8
2012 #define STM_USART_CR2_LBDIE     6
2013 #define STM_USART_CR2_LBDL      5
2014 #define STM_USART_CR2_ADDM7     4
2015
2016 #define STM_USART_CR3_WUFIE     22
2017 #define STM_USART_CR3_WUS       20
2018 #define STM_USART_CR3_SCARCNT   17
2019 #define STM_USART_CR3_DEP       15
2020 #define STM_USART_CR3_DEM       14
2021 #define STM_USART_CR3_DDRE      13
2022 #define STM_USART_CR3_OVRDIS    12
2023 #define STM_USART_CR3_ONEBIT    11
2024 #define STM_USART_CR3_CTIIE     10
2025 #define STM_USART_CR3_CTSE      9
2026 #define STM_USART_CR3_RTSE      8
2027 #define STM_USART_CR3_DMAT      7
2028 #define STM_USART_CR3_DMAR      6
2029 #define STM_USART_CR3_SCEN      5
2030 #define STM_USART_CR3_NACK      4
2031 #define STM_USART_CR3_HDSEL     3
2032 #define STM_USART_CR3_IRLP      2
2033 #define STM_USART_CR3_IREN      1
2034 #define STM_USART_CR3_EIE       0
2035
2036 #define STM_USART_GTPR_GT       8
2037 #define STM_USART_GTPR_PSC      0
2038
2039 #define STM_USART_RQR_TXFRQ     4
2040 #define STM_USART_RQR_RXFRQ     3
2041 #define STM_USART_RQR_MMRQ      2
2042 #define STM_USART_RQR_SBKRQ     1
2043 #define STM_USART_RQR_ABRRQ     0
2044
2045 #define STM_USART_ISR_REACK     22
2046 #define STM_USART_ISR_TEACK     21
2047 #define STM_USART_ISR_WUF       20
2048 #define STM_USART_ISR_RWU       19
2049 #define STM_USART_ISR_SBKF      18
2050 #define STM_USART_ISR_CMF       17
2051 #define STM_USART_ISR_BUSY      16
2052 #define STM_USART_ISR_ABRF      15
2053 #define STM_USART_ISR_ABRE      14
2054 #define STM_USART_ISR_EOBF      12
2055 #define STM_USART_ISR_RTOF      11
2056 #define STM_USART_ISR_CTS       10
2057 #define STM_USART_ISR_CTSIF     9
2058 #define STM_USART_ISR_LBDF      8
2059 #define STM_USART_ISR_TXE       7
2060 #define STM_USART_ISR_TC        6
2061 #define STM_USART_ISR_RXNE      5
2062 #define STM_USART_ISR_IDLE      4
2063 #define STM_USART_ISR_ORE       3
2064 #define STM_USART_ISR_NF        2
2065 #define STM_USART_ISR_FE        1
2066 #define STM_USART_ISR_PE        0
2067
2068 #define STM_USART_ICR_WUCF      20
2069 #define STM_USART_ICR_CMCF      17
2070 #define STM_USART_ICR_EOBCF     12
2071 #define STM_USART_ICR_RTOCF     11
2072 #define STM_USART_ICR_CTSCF     9
2073 #define STM_USART_ICR_LBDCF     8
2074 #define STM_USART_ICR_TCCF      6
2075 #define STM_USART_ICR_IDLECF    4
2076 #define STM_USART_ICR_ORECF     3
2077 #define STM_USART_ICR_NCF       2
2078 #define STM_USART_ICR_FECF      1
2079 #define STM_USART_ICR_PECF      0
2080
2081 extern struct stm_usart stm_usart1;
2082 extern struct stm_usart stm_usart2;
2083
2084 #define isr_decl(name) \
2085         void stm_ ## name ## _isr(void)
2086
2087 isr_decl(halt);
2088 isr_decl(ignore);
2089 isr_decl(nmi);
2090 isr_decl(hardfault);
2091 isr_decl(memmanage);
2092 isr_decl(busfault);
2093 isr_decl(usagefault);
2094 isr_decl(svc);
2095 isr_decl(debugmon);
2096 isr_decl(pendsv);
2097 isr_decl(systick);
2098 isr_decl(wwdg);
2099 isr_decl(pvd);
2100 isr_decl(rtc);
2101 isr_decl(flash);
2102 isr_decl(rcc_crs);
2103 isr_decl(exti0_1);
2104 isr_decl(exti2_3);
2105 isr_decl(exti4_15);
2106 isr_decl(tsc);
2107 isr_decl(dma_ch1);
2108 isr_decl(dma_ch2_3);
2109 isr_decl(dma_ch4_5_6);
2110 isr_decl(adc_comp);
2111 isr_decl(tim1_brk_up_trg_com);
2112 isr_decl(tim1_cc);
2113 isr_decl(tim2);
2114 isr_decl(tim3);
2115 isr_decl(tim6_dac);
2116 isr_decl(tim7);
2117 isr_decl(tim14);
2118 isr_decl(tim15);
2119 isr_decl(tim16);
2120 isr_decl(tim17);
2121 isr_decl(i2c1);
2122 isr_decl(i2c2);
2123 isr_decl(spi1);
2124 isr_decl(spi2);
2125 isr_decl(usart1);
2126 isr_decl(usart2);
2127 isr_decl(usart3_4_5_6_7_8);
2128 isr_decl(cec_can);
2129 isr_decl(usb);
2130
2131 #endif /* _STM32F0_H_ */