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   1 /*
   2  * Copyright © 2015 Keith Packard <keithp@keithp.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; version 2 of the License.
   7  *
   8  * This program is distributed in the hope that it will be useful, but
   9  * WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  11  * General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along
  14  * with this program; if not, write to the Free Software Foundation, Inc.,
  15  * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  16  */
  17
  18 #ifndef _STM32F0_H_
  19 #define _STM32F0_H_
  20
  21 #include <stdint.h>
  22
  23 typedef volatile uint32_t       vuint32_t;
  24 typedef volatile void *         vvoid_t;
  25 typedef volatile uint16_t       vuint16_t;
  26
  27 struct stm_gpio {
  28         vuint32_t       moder;
  29         vuint32_t       otyper;
  30         vuint32_t       ospeedr;
  31         vuint32_t       pupdr;
  32
  33         vuint32_t       idr;
  34         vuint32_t       odr;
  35         vuint32_t       bsrr;
  36         vuint32_t       lckr;
  37
  38         vuint32_t       afrl;
  39         vuint32_t       afrh;
  40         vuint32_t       brr;
  41 };
  42
  43 #define STM_MODER_SHIFT(pin)            ((pin) << 1)
  44 #define STM_MODER_MASK                  3
  45 #define STM_MODER_INPUT                 0
  46 #define STM_MODER_OUTPUT                1
  47 #define STM_MODER_ALTERNATE             2
  48 #define STM_MODER_ANALOG                3
  49
  50 static inline void
  51 stm_moder_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
  52         gpio->moder = ((gpio->moder &
  53                         ~(STM_MODER_MASK << STM_MODER_SHIFT(pin))) |
  54                        value << STM_MODER_SHIFT(pin));
  55 }
  56
  57 static inline uint32_t
  58 stm_moder_get(struct stm_gpio *gpio, int pin) {
  59         return (gpio->moder >> STM_MODER_SHIFT(pin)) & STM_MODER_MASK;
  60 }
  61
  62 #define STM_OTYPER_SHIFT(pin)           (pin)
  63 #define STM_OTYPER_MASK                 1
  64 #define STM_OTYPER_PUSH_PULL            0
  65 #define STM_OTYPER_OPEN_DRAIN           1
  66
  67 static inline void
  68 stm_otyper_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
  69         gpio->otyper = ((gpio->otyper &
  70                          ~(STM_OTYPER_MASK << STM_OTYPER_SHIFT(pin))) |
  71                         value << STM_OTYPER_SHIFT(pin));
  72 }
  73
  74 static inline uint32_t
  75 stm_otyper_get(struct stm_gpio *gpio, int pin) {
  76         return (gpio->otyper >> STM_OTYPER_SHIFT(pin)) & STM_OTYPER_MASK;
  77 }
  78
  79 #define STM_OSPEEDR_SHIFT(pin)          ((pin) << 1)
  80 #define STM_OSPEEDR_MASK                3
  81 #define STM_OSPEEDR_LOW                 0       /* 2MHz */
  82 #define STM_OSPEEDR_MEDIUM              1       /* 10MHz */
  83 #define STM_OSPEEDR_HIGH                3       /* 10-50MHz */
  84
  85 static inline void
  86 stm_ospeedr_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
  87         gpio->ospeedr = ((gpio->ospeedr &
  88                         ~(STM_OSPEEDR_MASK << STM_OSPEEDR_SHIFT(pin))) |
  89                        value << STM_OSPEEDR_SHIFT(pin));
  90 }
  91
  92 static inline uint32_t
  93 stm_ospeedr_get(struct stm_gpio *gpio, int pin) {
  94         return (gpio->ospeedr >> STM_OSPEEDR_SHIFT(pin)) & STM_OSPEEDR_MASK;
  95 }
  96
  97 #define STM_PUPDR_SHIFT(pin)            ((pin) << 1)
  98 #define STM_PUPDR_MASK                  3
  99 #define STM_PUPDR_NONE                  0
 100 #define STM_PUPDR_PULL_UP               1
 101 #define STM_PUPDR_PULL_DOWN             2
 102 #define STM_PUPDR_RESERVED              3
 103
 104 static inline void
 105 stm_pupdr_set(struct stm_gpio *gpio, int pin, uint32_t value) {
 106         gpio->pupdr = ((gpio->pupdr &
 107                         ~(STM_PUPDR_MASK << STM_PUPDR_SHIFT(pin))) |
 108                        value << STM_PUPDR_SHIFT(pin));
 109 }
 110
 111 static inline uint32_t
 112 stm_pupdr_get(struct stm_gpio *gpio, int pin) {
 113         return (gpio->pupdr >> STM_PUPDR_SHIFT(pin)) & STM_PUPDR_MASK;
 114 }
 115
 116 #define STM_AFR_SHIFT(pin)              ((pin) << 2)
 117 #define STM_AFR_MASK                    0xf
 118 #define STM_AFR_NONE                    0
 119 #define STM_AFR_AF0                     0x0
 120 #define STM_AFR_AF1                     0x1
 121 #define STM_AFR_AF2                     0x2
 122 #define STM_AFR_AF3                     0x3
 123 #define STM_AFR_AF4                     0x4
 124 #define STM_AFR_AF5                     0x5
 125 #define STM_AFR_AF6                     0x6
 126 #define STM_AFR_AF7                     0x7
 127
 128 static inline void
 129 stm_afr_set(struct stm_gpio *gpio, int pin, uint32_t value) {
 130         /*
 131          * Set alternate pin mode too
 132          */
 133         stm_moder_set(gpio, pin, STM_MODER_ALTERNATE);
 134         if (pin < 8)
 135                 gpio->afrl = ((gpio->afrl &
 136                                ~(STM_AFR_MASK << STM_AFR_SHIFT(pin))) |
 137                               value << STM_AFR_SHIFT(pin));
 138         else {
 139                 pin -= 8;
 140                 gpio->afrh = ((gpio->afrh &
 141                                ~(STM_AFR_MASK << STM_AFR_SHIFT(pin))) |
 142                               value << STM_AFR_SHIFT(pin));
 143         }
 144 }
 145
 146 static inline uint32_t
 147 stm_afr_get(struct stm_gpio *gpio, int pin) {
 148         if (pin < 8)
 149                 return (gpio->afrl >> STM_AFR_SHIFT(pin)) & STM_AFR_MASK;
 150         else {
 151                 pin -= 8;
 152                 return (gpio->afrh >> STM_AFR_SHIFT(pin)) & STM_AFR_MASK;
 153         }
 154 }
 155
 156 static inline void
 157 stm_gpio_set(struct stm_gpio *gpio, int pin, uint8_t value) {
 158         /* Use the bit set/reset register to do this atomically */
 159         gpio->bsrr = ((uint32_t) (value ^ 1) << (pin + 16)) | ((uint32_t) value << pin);
 160 }
 161
 162 static inline uint8_t
 163 stm_gpio_get(struct stm_gpio *gpio, int pin) {
 164         return (gpio->idr >> pin) & 1;
 165 }
 166
 167 static inline uint16_t
 168 stm_gpio_get_all(struct stm_gpio *gpio) {
 169         return gpio->idr;
 170 }
 171
 172 /*
 173  * We can't define these in registers.ld or our fancy
 174  * ao_enable_gpio macro will expand into a huge pile of code
 175  * as the compiler won't do correct constant folding and
 176  * dead-code elimination
 177  */
 178
 179 extern struct stm_gpio stm_gpioa;
 180 extern struct stm_gpio stm_gpiob;
 181 extern struct stm_gpio stm_gpioc;
 182 extern struct stm_gpio stm_gpiof;
 183
 184 #define stm_gpiof  (*((struct stm_gpio *) 0x48001400))
 185 #define stm_gpioc  (*((struct stm_gpio *) 0x48000800))
 186 #define stm_gpiob  (*((struct stm_gpio *) 0x48000400))
 187 #define stm_gpioa  (*((struct stm_gpio *) 0x48000000))
 188
 189 struct stm_usart {
 190         vuint32_t       cr1;    /* control register 1 */
 191         vuint32_t       cr2;    /* control register 2 */
 192         vuint32_t       cr3;    /* control register 3 */
 193         vuint32_t       brr;    /* baud rate register */
 194
 195         vuint32_t       gtpr;   /* guard time and prescaler */
 196         vuint32_t       rtor;   /* */
 197         vuint32_t       rqr;    /* */
 198         vuint32_t       isr;    /* */
 199
 200         vuint32_t       icr;    /* */
 201         vuint32_t       rdr;    /* */
 202         vuint32_t       tdr;    /* */
 203 };
 204
 205 extern struct stm_usart stm_usart1;
 206 extern struct stm_usart stm_usart2;
 207
 208 #define STM_USART_SR_CTS        (9)     /* CTS flag */
 209 #define STM_USART_SR_LBD        (8)     /* LIN break detection flag */
 210 #define STM_USART_SR_TXE        (7)     /* Transmit data register empty */
 211 #define STM_USART_SR_TC         (6)     /* Transmission complete */
 212 #define STM_USART_SR_RXNE       (5)     /* Read data register not empty */
 213 #define STM_USART_SR_IDLE       (4)     /* IDLE line detected */
 214 #define STM_USART_SR_ORE        (3)     /* Overrun error */
 215 #define STM_USART_SR_NF         (2)     /* Noise detected flag */
 216 #define STM_USART_SR_FE         (1)     /* Framing error */
 217 #define STM_USART_SR_PE         (0)     /* Parity error */
 218
 219 #define STM_USART_CR1_OVER8     (15)    /* Oversampling mode */
 220 #define STM_USART_CR1_UE        (13)    /* USART enable */
 221 #define STM_USART_CR1_M         (12)    /* Word length */
 222 #define STM_USART_CR1_WAKE      (11)    /* Wakeup method */
 223 #define STM_USART_CR1_PCE       (10)    /* Parity control enable */
 224 #define STM_USART_CR1_PS        (9)     /* Parity selection */
 225 #define STM_USART_CR1_PEIE      (8)     /* PE interrupt enable */
 226 #define STM_USART_CR1_TXEIE     (7)     /* TXE interrupt enable */
 227 #define STM_USART_CR1_TCIE      (6)     /* Transmission complete interrupt enable */
 228 #define STM_USART_CR1_RXNEIE    (5)     /* RXNE interrupt enable */
 229 #define STM_USART_CR1_IDLEIE    (4)     /* IDLE interrupt enable */
 230 #define STM_USART_CR1_TE        (3)     /* Transmitter enable */
 231 #define STM_USART_CR1_RE        (2)     /* Receiver enable */
 232 #define STM_USART_CR1_RWU       (1)     /* Receiver wakeup */
 233 #define STM_USART_CR1_SBK       (0)     /* Send break */
 234
 235 #define STM_USART_CR2_LINEN     (14)    /* LIN mode enable */
 236 #define STM_USART_CR2_STOP      (12)    /* STOP bits */
 237 #define STM_USART_CR2_STOP_MASK 3
 238 #define STM_USART_CR2_STOP_1    0
 239 #define STM_USART_CR2_STOP_0_5  1
 240 #define STM_USART_CR2_STOP_2    2
 241 #define STM_USART_CR2_STOP_1_5  3
 242
 243 #define STM_USART_CR2_CLKEN     (11)    /* Clock enable */
 244 #define STM_USART_CR2_CPOL      (10)    /* Clock polarity */
 245 #define STM_USART_CR2_CPHA      (9)     /* Clock phase */
 246 #define STM_USART_CR2_LBCL      (8)     /* Last bit clock pulse */
 247 #define STM_USART_CR2_LBDIE     (6)     /* LIN break detection interrupt enable */
 248 #define STM_USART_CR2_LBDL      (5)     /* lin break detection length */
 249 #define STM_USART_CR2_ADD       (0)
 250 #define STM_USART_CR2_ADD_MASK  0xf
 251
 252 #define STM_USART_CR3_ONEBITE   (11)    /* One sample bit method enable */
 253 #define STM_USART_CR3_CTSIE     (10)    /* CTS interrupt enable */
 254 #define STM_USART_CR3_CTSE      (9)     /* CTS enable */
 255 #define STM_USART_CR3_RTSE      (8)     /* RTS enable */
 256 #define STM_USART_CR3_DMAT      (7)     /* DMA enable transmitter */
 257 #define STM_USART_CR3_DMAR      (6)     /* DMA enable receiver */
 258 #define STM_USART_CR3_SCEN      (5)     /* Smartcard mode enable */
 259 #define STM_USART_CR3_NACK      (4)     /* Smartcard NACK enable */
 260 #define STM_USART_CR3_HDSEL     (3)     /* Half-duplex selection */
 261 #define STM_USART_CR3_IRLP      (2)     /* IrDA low-power */
 262 #define STM_USART_CR3_IREN      (1)     /* IrDA mode enable */
 263 #define STM_USART_CR3_EIE       (0)     /* Error interrupt enable */
 264
 265 struct stm_tim {
 266 };
 267
 268 extern struct stm_tim stm_tim9;
 269
 270 struct stm_tim1011 {
 271         vuint32_t       cr1;
 272         uint32_t        unused_4;
 273         vuint32_t       smcr;
 274         vuint32_t       dier;
 275         vuint32_t       sr;
 276         vuint32_t       egr;
 277         vuint32_t       ccmr1;
 278         uint32_t        unused_1c;
 279         vuint32_t       ccer;
 280         vuint32_t       cnt;
 281         vuint32_t       psc;
 282         vuint32_t       arr;
 283         uint32_t        unused_30;
 284         vuint32_t       ccr1;
 285         uint32_t        unused_38;
 286         uint32_t        unused_3c;
 287         uint32_t        unused_40;
 288         uint32_t        unused_44;
 289         uint32_t        unused_48;
 290         uint32_t        unused_4c;
 291         vuint32_t       or;
 292 };
 293
 294 extern struct stm_tim1011 stm_tim10;
 295 extern struct stm_tim1011 stm_tim11;
 296
 297 #define STM_TIM1011_CR1_CKD     8
 298 #define  STM_TIM1011_CR1_CKD_1          0
 299 #define  STM_TIM1011_CR1_CKD_2          1
 300 #define  STM_TIM1011_CR1_CKD_4          2
 301 #define  STM_TIM1011_CR1_CKD_MASK       3
 302 #define STM_TIM1011_CR1_ARPE    7
 303 #define STM_TIM1011_CR1_URS     2
 304 #define STM_TIM1011_CR1_UDIS    1
 305 #define STM_TIM1011_CR1_CEN     0
 306
 307 #define STM_TIM1011_SMCR_ETP    15
 308 #define STM_TIM1011_SMCR_ECE    14
 309 #define STM_TIM1011_SMCR_ETPS   12
 310 #define  STM_TIM1011_SMCR_ETPS_OFF      0
 311 #define  STM_TIM1011_SMCR_ETPS_2        1
 312 #define  STM_TIM1011_SMCR_ETPS_4        2
 313 #define  STM_TIM1011_SMCR_ETPS_8        3
 314 #define  STM_TIM1011_SMCR_ETPS_MASK     3
 315 #define STM_TIM1011_SMCR_ETF    8
 316 #define  STM_TIM1011_SMCR_ETF_NONE              0
 317 #define  STM_TIM1011_SMCR_ETF_CK_INT_2          1
 318 #define  STM_TIM1011_SMCR_ETF_CK_INT_4          2
 319 #define  STM_TIM1011_SMCR_ETF_CK_INT_8          3
 320 #define  STM_TIM1011_SMCR_ETF_DTS_2_6           4
 321 #define  STM_TIM1011_SMCR_ETF_DTS_2_8           5
 322 #define  STM_TIM1011_SMCR_ETF_DTS_4_6           6
 323 #define  STM_TIM1011_SMCR_ETF_DTS_4_8           7
 324 #define  STM_TIM1011_SMCR_ETF_DTS_8_6           8
 325 #define  STM_TIM1011_SMCR_ETF_DTS_8_8           9
 326 #define  STM_TIM1011_SMCR_ETF_DTS_16_5          10
 327 #define  STM_TIM1011_SMCR_ETF_DTS_16_6          11
 328 #define  STM_TIM1011_SMCR_ETF_DTS_16_8          12
 329 #define  STM_TIM1011_SMCR_ETF_DTS_32_5          13
 330 #define  STM_TIM1011_SMCR_ETF_DTS_32_6          14
 331 #define  STM_TIM1011_SMCR_ETF_DTS_32_8          15
 332 #define  STM_TIM1011_SMCR_ETF_MASK              15
 333
 334 #define STM_TIM1011_DIER_CC1E   1
 335 #define STM_TIM1011_DIER_UIE    0
 336
 337 #define STM_TIM1011_SR_CC1OF    9
 338 #define STM_TIM1011_SR_CC1IF    1
 339 #define STM_TIM1011_SR_UIF      0
 340
 341 #define STM_TIM1011_EGR_CC1G    1
 342 #define STM_TIM1011_EGR_UG      0
 343
 344 #define STM_TIM1011_CCMR1_OC1CE 7
 345 #define STM_TIM1011_CCMR1_OC1M  4
 346 #define  STM_TIM1011_CCMR1_OC1M_FROZEN                  0
 347 #define  STM_TIM1011_CCMR1_OC1M_SET_1_ACTIVE_ON_MATCH   1
 348 #define  STM_TIM1011_CCMR1_OC1M_SET_1_INACTIVE_ON_MATCH 2
 349 #define  STM_TIM1011_CCMR1_OC1M_TOGGLE                  3
 350 #define  STM_TIM1011_CCMR1_OC1M_FORCE_INACTIVE          4
 351 #define  STM_TIM1011_CCMR1_OC1M_FORCE_ACTIVE            5
 352 #define  STM_TIM1011_CCMR1_OC1M_PWM_MODE_1              6
 353 #define  STM_TIM1011_CCMR1_OC1M_PWM_MODE_2              7
 354 #define  STM_TIM1011_CCMR1_OC1M_MASK                    7
 355 #define STM_TIM1011_CCMR1_OC1PE 3
 356 #define STM_TIM1011_CCMR1_OC1FE 2
 357 #define STM_TIM1011_CCMR1_CC1S  0
 358 #define  STM_TIM1011_CCMR1_CC1S_OUTPUT                  0
 359 #define  STM_TIM1011_CCMR1_CC1S_INPUT_TI1               1
 360 #define  STM_TIM1011_CCMR1_CC1S_INPUT_TI2               2
 361 #define  STM_TIM1011_CCMR1_CC1S_INPUT_TRC               3
 362 #define  STM_TIM1011_CCMR1_CC1S_MASK                    3
 363
 364 #define  STM_TIM1011_CCMR1_IC1F_NONE            0
 365 #define  STM_TIM1011_CCMR1_IC1F_CK_INT_2        1
 366 #define  STM_TIM1011_CCMR1_IC1F_CK_INT_4        2
 367 #define  STM_TIM1011_CCMR1_IC1F_CK_INT_8        3
 368 #define  STM_TIM1011_CCMR1_IC1F_DTS_2_6         4
 369 #define  STM_TIM1011_CCMR1_IC1F_DTS_2_8         5
 370 #define  STM_TIM1011_CCMR1_IC1F_DTS_4_6         6
 371 #define  STM_TIM1011_CCMR1_IC1F_DTS_4_8         7
 372 #define  STM_TIM1011_CCMR1_IC1F_DTS_8_6         8
 373 #define  STM_TIM1011_CCMR1_IC1F_DTS_8_8         9
 374 #define  STM_TIM1011_CCMR1_IC1F_DTS_16_5        10
 375 #define  STM_TIM1011_CCMR1_IC1F_DTS_16_6        11
 376 #define  STM_TIM1011_CCMR1_IC1F_DTS_16_8        12
 377 #define  STM_TIM1011_CCMR1_IC1F_DTS_32_5        13
 378 #define  STM_TIM1011_CCMR1_IC1F_DTS_32_6        14
 379 #define  STM_TIM1011_CCMR1_IC1F_DTS_32_8        15
 380 #define  STM_TIM1011_CCMR1_IC1F_MASK            15
 381 #define STM_TIM1011_CCMR1_IC1PSC        2
 382 #define  STM_TIM1011_CCMR1_IC1PSC_1             0
 383 #define  STM_TIM1011_CCMR1_IC1PSC_2             1
 384 #define  STM_TIM1011_CCMR1_IC1PSC_4             2
 385 #define  STM_TIM1011_CCMR1_IC1PSC_8             3
 386 #define  STM_TIM1011_CCMR1_IC1PSC_MASK          3
 387 #define STM_TIM1011_CCMR1_CC1S          0
 388
 389 #define STM_TIM1011_CCER_CC1NP          3
 390 #define STM_TIM1011_CCER_CC1P           1
 391 #define STM_TIM1011_CCER_CC1E           0
 392
 393 #define STM_TIM1011_OR_TI1_RMP_RI       3
 394 #define STM_TIM1011_ETR_RMP             2
 395 #define STM_TIM1011_TI1_RMP             0
 396 #define  STM_TIM1011_TI1_RMP_GPIO               0
 397 #define  STM_TIM1011_TI1_RMP_LSI                1
 398 #define  STM_TIM1011_TI1_RMP_LSE                2
 399 #define  STM_TIM1011_TI1_RMP_RTC                3
 400 #define  STM_TIM1011_TI1_RMP_MASK               3
 401
 402 /* Flash interface */
 403
 404 struct stm_flash {
 405         vuint32_t       acr;
 406         vuint32_t       keyr;
 407         vuint32_t       optkeyr;
 408         vuint32_t       sr;
 409
 410         vuint32_t       cr;
 411         vuint32_t       ar;
 412         vuint32_t       unused_0x18;
 413         vuint32_t       obr;
 414
 415         vuint32_t       wrpr;
 416 };
 417
 418 extern struct stm_flash stm_flash;
 419
 420 #define STM_FLASH_ACR_PRFTBS    (5)
 421 #define STM_FLASH_ACR_PRFTBE    (4)
 422 #define STM_FLASH_ACR_LATENCY   (0)
 423 #define  STM_FLASH_ACR_LATENCY_0                0
 424 #define  STM_FLASH_ACR_LATENCY_1                1
 425
 426 #define STM_FLASH_PECR_OBL_LAUNCH       18
 427 #define STM_FLASH_PECR_ERRIE            17
 428 #define STM_FLASH_PECR_EOPIE            16
 429 #define STM_FLASH_PECR_FPRG             10
 430 #define STM_FLASH_PECR_ERASE            9
 431 #define STM_FLASH_PECR_FTDW             8
 432 #define STM_FLASH_PECR_DATA             4
 433 #define STM_FLASH_PECR_PROG             3
 434 #define STM_FLASH_PECR_OPTLOCK          2
 435 #define STM_FLASH_PECR_PRGLOCK          1
 436 #define STM_FLASH_PECR_PELOCK           0
 437
 438 #define STM_FLASH_SR_EOP                5
 439 #define STM_FLASH_SR_WRPRTERR           4
 440 #define STM_FLASH_SR_PGERR              2
 441 #define STM_FLASH_SR_BSY                0
 442
 443 #define STM_FLASH_CR_OBL_LAUNCH         13
 444 #define STM_FLASH_CR_EOPIE              12
 445 #define STM_FLASH_CR_ERRIE              10
 446 #define STM_FLASH_CR_OPTWRE             9
 447 #define STM_FLASH_CR_LOCK               7
 448 #define STM_FLASH_CR_STRT               6
 449 #define STM_FLASH_CR_OPTER              5
 450 #define STM_FLASH_CR_OPTPG              4
 451 #define STM_FLASH_CR_MER                2
 452 #define STM_FLASH_CR_PER                1
 453 #define STM_FLASH_CR_PG                 0
 454
 455 #define STM_FLASH_OBR_DATA1             24
 456 #define STM_FLASH_OBR_DATA0             16
 457 #define STM_FLASH_OBR_BOOT_SEL          15
 458 #define STM_FLASH_OBR_RAM_PARITY_CHECK  14
 459 #define STM_FLASH_OBR_VDDA_MONITOR      13
 460 #define STM_FLASH_OBR_NBOOT1            12
 461 #define STM_FLASH_OBR_NBOOT0            11
 462 #define STM_FLASH_OBR_NRST_STDBY        10
 463 #define STM_FLASH_OBR_NRST_STOP         9
 464 #define STM_FLASH_OBR_WDG_SW            8
 465 #define STM_FLASH_OBR_RDPRT             1
 466 #define  STM_FLASH_OBR_RDPRT_LEVEL0             0
 467 #define  STM_FLASH_OBR_RDPRT_LEVEL1             1
 468 #define  STM_FLASH_OBR_RDPRT_LEVEL2             3
 469 #define STM_FLASH_OBR_OPTERR            0
 470
 471 #define STM_FLASH_KEYR_KEY1     0x45670123
 472 #define STM_FLASH_KEYR_KEY2     0xcdef89ab
 473
 474 struct stm_rcc {
 475         vuint32_t       cr;
 476         vuint32_t       cfgr;
 477         vuint32_t       cir;
 478         vuint32_t       apb2rstr;
 479
 480         vuint32_t       apb1rstr;
 481         vuint32_t       ahbenr;
 482         vuint32_t       apb2enr;
 483         vuint32_t       apb1enr;
 484
 485         vuint32_t       bdcr;
 486         vuint32_t       csr;
 487         vuint32_t       ahbrstr;
 488         vuint32_t       cfgr2;
 489
 490         vuint32_t       cfgr3;
 491         vuint32_t       cr2;
 492 };
 493
 494 extern struct stm_rcc stm_rcc;
 495
 496 /* Nominal high speed internal oscillator frequency is 16MHz */
 497 #define STM_HSI_FREQ            16000000
 498
 499 #define STM_RCC_CR_PLLRDY       (25)
 500 #define STM_RCC_CR_PLLON        (24)
 501 #define STM_RCC_CR_CSSON        (19)
 502 #define STM_RCC_CR_HSEBYP       (18)
 503 #define STM_RCC_CR_HSERDY       (17)
 504 #define STM_RCC_CR_HSEON        (16)
 505 #define STM_RCC_CR_HSICAL       (8)
 506 #define STM_RCC_CR_HSITRIM      (3)
 507 #define STM_RCC_CR_HSIRDY       (1)
 508 #define STM_RCC_CR_HSION        (0)
 509
 510 #define STM_RCC_CFGR_PLL_NODIV  (31)
 511 #define  STM_RCC_CFGR_PLL_NODIV_DIV_1   1
 512 #define  STM_RCC_CFGR_PLL_NODIV_DIV_2   0
 513
 514 #define STM_RCC_CFGR_MCOPRE     (28)
 515 #define  STM_RCC_CFGR_MCOPRE_DIV_1      0
 516 #define  STM_RCC_CFGR_MCOPRE_DIV_2      1
 517 #define  STM_RCC_CFGR_MCOPRE_DIV_4      2
 518 #define  STM_RCC_CFGR_MCOPRE_DIV_8      3
 519 #define  STM_RCC_CFGR_MCOPRE_DIV_16     4
 520 #define  STM_RCC_CFGR_MCOPRE_DIV_32     5
 521 #define  STM_RCC_CFGR_MCOPRE_DIV_64     6
 522 #define  STM_RCC_CFGR_MCOPRE_DIV_128    7
 523 #define  STM_RCC_CFGR_MCOPRE_DIV_MASK   7
 524
 525 #define STM_RCC_CFGR_MCO        (24)
 526 # define STM_RCC_CFGR_MCO_DISABLE       0
 527
 528 #define STM_RCC_CFGR_PLLMUL     (18)
 529 #define  STM_RCC_CFGR_PLLMUL_2          0
 530 #define  STM_RCC_CFGR_PLLMUL_3          1
 531 #define  STM_RCC_CFGR_PLLMUL_4          2
 532 #define  STM_RCC_CFGR_PLLMUL_5          3
 533 #define  STM_RCC_CFGR_PLLMUL_6          4
 534 #define  STM_RCC_CFGR_PLLMUL_7          5
 535 #define  STM_RCC_CFGR_PLLMUL_8          6
 536 #define  STM_RCC_CFGR_PLLMUL_9          7
 537 #define  STM_RCC_CFGR_PLLMUL_10         8
 538 #define  STM_RCC_CFGR_PLLMUL_11         9
 539 #define  STM_RCC_CFGR_PLLMUL_12         10
 540 #define  STM_RCC_CFGR_PLLMUL_13         11
 541 #define  STM_RCC_CFGR_PLLMUL_14         12
 542 #define  STM_RCC_CFGR_PLLMUL_15         13
 543 #define  STM_RCC_CFGR_PLLMUL_16         14
 544 #define  STM_RCC_CFGR_PLLMUL_MASK       0xf
 545
 546 #define STM_RCC_CFGR_PLLXTPRE   (17)
 547
 548 #define STM_RCC_CFGR_PLLSRC     (15)
 549 # define STM_RCC_CFGR_PLLSRC_HSI_DIV_2  0
 550 # define STM_RCC_CFGR_PLLSRC_HSI        1
 551 # define STM_RCC_CFGR_PLLSRC_HSE        2
 552 # define STM_RCC_CFGR_PLLSRC_HSI48      3
 553
 554 #define STM_RCC_CFGR_ADCPRE     (14)
 555
 556 #define STM_RCC_CFGR_PPRE       (8)
 557 #define  STM_RCC_CFGR_PPRE_DIV_1        0
 558 #define  STM_RCC_CFGR_PPRE_DIV_2        4
 559 #define  STM_RCC_CFGR_PPRE_DIV_4        5
 560 #define  STM_RCC_CFGR_PPRE_DIV_8        6
 561 #define  STM_RCC_CFGR_PPRE_DIV_16       7
 562 #define  STM_RCC_CFGR_PPRE_MASK         7
 563
 564 #define STM_RCC_CFGR_HPRE       (4)
 565 #define  STM_RCC_CFGR_HPRE_DIV_1        0
 566 #define  STM_RCC_CFGR_HPRE_DIV_2        8
 567 #define  STM_RCC_CFGR_HPRE_DIV_4        9
 568 #define  STM_RCC_CFGR_HPRE_DIV_8        0xa
 569 #define  STM_RCC_CFGR_HPRE_DIV_16       0xb
 570 #define  STM_RCC_CFGR_HPRE_DIV_64       0xc
 571 #define  STM_RCC_CFGR_HPRE_DIV_128      0xd
 572 #define  STM_RCC_CFGR_HPRE_DIV_256      0xe
 573 #define  STM_RCC_CFGR_HPRE_DIV_512      0xf
 574 #define  STM_RCC_CFGR_HPRE_MASK         0xf
 575
 576 #define STM_RCC_CFGR_SWS        (2)
 577 #define  STM_RCC_CFGR_SWS_HSI           0
 578 #define  STM_RCC_CFGR_SWS_HSE           1
 579 #define  STM_RCC_CFGR_SWS_PLL           2
 580 #define  STM_RCC_CFGR_SWS_HSI48         3
 581 #define  STM_RCC_CFGR_SWS_MASK          3
 582
 583 #define STM_RCC_CFGR_SW         (0)
 584 #define  STM_RCC_CFGR_SW_HSI            0
 585 #define  STM_RCC_CFGR_SW_HSE            1
 586 #define  STM_RCC_CFGR_SW_PLL            2
 587 #define  STM_RCC_CFGR_SW_HSI48          3
 588 #define  STM_RCC_CFGR_SW_MASK           3
 589
 590 #define STM_RCC_APB1RSTR_CECRST         30
 591 #define STM_RCC_APB1RSTR_DACRST         29
 592 #define STM_RCC_APB1RSTR_PWRRST         28
 593 #define STM_RCC_APB1RSTR_CRSRST         27
 594 #define STM_RCC_APB1RSTR_CANRST         25
 595 #define STM_RCC_APB1RSTR_USBRST         23
 596 #define STM_RCC_APB1RSTR_I2C2RST        22
 597 #define STM_RCC_APB1RSTR_I1C1RST        21
 598 #define STM_RCC_APB1RSTR_USART5RST      20
 599 #define STM_RCC_APB1RSTR_USART4RST      19
 600 #define STM_RCC_APB1RSTR_USART3RST      18
 601 #define STM_RCC_APB1RSTR_USART2RST      17
 602 #define STM_RCC_APB1RSTR_SPI2RST        14
 603 #define STM_RCC_APB1RSTR_WWDGRST        11
 604 #define STM_RCC_APB1RSTR_TIM14RST       8
 605 #define STM_RCC_APB1RSTR_TIM7RST        5
 606 #define STM_RCC_APB1RSTR_TIM6RST        4
 607 #define STM_RCC_APB1RSTR_TIM3RST        1
 608 #define STM_RCC_APB1RSTR_TIM2RST        0
 609
 610 #define STM_RCC_AHBENR_TSCEN    24
 611 #define STM_RCC_AHBENR_IOPFEN   22
 612 #define STM_RCC_AHBENR_IOPEEN   21
 613 #define STM_RCC_AHBENR_IOPDEN   20
 614 #define STM_RCC_AHBENR_IOPCEN   19
 615 #define STM_RCC_AHBENR_IOPBEN   18
 616 #define STM_RCC_AHBENR_IOPAEN   17
 617 #define STM_RCC_AHBENR_CRCEN    6
 618 #define STM_RCC_AHBENR_FLITFEN  4
 619 #define STM_RCC_AHBENR_SRAMEN   2
 620 #define STM_RCC_AHBENR_DMA2EN   1
 621 #define STM_RCC_AHBENR_DMAEM    0
 622
 623 #define STM_RCC_APB2ENR_DBGMCUEN        22
 624 #define STM_RCC_APB2ENR_TIM17EN         18
 625 #define STM_RCC_APB2ENR_TIM16EN         17
 626 #define STM_RCC_APB2ENR_TIM15EN         16
 627 #define STM_RCC_APB2ENR_USART1EN        14
 628 #define STM_RCC_APB2ENR_SPI1EN          12
 629 #define STM_RCC_APB2ENR_TIM1EN          11
 630 #define STM_RCC_APB2ENR_ADCEN           9
 631 #define STM_RCC_APB2ENR_USART8EN        7
 632 #define STM_RCC_APB2ENR_USART7EN        6
 633 #define STM_RCC_APB2ENR_USART6EN        5
 634 #define STM_RCC_APB2ENR_SYSCFGCOMPEN    0
 635
 636 #define STM_RCC_APB1ENR_CECEN           30
 637 #define STM_RCC_APB1ENR_DACEN           29
 638 #define STM_RCC_APB1ENR_PWREN           28
 639 #define STM_RCC_APB1ENR_CRSEN           27
 640 #define STM_RCC_APB1ENR_CANEN           25
 641 #define STM_RCC_APB1ENR_USBEN           23
 642 #define STM_RCC_APB1ENR_I2C2EN          22
 643 #define STM_RCC_APB1ENR_IC21EN          21
 644 #define STM_RCC_APB1ENR_USART5EN        20
 645 #define STM_RCC_APB1ENR_USART4EN        19
 646 #define STM_RCC_APB1ENR_USART3EN        18
 647 #define STM_RCC_APB1ENR_USART2EN        17
 648 #define STM_RCC_APB1ENR_SPI2EN          14
 649 #define STM_RCC_APB1ENR_WWDGEN          11
 650 #define STM_RCC_APB1ENR_TIM14EN         8
 651 #define STM_RCC_APB1ENR_TIM7EN          5
 652 #define STM_RCC_APB1ENR_TIM6EN          4
 653 #define STM_RCC_APB1ENR_TIM3EN          1
 654 #define STM_RCC_APB1ENR_TIM2EN          0
 655
 656 #define STM_RCC_CSR_LPWRRSTF            (31)
 657 #define STM_RCC_CSR_WWDGRSTF            (30)
 658 #define STM_RCC_CSR_IWDGRSTF            (29)
 659 #define STM_RCC_CSR_SFTRSTF             (28)
 660 #define STM_RCC_CSR_PORRSTF             (27)
 661 #define STM_RCC_CSR_PINRSTF             (26)
 662 #define STM_RCC_CSR_OBLRSTF             (25)
 663 #define STM_RCC_CSR_RMVF                (24)
 664 #define STM_RCC_CSR_V18PWRRSTF          (23)
 665 #define STM_RCC_CSR_LSIRDY              (1)
 666 #define STM_RCC_CSR_LSION               (0)
 667
 668 #define STM_RCC_CR2_HSI48CAL            24
 669 #define STM_RCC_CR2_HSI48RDY            17
 670 #define STM_RCC_CR2_HSI48ON             16
 671 #define STM_RCC_CR2_HSI14CAL            8
 672 #define STM_RCC_CR2_HSI14TRIM           3
 673 #define STM_RCC_CR2_HSI14DIS            2
 674 #define STM_RCC_CR2_HSI14RDY            1
 675 #define STM_RCC_CR2_HSI14ON             0
 676
 677 #define STM_RCC_CFGR3_USART3SW          18
 678 #define STM_RCC_CFGR3_USART2SW          16
 679 #define STM_RCC_CFGR3_ADCSW             8
 680 #define STM_RCC_CFGR3_USBSW             7
 681 #define STM_RCC_CFGR3_CECSW             6
 682 #define STM_RCC_CFGR3_I2C1SW            4
 683 #define STM_RCC_CFGR3_USART1SW          0
 684
 685 struct stm_crs {
 686         vuint32_t       cr;
 687         vuint32_t       cfgr;
 688         vuint32_t       isr;
 689         vuint32_t       icr;
 690 };
 691
 692 extern struct stm_crs stm_crs;
 693
 694 #define STM_CRS_CR_TRIM         8
 695 #define STM_CRS_CR_SWSYNC       7
 696 #define STM_CRS_CR_AUTOTRIMEN   6
 697 #define STM_CRS_CR_CEN          5
 698 #define STM_CRS_CR_ESYNCIE      3
 699 #define STM_CRS_CR_ERRIE        2
 700 #define STM_CRS_CR_SYNCWARNIE   1
 701 #define STM_CRS_CR_SYNCOKIE     0
 702
 703 #define STM_CRS_CFGR_SYNCPOL    31
 704 #define STM_CRS_CFGR_SYNCSRC    28
 705 #define  STM_CRS_CFGR_SYNCSRC_GPIO      0
 706 #define  STM_CRS_CFGR_SYNCSRC_LSE       1
 707 #define  STM_CRS_CFGR_SYNCSRC_USB       2
 708 #define STM_CRS_CFGR_SYNCDIV    24
 709 #define  STM_CRS_CFGR_SYNCDIV_1         0
 710 #define  STM_CRS_CFGR_SYNCDIV_2         1
 711 #define  STM_CRS_CFGR_SYNCDIV_4         2
 712 #define  STM_CRS_CFGR_SYNCDIV_8         3
 713 #define  STM_CRS_CFGR_SYNCDIV_16        4
 714 #define  STM_CRS_CFGR_SYNCDIV_32        5
 715 #define  STM_CRS_CFGR_SYNCDIV_64        6
 716 #define  STM_CRS_CFGR_SYNCDIV_128       7
 717 #define STM_CRS_CFGR_FELIM      16
 718 #define STM_CRS_CFGR_RELOAD     0
 719
 720 #define STM_CRS_ISR_FECAP       16
 721 #define STM_CRS_ISR_FEDIR       15
 722 #define STM_CRS_ISR_TRIMOVF     10
 723 #define STM_CRS_ISR_SYNCMISS    9
 724 #define STM_CRS_ISR_SYNCERR     8
 725 #define STM_CRS_ISR_ESYNCF      3
 726 #define STM_CRS_ISR_ERRF        2
 727 #define STM_CRS_ISR_SYNCWARNF   1
 728 #define STM_CRS_ISR_SYNCOKF     0
 729
 730 #define STM_CRS_ICR_ESYNCC      3
 731 #define STM_CRS_ICR_ERRC        2
 732 #define STM_CRS_ICR_SYNCWARNC   1
 733 #define STM_CRS_ICR_SYNCOKC     0
 734
 735 struct stm_pwr {
 736         vuint32_t       cr;
 737         vuint32_t       csr;
 738 };
 739
 740 extern struct stm_pwr stm_pwr;
 741
 742 #define STM_PWR_CR_DBP          (8)
 743
 744 #define STM_PWR_CR_PLS          (5)
 745 #define  STM_PWR_CR_PLS_2_0     0
 746 #define  STM_PWR_CR_PLS_2_1     1
 747 #define  STM_PWR_CR_PLS_2_2     2
 748 #define  STM_PWR_CR_PLS_2_3     3
 749 #define  STM_PWR_CR_PLS_2_4     4
 750 #define  STM_PWR_CR_PLS_2_5     5
 751 #define  STM_PWR_CR_PLS_2_6     6
 752 #define  STM_PWR_CR_PLS_EXT     7
 753 #define  STM_PWR_CR_PLS_MASK    7
 754
 755 #define STM_PWR_CR_PVDE         (4)
 756 #define STM_PWR_CR_CSBF         (3)
 757 #define STM_PWR_CR_CWUF         (2)
 758 #define STM_PWR_CR_PDDS         (1)
 759 #define STM_PWR_CR_LPSDSR       (0)
 760
 761 #define STM_PWR_CSR_EWUP3       (10)
 762 #define STM_PWR_CSR_EWUP2       (9)
 763 #define STM_PWR_CSR_EWUP1       (8)
 764 #define STM_PWR_CSR_REGLPF      (5)
 765 #define STM_PWR_CSR_VOSF        (4)
 766 #define STM_PWR_CSR_VREFINTRDYF (3)
 767 #define STM_PWR_CSR_PVDO        (2)
 768 #define STM_PWR_CSR_SBF         (1)
 769 #define STM_PWR_CSR_WUF         (0)
 770
 771 struct stm_tim67 {
 772         vuint32_t       cr1;
 773         vuint32_t       cr2;
 774         uint32_t        _unused_08;
 775         vuint32_t       dier;
 776
 777         vuint32_t       sr;
 778         vuint32_t       egr;
 779         uint32_t        _unused_18;
 780         uint32_t        _unused_1c;
 781
 782         uint32_t        _unused_20;
 783         vuint32_t       cnt;
 784         vuint32_t       psc;
 785         vuint32_t       arr;
 786 };
 787
 788 extern struct stm_tim67 stm_tim6;
 789
 790 #define STM_TIM67_CR1_ARPE      (7)
 791 #define STM_TIM67_CR1_OPM       (3)
 792 #define STM_TIM67_CR1_URS       (2)
 793 #define STM_TIM67_CR1_UDIS      (1)
 794 #define STM_TIM67_CR1_CEN       (0)
 795
 796 #define STM_TIM67_CR2_MMS       (4)
 797 #define  STM_TIM67_CR2_MMS_RESET        0
 798 #define  STM_TIM67_CR2_MMS_ENABLE       1
 799 #define  STM_TIM67_CR2_MMS_UPDATE       2
 800 #define  STM_TIM67_CR2_MMS_MASK         7
 801
 802 #define STM_TIM67_DIER_UDE      (8)
 803 #define STM_TIM67_DIER_UIE      (0)
 804
 805 #define STM_TIM67_SR_UIF        (0)
 806
 807 #define STM_TIM67_EGR_UG        (0)
 808
 809 struct stm_lcd {
 810         vuint32_t       cr;
 811         vuint32_t       fcr;
 812         vuint32_t       sr;
 813         vuint32_t       clr;
 814         uint32_t        unused_0x10;
 815         vuint32_t       ram[8*2];
 816 };
 817
 818 extern struct stm_lcd stm_lcd;
 819
 820 #define STM_LCD_CR_MUX_SEG              (7)
 821
 822 #define STM_LCD_CR_BIAS                 (5)
 823 #define  STM_LCD_CR_BIAS_1_4            0
 824 #define  STM_LCD_CR_BIAS_1_2            1
 825 #define  STM_LCD_CR_BIAS_1_3            2
 826 #define  STM_LCD_CR_BIAS_MASK           3
 827
 828 #define STM_LCD_CR_DUTY                 (2)
 829 #define  STM_LCD_CR_DUTY_STATIC         0
 830 #define  STM_LCD_CR_DUTY_1_2            1
 831 #define  STM_LCD_CR_DUTY_1_3            2
 832 #define  STM_LCD_CR_DUTY_1_4            3
 833 #define  STM_LCD_CR_DUTY_1_8            4
 834 #define  STM_LCD_CR_DUTY_MASK           7
 835
 836 #define STM_LCD_CR_VSEL                 (1)
 837 #define STM_LCD_CR_LCDEN                (0)
 838
 839 #define STM_LCD_FCR_PS                  (22)
 840 #define  STM_LCD_FCR_PS_1               0x0
 841 #define  STM_LCD_FCR_PS_2               0x1
 842 #define  STM_LCD_FCR_PS_4               0x2
 843 #define  STM_LCD_FCR_PS_8               0x3
 844 #define  STM_LCD_FCR_PS_16              0x4
 845 #define  STM_LCD_FCR_PS_32              0x5
 846 #define  STM_LCD_FCR_PS_64              0x6
 847 #define  STM_LCD_FCR_PS_128             0x7
 848 #define  STM_LCD_FCR_PS_256             0x8
 849 #define  STM_LCD_FCR_PS_512             0x9
 850 #define  STM_LCD_FCR_PS_1024            0xa
 851 #define  STM_LCD_FCR_PS_2048            0xb
 852 #define  STM_LCD_FCR_PS_4096            0xc
 853 #define  STM_LCD_FCR_PS_8192            0xd
 854 #define  STM_LCD_FCR_PS_16384           0xe
 855 #define  STM_LCD_FCR_PS_32768           0xf
 856 #define  STM_LCD_FCR_PS_MASK            0xf
 857
 858 #define STM_LCD_FCR_DIV                 (18)
 859 #define STM_LCD_FCR_DIV_16              0x0
 860 #define STM_LCD_FCR_DIV_17              0x1
 861 #define STM_LCD_FCR_DIV_18              0x2
 862 #define STM_LCD_FCR_DIV_19              0x3
 863 #define STM_LCD_FCR_DIV_20              0x4
 864 #define STM_LCD_FCR_DIV_21              0x5
 865 #define STM_LCD_FCR_DIV_22              0x6
 866 #define STM_LCD_FCR_DIV_23              0x7
 867 #define STM_LCD_FCR_DIV_24              0x8
 868 #define STM_LCD_FCR_DIV_25              0x9
 869 #define STM_LCD_FCR_DIV_26              0xa
 870 #define STM_LCD_FCR_DIV_27              0xb
 871 #define STM_LCD_FCR_DIV_28              0xc
 872 #define STM_LCD_FCR_DIV_29              0xd
 873 #define STM_LCD_FCR_DIV_30              0xe
 874 #define STM_LCD_FCR_DIV_31              0xf
 875 #define STM_LCD_FCR_DIV_MASK            0xf
 876
 877 #define STM_LCD_FCR_BLINK               (16)
 878 #define  STM_LCD_FCR_BLINK_DISABLE              0
 879 #define  STM_LCD_FCR_BLINK_SEG0_COM0            1
 880 #define  STM_LCD_FCR_BLINK_SEG0_COMALL          2
 881 #define  STM_LCD_FCR_BLINK_SEGALL_COMALL        3
 882 #define  STM_LCD_FCR_BLINK_MASK                 3
 883
 884 #define STM_LCD_FCR_BLINKF              (13)
 885 #define  STM_LCD_FCR_BLINKF_8                   0
 886 #define  STM_LCD_FCR_BLINKF_16                  1
 887 #define  STM_LCD_FCR_BLINKF_32                  2
 888 #define  STM_LCD_FCR_BLINKF_64                  3
 889 #define  STM_LCD_FCR_BLINKF_128                 4
 890 #define  STM_LCD_FCR_BLINKF_256                 5
 891 #define  STM_LCD_FCR_BLINKF_512                 6
 892 #define  STM_LCD_FCR_BLINKF_1024                7
 893 #define  STM_LCD_FCR_BLINKF_MASK                7
 894
 895 #define STM_LCD_FCR_CC                  (10)
 896 #define  STM_LCD_FCR_CC_MASK                    7
 897
 898 #define STM_LCD_FCR_DEAD                (7)
 899 #define  STM_LCD_FCR_DEAD_MASK                  7
 900
 901 #define STM_LCD_FCR_PON                 (4)
 902 #define  STM_LCD_FCR_PON_MASK                   7
 903
 904 #define STM_LCD_FCR_UDDIE               (3)
 905 #define STM_LCD_FCR_SOFIE               (1)
 906 #define STM_LCD_FCR_HD                  (0)
 907
 908 #define STM_LCD_SR_FCRSF                (5)
 909 #define STM_LCD_SR_RDY                  (4)
 910 #define STM_LCD_SR_UDD                  (3)
 911 #define STM_LCD_SR_UDR                  (2)
 912 #define STM_LCD_SR_SOF                  (1)
 913 #define STM_LCD_SR_ENS                  (0)
 914
 915 #define STM_LCD_CLR_UDDC                (3)
 916 #define STM_LCD_CLR_SOFC                (1)
 917
 918 /* The SYSTICK starts at 0xe000e010 */
 919
 920 struct stm_systick {
 921         vuint32_t       csr;
 922         vuint32_t       rvr;
 923         vuint32_t       cvr;
 924         vuint32_t       calib;
 925 };
 926
 927 extern struct stm_systick stm_systick;
 928
 929 #define STM_SYSTICK_CSR_ENABLE          0
 930 #define STM_SYSTICK_CSR_TICKINT         1
 931 #define STM_SYSTICK_CSR_CLKSOURCE       2
 932 #define  STM_SYSTICK_CSR_CLKSOURCE_EXTERNAL             0
 933 #define  STM_SYSTICK_CSR_CLKSOURCE_HCLK_8               1
 934 #define STM_SYSTICK_CSR_COUNTFLAG       16
 935
 936 /* The NVIC starts at 0xe000e100, so add that to the offsets to find the absolute address */
 937
 938 struct stm_nvic {
 939         vuint32_t       iser;           /* 0x000 0xe000e100 Set Enable Register */
 940
 941         uint8_t         _unused020[0x080 - 0x004];
 942
 943         vuint32_t       icer;           /* 0x080 0xe000e180 Clear Enable Register */
 944
 945         uint8_t         _unused0a0[0x100 - 0x084];
 946
 947         vuint32_t       ispr;           /* 0x100 0xe000e200 Set Pending Register */
 948
 949         uint8_t         _unused120[0x180 - 0x104];
 950
 951         vuint32_t       icpr;           /* 0x180 0xe000e280 Clear Pending Register */
 952
 953         uint8_t         _unused1a0[0x300 - 0x184];
 954
 955         vuint32_t       ipr[8];         /* 0x300 0xe000e400 Priority Register */
 956 };
 957
 958 extern struct stm_nvic stm_nvic;
 959
 960 #define IRQ_MASK(irq)   (1 << (irq))
 961 #define IRQ_BOOL(v,irq) (((v) >> (irq)) & 1)
 962
 963 static inline void
 964 stm_nvic_set_enable(int irq) {
 965         stm_nvic.iser = IRQ_MASK(irq);
 966 }
 967
 968 static inline void
 969 stm_nvic_clear_enable(int irq) {
 970         stm_nvic.icer = IRQ_MASK(irq);
 971 }
 972
 973 static inline int
 974 stm_nvic_enabled(int irq) {
 975         return IRQ_BOOL(stm_nvic.iser, irq);
 976 }
 977
 978 static inline void
 979 stm_nvic_set_pending(int irq) {
 980         stm_nvic.ispr = IRQ_MASK(irq);
 981 }
 982
 983 static inline void
 984 stm_nvic_clear_pending(int irq) {
 985         stm_nvic.icpr = IRQ_MASK(irq);
 986 }
 987
 988 static inline int
 989 stm_nvic_pending(int irq) {
 990         return IRQ_BOOL(stm_nvic.ispr, irq);
 991 }
 992
 993 #define IRQ_PRIO_REG(irq)       ((irq) >> 2)
 994 #define IRQ_PRIO_BIT(irq)       (((irq) & 3) << 3)
 995 #define IRQ_PRIO_MASK(irq)      (0xff << IRQ_PRIO_BIT(irq))
 996
 997 static inline void
 998 stm_nvic_set_priority(int irq, uint8_t prio) {
 999         int             n = IRQ_PRIO_REG(irq);
1000         uint32_t        v;
1001
1002         v = stm_nvic.ipr[n];
1003         v &= ~IRQ_PRIO_MASK(irq);
1004         v |= (prio) << IRQ_PRIO_BIT(irq);
1005         stm_nvic.ipr[n] = v;
1006 }
1007
1008 static inline uint8_t
1009 stm_nvic_get_priority(int irq) {
1010         return (stm_nvic.ipr[IRQ_PRIO_REG(irq)] >> IRQ_PRIO_BIT(irq)) & IRQ_PRIO_MASK(0);
1011 }
1012
1013 struct stm_scb {
1014         vuint32_t       cpuid;
1015         vuint32_t       icsr;
1016         vuint32_t       vtor;
1017         vuint32_t       aircr;
1018
1019         vuint32_t       scr;
1020         vuint32_t       ccr;
1021         vuint32_t       shpr1;
1022         vuint32_t       shpr2;
1023
1024         vuint32_t       shpr3;
1025         vuint32_t       shcrs;
1026         vuint32_t       cfsr;
1027         vuint32_t       hfsr;
1028
1029         uint32_t        unused_30;
1030         vuint32_t       mmfar;
1031         vuint32_t       bfar;
1032 };
1033
1034 extern struct stm_scb stm_scb;
1035
1036 #define STM_SCB_AIRCR_VECTKEY           16
1037 #define  STM_SCB_AIRCR_VECTKEY_KEY              0x05fa
1038 #define STM_SCB_AIRCR_PRIGROUP          8
1039 #define STM_SCB_AIRCR_SYSRESETREQ       2
1040 #define STM_SCB_AIRCR_VECTCLRACTIVE     1
1041 #define STM_SCB_AIRCR_VECTRESET         0
1042
1043 struct stm_mpu {
1044         vuint32_t       typer;
1045         vuint32_t       cr;
1046         vuint32_t       rnr;
1047         vuint32_t       rbar;
1048
1049         vuint32_t       rasr;
1050         vuint32_t       rbar_a1;
1051         vuint32_t       rasr_a1;
1052         vuint32_t       rbar_a2;
1053         vuint32_t       rasr_a2;
1054         vuint32_t       rbar_a3;
1055         vuint32_t       rasr_a3;
1056 };
1057
1058 extern struct stm_mpu stm_mpu;
1059
1060 #define STM_MPU_TYPER_IREGION   16
1061 #define  STM_MPU_TYPER_IREGION_MASK     0xff
1062 #define STM_MPU_TYPER_DREGION   8
1063 #define  STM_MPU_TYPER_DREGION_MASK     0xff
1064 #define STM_MPU_TYPER_SEPARATE  0
1065
1066 #define STM_MPU_CR_PRIVDEFENA   2
1067 #define STM_MPU_CR_HFNMIENA     1
1068 #define STM_MPU_CR_ENABLE       0
1069
1070 #define STM_MPU_RNR_REGION      0
1071 #define STM_MPU_RNR_REGION_MASK         0xff
1072
1073 #define STM_MPU_RBAR_ADDR       5
1074 #define STM_MPU_RBAR_ADDR_MASK          0x7ffffff
1075
1076 #define STM_MPU_RBAR_VALID      4
1077 #define STM_MPU_RBAR_REGION     0
1078 #define STM_MPU_RBAR_REGION_MASK        0xf
1079
1080 #define STM_MPU_RASR_XN         28
1081 #define STM_MPU_RASR_AP         24
1082 #define  STM_MPU_RASR_AP_NONE_NONE      0
1083 #define  STM_MPU_RASR_AP_RW_NONE        1
1084 #define  STM_MPU_RASR_AP_RW_RO          2
1085 #define  STM_MPU_RASR_AP_RW_RW          3
1086 #define  STM_MPU_RASR_AP_RO_NONE        5
1087 #define  STM_MPU_RASR_AP_RO_RO          6
1088 #define  STM_MPU_RASR_AP_MASK           7
1089 #define STM_MPU_RASR_TEX        19
1090 #define  STM_MPU_RASR_TEX_MASK          7
1091 #define STM_MPU_RASR_S          18
1092 #define STM_MPU_RASR_C          17
1093 #define STM_MPU_RASR_B          16
1094 #define STM_MPU_RASR_SRD        8
1095 #define  STM_MPU_RASR_SRD_MASK          0xff
1096 #define STM_MPU_RASR_SIZE       1
1097 #define  STM_MPU_RASR_SIZE_MASK         0x1f
1098 #define STM_MPU_RASR_ENABLE     0
1099
1100 #define isr(name) void stm_ ## name ## _isr(void);
1101
1102 isr(nmi)
1103 isr(hardfault)
1104 isr(memmanage)
1105 isr(busfault)
1106 isr(usagefault)
1107 isr(svc)
1108 isr(debugmon)
1109 isr(pendsv)
1110 isr(systick)
1111 isr(wwdg)
1112 isr(pvd)
1113 isr(tamper_stamp)
1114 isr(rtc_wkup)
1115 isr(flash)
1116 isr(rcc)
1117 isr(exti0)
1118 isr(exti1)
1119 isr(exti2)
1120 isr(exti3)
1121 isr(exti4)
1122 isr(dma1_channel1)
1123 isr(dma1_channel2)
1124 isr(dma1_channel3)
1125 isr(dma1_channel4)
1126 isr(dma1_channel5)
1127 isr(dma1_channel6)
1128 isr(dma1_channel7)
1129 isr(adc1)
1130 isr(usb_hp)
1131 isr(usb_lp)
1132 isr(dac)
1133 isr(comp)
1134 isr(exti9_5)
1135 isr(lcd)
1136 isr(tim9)
1137 isr(tim10)
1138 isr(tim11)
1139 isr(tim2)
1140 isr(tim3)
1141 isr(tim4)
1142 isr(i2c1_ev)
1143 isr(i2c1_er)
1144 isr(i2c2_ev)
1145 isr(i2c2_er)
1146 isr(spi1)
1147 isr(spi2)
1148 isr(usart1)
1149 isr(usart2)
1150 isr(usart3)
1151 isr(exti15_10)
1152 isr(rtc_alarm)
1153 isr(usb_fs_wkup)
1154 isr(tim6)
1155 isr(tim7)
1156
1157 #undef isr
1158
1159 #define STM_ISR_WWDG_POS                0
1160 #define STM_ISR_PVD_VDDIO2_POS          1
1161 #define STM_ISR_RTC_POS                 2
1162 #define STM_ISR_FLASH_POS               3
1163 #define STM_ISR_RCC_CRS_POS             4
1164 #define STM_ISR_EXTI0_1_POS             5
1165 #define STM_ISR_EXTI2_3_POS             6
1166 #define STM_ISR_EXTI4_15_POS            7
1167 #define STM_ISR_TSC_POS                 8
1168 #define STM_ISR_DMA_CH1_POS             9
1169 #define STM_ISR_DMA_CH2_3_DMA2_CH1_2_POS        10
1170 #define STM_ISR_DMA_CH44_5_6_7_DMA2_CH3_4_5_POS 11
1171 #define STM_ISR_ADC_COMP_POS            12
1172 #define STM_ISR_TIM1_BRK_UP_TRG_COM_POS 13
1173 #define STM_ISR_TIM1_CC_POS             14
1174 #define STM_ISR_TIM2_POS                15
1175 #define STM_ISR_TIM3_POS                16
1176 #define STM_ISR_TIM6_DAC_POS            17
1177 #define STM_ISR_TIM7_POS                18
1178 #define STM_ISR_TIM14_POS               19
1179 #define STM_ISR_TIM15_POS               20
1180 #define STM_ISR_TIM16_POS               21
1181 #define STM_ISR_TIM17_POS               22
1182 #define STM_ISR_I2C1_POS                23
1183 #define STM_ISR_I2C2_POS                24
1184 #define STM_ISR_SPI1_POS                25
1185 #define STM_ISR_SPI2_POS                26
1186 #define STM_ISR_USART1_POS              27
1187 #define STM_ISR_USART2_POS              28
1188 #define STM_ISR_UASART3_4_5_6_7_8_POS   29
1189 #define STM_ISR_CEC_CAN_POS             30
1190 #define STM_ISR_USB_POS                 31
1191
1192 struct stm_syscfg {
1193         vuint32_t       cfgr1;
1194         vuint32_t       exticr[4];
1195         vuint32_t       cfgr2;
1196 };
1197
1198 extern struct stm_syscfg stm_syscfg;
1199
1200 #define STM_SYSCFG_CFGR1_TIM3_DMA_RMP   30
1201 #define STM_SYSCFG_CFGR1_TIM2_DMA_RMP   29
1202 #define STM_SYSCFG_CFGR1_TIM1_DMA_RMP   28
1203 #define STM_SYSCFG_CFGR1_I2C1_DMA_RMP   27
1204 #define STM_SYSCFG_CFGR1_USART3_DMA_RMP 26
1205 #define STM_SYSCFG_CFGR1_USART2_DMA_RMP 25
1206 #define STM_SYSCFG_CFGR1_SPI2_DMA_RMP   24
1207 #define STM_SYSCFG_CFGR1_I2C_PA10_FMP   23
1208 #define STM_SYSCFG_CFGR1_I2C_PA9_FMP    22
1209 #define STM_SYSCFG_CFGR1_I2C2_FMP       21
1210 #define STM_SYSCFG_CFGR1_I2C1_FMP       20
1211 #define STM_SYSCFG_CFGR1_I2C_PB9_FMP    19
1212 #define STM_SYSCFG_CFGR1_I2C_PB8_FMP    18
1213 #define STM_SYSCFG_CFGR1_I2C_PB7_FMP    17
1214 #define STM_SYSCFG_CFGR1_I2C_PB6_FMP    16
1215 #define STM_SYSCFG_CFGR1_TIM17_DMA_RMP2 14
1216 #define STM_SYSCFG_CFGR1_TIM16_DMA_RMP2 13
1217 #define STM_SYSCFG_CFGR1_TIM17_DMA_RMP  12
1218 #define STM_SYSCFG_CFGR1_TIM16_DMA_RMP  11
1219 #define STM_SYSCFG_CFGR1_USART1_RX_DMA_RMP      10
1220 #define STM_SYSCFG_CFGR1_USART1_TX_DMA_RMP      9
1221 #define STM_SYSCFG_CFGR1_ADC_DMA_RMP            8
1222 #define STM_SYSCFG_CFGR1_IRDA_ENV_SEL   6
1223 #define  STM_SYSCFG_CFGR1_IRDA_ENV_SEL_TIMER16  0
1224 #define  STM_SYSCFG_CFGR1_IRDA_ENV_SEL_USART1   1
1225 #define  STM_SYSCFG_CFGR1_IRDA_ENV_SEL_USART4   2
1226 #define STM_SYSCFG_CFGR1_PA11_PA12_RMP  4
1227 #define STM_SYSCFG_CFGR1_MEM_MODE       0
1228 #define  STM_SYSCFG_CFGR1_MEM_MODE_MAIN_FLASH   0
1229 #define  STM_SYSCFG_CFGR1_MEM_MODE_SYSTEM_FLASH 1
1230 #define  STM_SYSCFG_CFGR1_MEM_MODE_SRAM         3
1231 #define  STM_SYSCFG_CFGR1_MEM_MODE_MASK         3
1232
1233 #if 0
1234 static inline void
1235 stm_exticr_set(struct stm_gpio *gpio, int pin) {
1236         uint8_t reg = pin >> 2;
1237         uint8_t shift = (pin & 3) << 2;
1238         uint8_t val = 0;
1239
1240         /* Enable SYSCFG */
1241         stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_SYSCFGCOMPEN);
1242
1243         if (gpio == &stm_gpioa)
1244                 val = STM_SYSCFG_EXTICR_PA;
1245         else if (gpio == &stm_gpiob)
1246                 val = STM_SYSCFG_EXTICR_PB;
1247         else if (gpio == &stm_gpioc)
1248                 val = STM_SYSCFG_EXTICR_PC;
1249         else if (gpio == &stm_gpiof)
1250                 val = STM_SYSCFG_EXTICR_PF;
1251
1252         stm_syscfg.exticr[reg] = (stm_syscfg.exticr[reg] & ~(0xf << shift)) | val << shift;
1253 }
1254 #endif
1255
1256
1257 struct stm_dma_channel {
1258         vuint32_t       ccr;
1259         vuint32_t       cndtr;
1260         vvoid_t         cpar;
1261         vvoid_t         cmar;
1262         vuint32_t       reserved;
1263 };
1264
1265 #define STM_NUM_DMA     7
1266
1267 struct stm_dma {
1268         vuint32_t               isr;
1269         vuint32_t               ifcr;
1270         struct stm_dma_channel  channel[STM_NUM_DMA];
1271 };
1272
1273 extern struct stm_dma stm_dma;
1274
1275 /* DMA channels go from 1 to 7, instead of 0 to 6 (sigh)
1276  */
1277
1278 #define STM_DMA_INDEX(channel)          ((channel) - 1)
1279
1280 #define STM_DMA_ISR(index)              ((index) << 2)
1281 #define STM_DMA_ISR_MASK                        0xf
1282 #define STM_DMA_ISR_TEIF                        3
1283 #define STM_DMA_ISR_HTIF                        2
1284 #define STM_DMA_ISR_TCIF                        1
1285 #define STM_DMA_ISR_GIF                         0
1286
1287 #define STM_DMA_IFCR(index)             ((index) << 2)
1288 #define STM_DMA_IFCR_MASK                       0xf
1289 #define STM_DMA_IFCR_CTEIF                      3
1290 #define STM_DMA_IFCR_CHTIF                      2
1291 #define STM_DMA_IFCR_CTCIF                      1
1292 #define STM_DMA_IFCR_CGIF                       0
1293
1294 #define STM_DMA_CCR_MEM2MEM             (14)
1295
1296 #define STM_DMA_CCR_PL                  (12)
1297 #define  STM_DMA_CCR_PL_LOW                     (0)
1298 #define  STM_DMA_CCR_PL_MEDIUM                  (1)
1299 #define  STM_DMA_CCR_PL_HIGH                    (2)
1300 #define  STM_DMA_CCR_PL_VERY_HIGH               (3)
1301 #define  STM_DMA_CCR_PL_MASK                    (3)
1302
1303 #define STM_DMA_CCR_MSIZE               (10)
1304 #define  STM_DMA_CCR_MSIZE_8                    (0)
1305 #define  STM_DMA_CCR_MSIZE_16                   (1)
1306 #define  STM_DMA_CCR_MSIZE_32                   (2)
1307 #define  STM_DMA_CCR_MSIZE_MASK                 (3)
1308
1309 #define STM_DMA_CCR_PSIZE               (8)
1310 #define  STM_DMA_CCR_PSIZE_8                    (0)
1311 #define  STM_DMA_CCR_PSIZE_16                   (1)
1312 #define  STM_DMA_CCR_PSIZE_32                   (2)
1313 #define  STM_DMA_CCR_PSIZE_MASK                 (3)
1314
1315 #define STM_DMA_CCR_MINC                (7)
1316 #define STM_DMA_CCR_PINC                (6)
1317 #define STM_DMA_CCR_CIRC                (5)
1318 #define STM_DMA_CCR_DIR                 (4)
1319 #define  STM_DMA_CCR_DIR_PER_TO_MEM             0
1320 #define  STM_DMA_CCR_DIR_MEM_TO_PER             1
1321 #define STM_DMA_CCR_TEIE                (3)
1322 #define STM_DMA_CCR_HTIE                (2)
1323 #define STM_DMA_CCR_TCIE                (1)
1324 #define STM_DMA_CCR_EN                  (0)
1325
1326 #define STM_DMA_CHANNEL_ADC1            1
1327 #define STM_DMA_CHANNEL_SPI1_RX         2
1328 #define STM_DMA_CHANNEL_SPI1_TX         3
1329 #define STM_DMA_CHANNEL_SPI2_RX         4
1330 #define STM_DMA_CHANNEL_SPI2_TX         5
1331 #define STM_DMA_CHANNEL_USART3_TX       2
1332 #define STM_DMA_CHANNEL_USART3_RX       3
1333 #define STM_DMA_CHANNEL_USART1_TX       4
1334 #define STM_DMA_CHANNEL_USART1_RX       5
1335 #define STM_DMA_CHANNEL_USART2_RX       6
1336 #define STM_DMA_CHANNEL_USART2_TX       7
1337 #define STM_DMA_CHANNEL_I2C2_TX         4
1338 #define STM_DMA_CHANNEL_I2C2_RX         5
1339 #define STM_DMA_CHANNEL_I2C1_TX         6
1340 #define STM_DMA_CHANNEL_I2C1_RX         7
1341 #define STM_DMA_CHANNEL_TIM2_CH3        1
1342 #define STM_DMA_CHANNEL_TIM2_UP         2
1343 #define STM_DMA_CHANNEL_TIM2_CH1        5
1344 #define STM_DMA_CHANNEL_TIM2_CH2        7
1345 #define STM_DMA_CHANNEL_TIM2_CH4        7
1346 #define STM_DMA_CHANNEL_TIM3_CH3        2
1347 #define STM_DMA_CHANNEL_TIM3_CH4        3
1348 #define STM_DMA_CHANNEL_TIM3_UP         3
1349 #define STM_DMA_CHANNEL_TIM3_CH1        6
1350 #define STM_DMA_CHANNEL_TIM3_TRIG       6
1351 #define STM_DMA_CHANNEL_TIM4_CH1        1
1352 #define STM_DMA_CHANNEL_TIM4_CH2        4
1353 #define STM_DMA_CHANNEL_TIM4_CH3        5
1354 #define STM_DMA_CHANNEL_TIM4_UP         7
1355 #define STM_DMA_CHANNEL_TIM6_UP_DA      2
1356 #define STM_DMA_CHANNEL_C_CHANNEL1      2
1357 #define STM_DMA_CHANNEL_TIM7_UP_DA      3
1358 #define STM_DMA_CHANNEL_C_CHANNEL2      3
1359
1360 /*
1361  * Only spi channel 1 and 2 can use DMA
1362  */
1363 #define STM_NUM_SPI     2
1364
1365 struct stm_spi {
1366         vuint32_t       cr1;
1367         vuint32_t       cr2;
1368         vuint32_t       sr;
1369         vuint32_t       dr;
1370         vuint32_t       crcpr;
1371         vuint32_t       rxcrcr;
1372         vuint32_t       txcrcr;
1373 };
1374
1375 extern struct stm_spi stm_spi1, stm_spi2, stm_spi3;
1376
1377 /* SPI channels go from 1 to 3, instead of 0 to 2 (sigh)
1378  */
1379
1380 #define STM_SPI_INDEX(channel)          ((channel) - 1)
1381
1382 #define STM_SPI_CR1_BIDIMODE            15
1383 #define STM_SPI_CR1_BIDIOE              14
1384 #define STM_SPI_CR1_CRCEN               13
1385 #define STM_SPI_CR1_CRCNEXT             12
1386 #define STM_SPI_CR1_DFF                 11
1387 #define STM_SPI_CR1_RXONLY              10
1388 #define STM_SPI_CR1_SSM                 9
1389 #define STM_SPI_CR1_SSI                 8
1390 #define STM_SPI_CR1_LSBFIRST            7
1391 #define STM_SPI_CR1_SPE                 6
1392 #define STM_SPI_CR1_BR                  3
1393 #define  STM_SPI_CR1_BR_PCLK_2                  0
1394 #define  STM_SPI_CR1_BR_PCLK_4                  1
1395 #define  STM_SPI_CR1_BR_PCLK_8                  2
1396 #define  STM_SPI_CR1_BR_PCLK_16                 3
1397 #define  STM_SPI_CR1_BR_PCLK_32                 4
1398 #define  STM_SPI_CR1_BR_PCLK_64                 5
1399 #define  STM_SPI_CR1_BR_PCLK_128                6
1400 #define  STM_SPI_CR1_BR_PCLK_256                7
1401 #define  STM_SPI_CR1_BR_MASK                    7
1402
1403 #define STM_SPI_CR1_MSTR                2
1404 #define STM_SPI_CR1_CPOL                1
1405 #define STM_SPI_CR1_CPHA                0
1406
1407 #define STM_SPI_CR2_TXEIE       7
1408 #define STM_SPI_CR2_RXNEIE      6
1409 #define STM_SPI_CR2_ERRIE       5
1410 #define STM_SPI_CR2_SSOE        2
1411 #define STM_SPI_CR2_TXDMAEN     1
1412 #define STM_SPI_CR2_RXDMAEN     0
1413
1414 #define STM_SPI_SR_BSY          7
1415 #define STM_SPI_SR_OVR          6
1416 #define STM_SPI_SR_MODF         5
1417 #define STM_SPI_SR_CRCERR       4
1418 #define STM_SPI_SR_TXE          1
1419 #define STM_SPI_SR_RXNE         0
1420
1421 struct stm_adc {
1422         vuint32_t       sr;
1423         vuint32_t       cr1;
1424         vuint32_t       cr2;
1425         vuint32_t       smpr1;
1426         vuint32_t       smpr2;
1427         vuint32_t       smpr3;
1428         vuint32_t       jofr1;
1429         vuint32_t       jofr2;
1430         vuint32_t       jofr3;
1431         vuint32_t       jofr4;
1432         vuint32_t       htr;
1433         vuint32_t       ltr;
1434         vuint32_t       sqr1;
1435         vuint32_t       sqr2;
1436         vuint32_t       sqr3;
1437         vuint32_t       sqr4;
1438         vuint32_t       sqr5;
1439         vuint32_t       jsqr;
1440         vuint32_t       jdr1;
1441         vuint32_t       jdr2;
1442         vuint32_t       jdr3;
1443         vuint32_t       jdr4;
1444         vuint32_t       dr;
1445         uint8_t         reserved[0x300 - 0x5c];
1446         vuint32_t       csr;
1447         vuint32_t       ccr;
1448 };
1449
1450 extern struct stm_adc stm_adc;
1451
1452 #define STM_ADC_SR_JCNR         9
1453 #define STM_ADC_SR_RCNR         8
1454 #define STM_ADC_SR_ADONS        6
1455 #define STM_ADC_SR_OVR          5
1456 #define STM_ADC_SR_STRT         4
1457 #define STM_ADC_SR_JSTRT        3
1458 #define STM_ADC_SR_JEOC         2
1459 #define STM_ADC_SR_EOC          1
1460 #define STM_ADC_SR_AWD          0
1461
1462 #define STM_ADC_CR1_OVRIE       26
1463 #define STM_ADC_CR1_RES         24
1464 #define  STM_ADC_CR1_RES_12             0
1465 #define  STM_ADC_CR1_RES_10             1
1466 #define  STM_ADC_CR1_RES_8              2
1467 #define  STM_ADC_CR1_RES_6              3
1468 #define  STM_ADC_CR1_RES_MASK           3
1469 #define STM_ADC_CR1_AWDEN       23
1470 #define STM_ADC_CR1_JAWDEN      22
1471 #define STM_ADC_CR1_PDI         17
1472 #define STM_ADC_CR1_PDD         16
1473 #define STM_ADC_CR1_DISCNUM     13
1474 #define  STM_ADC_CR1_DISCNUM_1          0
1475 #define  STM_ADC_CR1_DISCNUM_2          1
1476 #define  STM_ADC_CR1_DISCNUM_3          2
1477 #define  STM_ADC_CR1_DISCNUM_4          3
1478 #define  STM_ADC_CR1_DISCNUM_5          4
1479 #define  STM_ADC_CR1_DISCNUM_6          5
1480 #define  STM_ADC_CR1_DISCNUM_7          6
1481 #define  STM_ADC_CR1_DISCNUM_8          7
1482 #define  STM_ADC_CR1_DISCNUM_MASK       7
1483 #define STM_ADC_CR1_JDISCEN     12
1484 #define STM_ADC_CR1_DISCEN      11
1485 #define STM_ADC_CR1_JAUTO       10
1486 #define STM_ADC_CR1_AWDSGL      9
1487 #define STM_ADC_CR1_SCAN        8
1488 #define STM_ADC_CR1_JEOCIE      7
1489 #define STM_ADC_CR1_AWDIE       6
1490 #define STM_ADC_CR1_EOCIE       5
1491 #define STM_ADC_CR1_AWDCH       0
1492 #define  STM_ADC_CR1_AWDCH_MASK         0x1f
1493
1494 #define STM_ADC_CR2_SWSTART     30
1495 #define STM_ADC_CR2_EXTEN       28
1496 #define  STM_ADC_CR2_EXTEN_DISABLE      0
1497 #define  STM_ADC_CR2_EXTEN_RISING       1
1498 #define  STM_ADC_CR2_EXTEN_FALLING      2
1499 #define  STM_ADC_CR2_EXTEN_BOTH         3
1500 #define  STM_ADC_CR2_EXTEN_MASK         3
1501 #define STM_ADC_CR2_EXTSEL      24
1502 #define  STM_ADC_CR2_EXTSEL_TIM9_CC2    0
1503 #define  STM_ADC_CR2_EXTSEL_TIM9_TRGO   1
1504 #define  STM_ADC_CR2_EXTSEL_TIM2_CC3    2
1505 #define  STM_ADC_CR2_EXTSEL_TIM2_CC2    3
1506 #define  STM_ADC_CR2_EXTSEL_TIM3_TRGO   4
1507 #define  STM_ADC_CR2_EXTSEL_TIM4_CC4    5
1508 #define  STM_ADC_CR2_EXTSEL_TIM2_TRGO   6
1509 #define  STM_ADC_CR2_EXTSEL_TIM3_CC1    7
1510 #define  STM_ADC_CR2_EXTSEL_TIM3_CC3    8
1511 #define  STM_ADC_CR2_EXTSEL_TIM4_TRGO   9
1512 #define  STM_ADC_CR2_EXTSEL_TIM6_TRGO   10
1513 #define  STM_ADC_CR2_EXTSEL_EXTI_11     15
1514 #define  STM_ADC_CR2_EXTSEL_MASK        15
1515 #define STM_ADC_CR2_JWSTART     22
1516 #define STM_ADC_CR2_JEXTEN      20
1517 #define  STM_ADC_CR2_JEXTEN_DISABLE     0
1518 #define  STM_ADC_CR2_JEXTEN_RISING      1
1519 #define  STM_ADC_CR2_JEXTEN_FALLING     2
1520 #define  STM_ADC_CR2_JEXTEN_BOTH        3
1521 #define  STM_ADC_CR2_JEXTEN_MASK        3
1522 #define STM_ADC_CR2_JEXTSEL     16
1523 #define  STM_ADC_CR2_JEXTSEL_TIM9_CC1   0
1524 #define  STM_ADC_CR2_JEXTSEL_TIM9_TRGO  1
1525 #define  STM_ADC_CR2_JEXTSEL_TIM2_TRGO  2
1526 #define  STM_ADC_CR2_JEXTSEL_TIM2_CC1   3
1527 #define  STM_ADC_CR2_JEXTSEL_TIM3_CC4   4
1528 #define  STM_ADC_CR2_JEXTSEL_TIM4_TRGO  5
1529 #define  STM_ADC_CR2_JEXTSEL_TIM4_CC1   6
1530 #define  STM_ADC_CR2_JEXTSEL_TIM4_CC2   7
1531 #define  STM_ADC_CR2_JEXTSEL_TIM4_CC3   8
1532 #define  STM_ADC_CR2_JEXTSEL_TIM10_CC1  9
1533 #define  STM_ADC_CR2_JEXTSEL_TIM7_TRGO  10
1534 #define  STM_ADC_CR2_JEXTSEL_EXTI_15    15
1535 #define  STM_ADC_CR2_JEXTSEL_MASK       15
1536 #define STM_ADC_CR2_ALIGN       11
1537 #define STM_ADC_CR2_EOCS        10
1538 #define STM_ADC_CR2_DDS         9
1539 #define STM_ADC_CR2_DMA         8
1540 #define STM_ADC_CR2_DELS        4
1541 #define  STM_ADC_CR2_DELS_NONE          0
1542 #define  STM_ADC_CR2_DELS_UNTIL_READ    1
1543 #define  STM_ADC_CR2_DELS_7             2
1544 #define  STM_ADC_CR2_DELS_15            3
1545 #define  STM_ADC_CR2_DELS_31            4
1546 #define  STM_ADC_CR2_DELS_63            5
1547 #define  STM_ADC_CR2_DELS_127           6
1548 #define  STM_ADC_CR2_DELS_255           7
1549 #define  STM_ADC_CR2_DELS_MASK          7
1550 #define STM_ADC_CR2_CONT        1
1551 #define STM_ADC_CR2_ADON        0
1552
1553 #define STM_ADC_CCR_TSVREFE     23
1554 #define STM_ADC_CCR_ADCPRE      16
1555 #define  STM_ADC_CCR_ADCPRE_HSI_1       0
1556 #define  STM_ADC_CCR_ADCPRE_HSI_2       1
1557 #define  STM_ADC_CCR_ADCPRE_HSI_4       2
1558 #define  STM_ADC_CCR_ADCPRE_MASK        3
1559
1560 struct stm_cal {
1561         uint16_t        ts_cal_cold;    /* 30°C */
1562         uint16_t        vrefint_cal;
1563         uint16_t        unused_c0;
1564         uint16_t        ts_cal_hot;     /* 110°C */
1565 };
1566
1567 extern struct stm_cal   stm_cal;
1568
1569 #define stm_temp_cal_cold       30
1570 #define stm_temp_cal_hot        110
1571
1572 struct stm_dbgmcu {
1573         uint32_t        idcode;
1574 };
1575
1576 extern struct stm_dbgmcu        stm_dbgmcu;
1577
1578 static inline uint16_t
1579 stm_dev_id(void) {
1580         return stm_dbgmcu.idcode & 0xfff;
1581 }
1582
1583 struct stm_flash_size {
1584         uint16_t        f_size;
1585 };
1586
1587 extern struct stm_flash_size    stm_flash_size_04x;
1588
1589 /* Returns flash size in bytes */
1590 extern uint32_t
1591 stm_flash_size(void);
1592
1593 struct stm_device_id {
1594         uint32_t        u_id0;
1595         uint32_t        u_id1;
1596         uint32_t        u_id2;
1597 };
1598
1599 extern struct stm_device_id     stm_device_id;
1600
1601 #define STM_NUM_I2C     2
1602
1603 #define STM_I2C_INDEX(channel)  ((channel) - 1)
1604
1605 struct stm_i2c {
1606         vuint32_t       cr1;
1607         vuint32_t       cr2;
1608         vuint32_t       oar1;
1609         vuint32_t       oar2;
1610         vuint32_t       dr;
1611         vuint32_t       sr1;
1612         vuint32_t       sr2;
1613         vuint32_t       ccr;
1614         vuint32_t       trise;
1615 };
1616
1617 extern struct stm_i2c stm_i2c1, stm_i2c2;
1618
1619 #define STM_I2C_CR1_SWRST       15
1620 #define STM_I2C_CR1_ALERT       13
1621 #define STM_I2C_CR1_PEC         12
1622 #define STM_I2C_CR1_POS         11
1623 #define STM_I2C_CR1_ACK         10
1624 #define STM_I2C_CR1_STOP        9
1625 #define STM_I2C_CR1_START       8
1626 #define STM_I2C_CR1_NOSTRETCH   7
1627 #define STM_I2C_CR1_ENGC        6
1628 #define STM_I2C_CR1_ENPEC       5
1629 #define STM_I2C_CR1_ENARP       4
1630 #define STM_I2C_CR1_SMBTYPE     3
1631 #define STM_I2C_CR1_SMBUS       1
1632 #define STM_I2C_CR1_PE          0
1633
1634 #define STM_I2C_CR2_LAST        12
1635 #define STM_I2C_CR2_DMAEN       11
1636 #define STM_I2C_CR2_ITBUFEN     10
1637 #define STM_I2C_CR2_ITEVTEN     9
1638 #define STM_I2C_CR2_ITERREN     8
1639 #define STM_I2C_CR2_FREQ        0
1640 #define  STM_I2C_CR2_FREQ_2_MHZ         2
1641 #define  STM_I2C_CR2_FREQ_4_MHZ         4
1642 #define  STM_I2C_CR2_FREQ_8_MHZ         8
1643 #define  STM_I2C_CR2_FREQ_16_MHZ        16
1644 #define  STM_I2C_CR2_FREQ_32_MHZ        32
1645 #define  STM_I2C_CR2_FREQ_MASK          0x3f
1646
1647 #define STM_I2C_SR1_SMBALERT    15
1648 #define STM_I2C_SR1_TIMEOUT     14
1649 #define STM_I2C_SR1_PECERR      12
1650 #define STM_I2C_SR1_OVR         11
1651 #define STM_I2C_SR1_AF          10
1652 #define STM_I2C_SR1_ARLO        9
1653 #define STM_I2C_SR1_BERR        8
1654 #define STM_I2C_SR1_TXE         7
1655 #define STM_I2C_SR1_RXNE        6
1656 #define STM_I2C_SR1_STOPF       4
1657 #define STM_I2C_SR1_ADD10       3
1658 #define STM_I2C_SR1_BTF         2
1659 #define STM_I2C_SR1_ADDR        1
1660 #define STM_I2C_SR1_SB          0
1661
1662 #define STM_I2C_SR2_PEC         8
1663 #define  STM_I2C_SR2_PEC_MASK   0xff00
1664 #define STM_I2C_SR2_DUALF       7
1665 #define STM_I2C_SR2_SMBHOST     6
1666 #define STM_I2C_SR2_SMBDEFAULT  5
1667 #define STM_I2C_SR2_GENCALL     4
1668 #define STM_I2C_SR2_TRA         2
1669 #define STM_I2C_SR2_BUSY        1
1670 #define STM_I2C_SR2_MSL         0
1671
1672 #define STM_I2C_CCR_FS          15
1673 #define STM_I2C_CCR_DUTY        14
1674 #define STM_I2C_CCR_CCR         0
1675 #define  STM_I2C_CCR_MASK       0x7ff
1676
1677 struct stm_tim234 {
1678         vuint32_t       cr1;
1679         vuint32_t       cr2;
1680         vuint32_t       smcr;
1681         vuint32_t       dier;
1682
1683         vuint32_t       sr;
1684         vuint32_t       egr;
1685         vuint32_t       ccmr1;
1686         vuint32_t       ccmr2;
1687
1688         vuint32_t       ccer;
1689         vuint32_t       cnt;
1690         vuint32_t       psc;
1691         vuint32_t       arr;
1692
1693         uint32_t        reserved_30;
1694         vuint32_t       ccr1;
1695         vuint32_t       ccr2;
1696         vuint32_t       ccr3;
1697
1698         vuint32_t       ccr4;
1699         uint32_t        reserved_44;
1700         vuint32_t       dcr;
1701         vuint32_t       dmar;
1702
1703         uint32_t        reserved_50;
1704 };
1705
1706 extern struct stm_tim234 stm_tim2, stm_tim3, stm_tim4;
1707
1708 #define STM_TIM234_CR1_CKD      8
1709 #define  STM_TIM234_CR1_CKD_1           0
1710 #define  STM_TIM234_CR1_CKD_2           1
1711 #define  STM_TIM234_CR1_CKD_4           2
1712 #define  STM_TIM234_CR1_CKD_MASK        3
1713 #define STM_TIM234_CR1_ARPE     7
1714 #define STM_TIM234_CR1_CMS      5
1715 #define  STM_TIM234_CR1_CMS_EDGE        0
1716 #define  STM_TIM234_CR1_CMS_CENTER_1    1
1717 #define  STM_TIM234_CR1_CMS_CENTER_2    2
1718 #define  STM_TIM234_CR1_CMS_CENTER_3    3
1719 #define  STM_TIM234_CR1_CMS_MASK        3
1720 #define STM_TIM234_CR1_DIR      4
1721 #define  STM_TIM234_CR1_DIR_UP          0
1722 #define  STM_TIM234_CR1_DIR_DOWN        1
1723 #define STM_TIM234_CR1_OPM      3
1724 #define STM_TIM234_CR1_URS      2
1725 #define STM_TIM234_CR1_UDIS     1
1726 #define STM_TIM234_CR1_CEN      0
1727
1728 #define STM_TIM234_CR2_TI1S     7
1729 #define STM_TIM234_CR2_MMS      4
1730 #define  STM_TIM234_CR2_MMS_RESET               0
1731 #define  STM_TIM234_CR2_MMS_ENABLE              1
1732 #define  STM_TIM234_CR2_MMS_UPDATE              2
1733 #define  STM_TIM234_CR2_MMS_COMPARE_PULSE       3
1734 #define  STM_TIM234_CR2_MMS_COMPARE_OC1REF      4
1735 #define  STM_TIM234_CR2_MMS_COMPARE_OC2REF      5
1736 #define  STM_TIM234_CR2_MMS_COMPARE_OC3REF      6
1737 #define  STM_TIM234_CR2_MMS_COMPARE_OC4REF      7
1738 #define  STM_TIM234_CR2_MMS_MASK                7
1739 #define STM_TIM234_CR2_CCDS     3
1740
1741 #define STM_TIM234_SMCR_ETP     15
1742 #define STM_TIM234_SMCR_ECE     14
1743 #define STM_TIM234_SMCR_ETPS    12
1744 #define  STM_TIM234_SMCR_ETPS_OFF               0
1745 #define  STM_TIM234_SMCR_ETPS_DIV_2             1
1746 #define  STM_TIM234_SMCR_ETPS_DIV_4             2
1747 #define  STM_TIM234_SMCR_ETPS_DIV_8             3
1748 #define  STM_TIM234_SMCR_ETPS_MASK              3
1749 #define STM_TIM234_SMCR_ETF     8
1750 #define  STM_TIM234_SMCR_ETF_NONE               0
1751 #define  STM_TIM234_SMCR_ETF_INT_N_2            1
1752 #define  STM_TIM234_SMCR_ETF_INT_N_4            2
1753 #define  STM_TIM234_SMCR_ETF_INT_N_8            3
1754 #define  STM_TIM234_SMCR_ETF_DTS_2_N_6          4
1755 #define  STM_TIM234_SMCR_ETF_DTS_2_N_8          5
1756 #define  STM_TIM234_SMCR_ETF_DTS_4_N_6          6
1757 #define  STM_TIM234_SMCR_ETF_DTS_4_N_8          7
1758 #define  STM_TIM234_SMCR_ETF_DTS_8_N_6          8
1759 #define  STM_TIM234_SMCR_ETF_DTS_8_N_8          9
1760 #define  STM_TIM234_SMCR_ETF_DTS_16_N_5         10
1761 #define  STM_TIM234_SMCR_ETF_DTS_16_N_6         11
1762 #define  STM_TIM234_SMCR_ETF_DTS_16_N_8         12
1763 #define  STM_TIM234_SMCR_ETF_DTS_32_N_5         13
1764 #define  STM_TIM234_SMCR_ETF_DTS_32_N_6         14
1765 #define  STM_TIM234_SMCR_ETF_DTS_32_N_8         15
1766 #define  STM_TIM234_SMCR_ETF_MASK               15
1767 #define STM_TIM234_SMCR_MSM     7
1768 #define STM_TIM234_SMCR_TS      4
1769 #define  STM_TIM234_SMCR_TS_ITR0                0
1770 #define  STM_TIM234_SMCR_TS_ITR1                1
1771 #define  STM_TIM234_SMCR_TS_ITR2                2
1772 #define  STM_TIM234_SMCR_TS_ITR3                3
1773 #define  STM_TIM234_SMCR_TS_TI1F_ED             4
1774 #define  STM_TIM234_SMCR_TS_TI1FP1              5
1775 #define  STM_TIM234_SMCR_TS_TI2FP2              6
1776 #define  STM_TIM234_SMCR_TS_ETRF                7
1777 #define  STM_TIM234_SMCR_TS_MASK                7
1778 #define STM_TIM234_SMCR_OCCS    3
1779 #define STM_TIM234_SMCR_SMS     0
1780 #define  STM_TIM234_SMCR_SMS_DISABLE            0
1781 #define  STM_TIM234_SMCR_SMS_ENCODER_MODE_1     1
1782 #define  STM_TIM234_SMCR_SMS_ENCODER_MODE_2     2
1783 #define  STM_TIM234_SMCR_SMS_ENCODER_MODE_3     3
1784 #define  STM_TIM234_SMCR_SMS_RESET_MODE         4
1785 #define  STM_TIM234_SMCR_SMS_GATED_MODE         5
1786 #define  STM_TIM234_SMCR_SMS_TRIGGER_MODE       6
1787 #define  STM_TIM234_SMCR_SMS_EXTERNAL_CLOCK     7
1788 #define  STM_TIM234_SMCR_SMS_MASK               7
1789
1790 #define STM_TIM234_SR_CC4OF     12
1791 #define STM_TIM234_SR_CC3OF     11
1792 #define STM_TIM234_SR_CC2OF     10
1793 #define STM_TIM234_SR_CC1OF     9
1794 #define STM_TIM234_SR_TIF       6
1795 #define STM_TIM234_SR_CC4IF     4
1796 #define STM_TIM234_SR_CC3IF     3
1797 #define STM_TIM234_SR_CC2IF     2
1798 #define STM_TIM234_SR_CC1IF     1
1799 #define STM_TIM234_SR_UIF       0
1800
1801 #define STM_TIM234_EGR_TG       6
1802 #define STM_TIM234_EGR_CC4G     4
1803 #define STM_TIM234_EGR_CC3G     3
1804 #define STM_TIM234_EGR_CC2G     2
1805 #define STM_TIM234_EGR_CC1G     1
1806 #define STM_TIM234_EGR_UG       0
1807
1808 #define STM_TIM234_CCMR1_OC2CE  15
1809 #define STM_TIM234_CCMR1_OC2M   12
1810 #define  STM_TIM234_CCMR1_OC2M_FROZEN                   0
1811 #define  STM_TIM234_CCMR1_OC2M_SET_HIGH_ON_MATCH        1
1812 #define  STM_TIM234_CCMR1_OC2M_SET_LOW_ON_MATCH         2
1813 #define  STM_TIM234_CCMR1_OC2M_TOGGLE                   3
1814 #define  STM_TIM234_CCMR1_OC2M_FORCE_LOW                4
1815 #define  STM_TIM234_CCMR1_OC2M_FORCE_HIGH               5
1816 #define  STM_TIM234_CCMR1_OC2M_PWM_MODE_1               6
1817 #define  STM_TIM234_CCMR1_OC2M_PWM_MODE_2               7
1818 #define  STM_TIM234_CCMR1_OC2M_MASK                     7
1819 #define STM_TIM234_CCMR1_OC2PE  11
1820 #define STM_TIM234_CCMR1_OC2FE  10
1821 #define STM_TIM234_CCMR1_CC2S   8
1822 #define  STM_TIM234_CCMR1_CC2S_OUTPUT                   0
1823 #define  STM_TIM234_CCMR1_CC2S_INPUT_TI2                1
1824 #define  STM_TIM234_CCMR1_CC2S_INPUT_TI1                2
1825 #define  STM_TIM234_CCMR1_CC2S_INPUT_TRC                3
1826 #define  STM_TIM234_CCMR1_CC2S_MASK                     3
1827
1828 #define STM_TIM234_CCMR1_OC1CE  7
1829 #define STM_TIM234_CCMR1_OC1M   4
1830 #define  STM_TIM234_CCMR1_OC1M_FROZEN                   0
1831 #define  STM_TIM234_CCMR1_OC1M_SET_HIGH_ON_MATCH        1
1832 #define  STM_TIM234_CCMR1_OC1M_SET_LOW_ON_MATCH         2
1833 #define  STM_TIM234_CCMR1_OC1M_TOGGLE                   3
1834 #define  STM_TIM234_CCMR1_OC1M_FORCE_LOW                4
1835 #define  STM_TIM234_CCMR1_OC1M_FORCE_HIGH               5
1836 #define  STM_TIM234_CCMR1_OC1M_PWM_MODE_1               6
1837 #define  STM_TIM234_CCMR1_OC1M_PWM_MODE_2               7
1838 #define  STM_TIM234_CCMR1_OC1M_MASK                     7
1839 #define STM_TIM234_CCMR1_OC1PE  11
1840 #define STM_TIM234_CCMR1_OC1FE  2
1841 #define STM_TIM234_CCMR1_CC1S   0
1842 #define  STM_TIM234_CCMR1_CC1S_OUTPUT                   0
1843 #define  STM_TIM234_CCMR1_CC1S_INPUT_TI1                1
1844 #define  STM_TIM234_CCMR1_CC1S_INPUT_TI2                2
1845 #define  STM_TIM234_CCMR1_CC1S_INPUT_TRC                3
1846 #define  STM_TIM234_CCMR1_CC1S_MASK                     3
1847
1848 #define STM_TIM234_CCMR2_OC4CE  15
1849 #define STM_TIM234_CCMR2_OC4M   12
1850 #define  STM_TIM234_CCMR2_OC4M_FROZEN                   0
1851 #define  STM_TIM234_CCMR2_OC4M_SET_HIGH_ON_MATCH        1
1852 #define  STM_TIM234_CCMR2_OC4M_SET_LOW_ON_MATCH         2
1853 #define  STM_TIM234_CCMR2_OC4M_TOGGLE                   3
1854 #define  STM_TIM234_CCMR2_OC4M_FORCE_LOW                4
1855 #define  STM_TIM234_CCMR2_OC4M_FORCE_HIGH               5
1856 #define  STM_TIM234_CCMR2_OC4M_PWM_MODE_1               6
1857 #define  STM_TIM234_CCMR2_OC4M_PWM_MODE_2               7
1858 #define  STM_TIM234_CCMR2_OC4M_MASK                     7
1859 #define STM_TIM234_CCMR2_OC4PE  11
1860 #define STM_TIM234_CCMR2_OC4FE  10
1861 #define STM_TIM234_CCMR2_CC4S   8
1862 #define  STM_TIM234_CCMR2_CC4S_OUTPUT                   0
1863 #define  STM_TIM234_CCMR2_CC4S_INPUT_TI4                1
1864 #define  STM_TIM234_CCMR2_CC4S_INPUT_TI3                2
1865 #define  STM_TIM234_CCMR2_CC4S_INPUT_TRC                3
1866 #define  STM_TIM234_CCMR2_CC4S_MASK                     3
1867
1868 #define STM_TIM234_CCMR2_OC3CE  7
1869 #define STM_TIM234_CCMR2_OC3M   4
1870 #define  STM_TIM234_CCMR2_OC3M_FROZEN                   0
1871 #define  STM_TIM234_CCMR2_OC3M_SET_HIGH_ON_MATCH        1
1872 #define  STM_TIM234_CCMR2_OC3M_SET_LOW_ON_MATCH         2
1873 #define  STM_TIM234_CCMR2_OC3M_TOGGLE                   3
1874 #define  STM_TIM234_CCMR2_OC3M_FORCE_LOW                4
1875 #define  STM_TIM234_CCMR2_OC3M_FORCE_HIGH               5
1876 #define  STM_TIM234_CCMR2_OC3M_PWM_MODE_1               6
1877 #define  STM_TIM234_CCMR2_OC3M_PWM_MODE_2               7
1878 #define  STM_TIM234_CCMR2_OC3M_MASK                     7
1879 #define STM_TIM234_CCMR2_OC3PE  11
1880 #define STM_TIM234_CCMR2_OC3FE  2
1881 #define STM_TIM234_CCMR2_CC3S   0
1882 #define  STM_TIM234_CCMR2_CC3S_OUTPUT                   0
1883 #define  STM_TIM234_CCMR2_CC3S_INPUT_TI3                1
1884 #define  STM_TIM234_CCMR2_CC3S_INPUT_TI4                2
1885 #define  STM_TIM234_CCMR2_CC3S_INPUT_TRC                3
1886 #define  STM_TIM234_CCMR2_CC3S_MASK                     3
1887
1888 #define STM_TIM234_CCER_CC4NP   15
1889 #define STM_TIM234_CCER_CC4P    13
1890 #define STM_TIM234_CCER_CC4E    12
1891 #define STM_TIM234_CCER_CC3NP   11
1892 #define STM_TIM234_CCER_CC3P    9
1893 #define STM_TIM234_CCER_CC3E    8
1894 #define STM_TIM234_CCER_CC2NP   7
1895 #define STM_TIM234_CCER_CC2P    5
1896 #define STM_TIM234_CCER_CC2E    4
1897 #define STM_TIM234_CCER_CC1NP   3
1898 #define STM_TIM234_CCER_CC1P    1
1899 #define STM_TIM234_CCER_CC1E    0
1900
1901 struct stm_usb {
1902         struct {
1903                 vuint16_t       r;
1904                 uint16_t        _;
1905         } epr[8];
1906         uint8_t         reserved_20[0x40 - 0x20];
1907         vuint16_t       cntr;
1908         uint16_t        reserved_42;
1909         vuint16_t       istr;
1910         uint16_t        reserved_46;
1911         vuint16_t       fnr;
1912         uint16_t        reserved_4a;
1913         vuint16_t       daddr;
1914         uint16_t        reserved_4e;
1915         vuint16_t       btable;
1916         uint16_t        reserved_52;
1917         vuint16_t       lpmcsr;
1918         uint16_t        reserved_56;
1919         vuint16_t       bcdr;
1920         uint16_t        reserved_5a;
1921 };
1922
1923 extern struct stm_usb stm_usb;
1924
1925 #define STM_USB_EPR_CTR_RX      15
1926 #define  STM_USB_EPR_CTR_RX_WRITE_INVARIANT             1
1927 #define STM_USB_EPR_DTOG_RX     14
1928 #define STM_USB_EPR_DTOG_RX_WRITE_INVARIANT             0
1929 #define STM_USB_EPR_STAT_RX     12
1930 #define  STM_USB_EPR_STAT_RX_DISABLED                   0
1931 #define  STM_USB_EPR_STAT_RX_STALL                      1
1932 #define  STM_USB_EPR_STAT_RX_NAK                        2
1933 #define  STM_USB_EPR_STAT_RX_VALID                      3
1934 #define  STM_USB_EPR_STAT_RX_MASK                       3
1935 #define  STM_USB_EPR_STAT_RX_WRITE_INVARIANT            0
1936 #define STM_USB_EPR_SETUP       11
1937 #define STM_USB_EPR_EP_TYPE     9
1938 #define  STM_USB_EPR_EP_TYPE_BULK                       0
1939 #define  STM_USB_EPR_EP_TYPE_CONTROL                    1
1940 #define  STM_USB_EPR_EP_TYPE_ISO                        2
1941 #define  STM_USB_EPR_EP_TYPE_INTERRUPT                  3
1942 #define  STM_USB_EPR_EP_TYPE_MASK                       3
1943 #define STM_USB_EPR_EP_KIND     8
1944 #define  STM_USB_EPR_EP_KIND_DBL_BUF                    1       /* Bulk */
1945 #define  STM_USB_EPR_EP_KIND_STATUS_OUT                 1       /* Control */
1946 #define STM_USB_EPR_CTR_TX      7
1947 #define  STM_USB_CTR_TX_WRITE_INVARIANT                 1
1948 #define STM_USB_EPR_DTOG_TX     6
1949 #define  STM_USB_EPR_DTOG_TX_WRITE_INVARIANT            0
1950 #define STM_USB_EPR_STAT_TX     4
1951 #define  STM_USB_EPR_STAT_TX_DISABLED                   0
1952 #define  STM_USB_EPR_STAT_TX_STALL                      1
1953 #define  STM_USB_EPR_STAT_TX_NAK                        2
1954 #define  STM_USB_EPR_STAT_TX_VALID                      3
1955 #define  STM_USB_EPR_STAT_TX_WRITE_INVARIANT            0
1956 #define  STM_USB_EPR_STAT_TX_MASK                       3
1957 #define STM_USB_EPR_EA          0
1958 #define  STM_USB_EPR_EA_MASK                            0xf
1959
1960 #define STM_USB_CNTR_CTRM       15
1961 #define STM_USB_CNTR_PMAOVRM    14
1962 #define STM_USB_CNTR_ERRM       13
1963 #define STM_USB_CNTR_WKUPM      12
1964 #define STM_USB_CNTR_SUSPM      11
1965 #define STM_USB_CNTR_RESETM     10
1966 #define STM_USB_CNTR_SOFM       9
1967 #define STM_USB_CNTR_ESOFM      8
1968 #define STM_USB_CNTR_RESUME     4
1969 #define STM_USB_CNTR_FSUSP      3
1970 #define STM_USB_CNTR_LP_MODE    2
1971 #define STM_USB_CNTR_PDWN       1
1972 #define STM_USB_CNTR_FRES       0
1973
1974 #define STM_USB_ISTR_CTR        15
1975 #define STM_USB_ISTR_PMAOVR     14
1976 #define STM_USB_ISTR_ERR        13
1977 #define STM_USB_ISTR_WKUP       12
1978 #define STM_USB_ISTR_SUSP       11
1979 #define STM_USB_ISTR_RESET      10
1980 #define STM_USB_ISTR_SOF        9
1981 #define STM_USB_ISTR_ESOF       8
1982 #define STM_USB_L1REQ           7
1983 #define STM_USB_ISTR_DIR        4
1984 #define STM_USB_ISTR_EP_ID      0
1985 #define  STM_USB_ISTR_EP_ID_MASK                0xf
1986
1987 #define STM_USB_FNR_RXDP        15
1988 #define STM_USB_FNR_RXDM        14
1989 #define STM_USB_FNR_LCK         13
1990 #define STM_USB_FNR_LSOF        11
1991 #define  STM_USB_FNR_LSOF_MASK                  0x3
1992 #define STM_USB_FNR_FN          0
1993 #define  STM_USB_FNR_FN_MASK                    0x7ff
1994
1995 #define STM_USB_DADDR_EF        7
1996 #define STM_USB_DADDR_ADD       0
1997 #define  STM_USB_DADDR_ADD_MASK                 0x7f
1998
1999 #define STM_USB_BCDR_DPPU       15
2000 #define STM_USB_BCDR_PS2DET     7
2001 #define STM_USB_BCDR_SDET       6
2002 #define STM_USB_BCDR_PDET       5
2003 #define STM_USB_BCDR_DCDET      4
2004 #define STM_USB_BCDR_SDEN       3
2005 #define STM_USB_BCDR_PDEN       2
2006 #define STM_USB_BCDR_DCDEN      1
2007 #define STM_USB_BCDR_BCDEN      0
2008
2009 union stm_usb_bdt {
2010         struct {
2011                 vuint16_t       addr_tx;
2012                 vuint16_t       count_tx;
2013                 vuint16_t       addr_rx;
2014                 vuint16_t       count_rx;
2015         } single;
2016         struct {
2017                 vuint16_t       addr;
2018                 vuint16_t       count;
2019         } double_tx[2];
2020         struct {
2021                 vuint16_t       addr;
2022                 vuint16_t       count;
2023         } double_rx[2];
2024 };
2025
2026 #define STM_USB_BDT_COUNT_RX_BL_SIZE    15
2027 #define STM_USB_BDT_COUNT_RX_NUM_BLOCK  10
2028 #define  STM_USB_BDT_COUNT_RX_NUM_BLOCK_MASK    0x1f
2029 #define STM_USB_BDT_COUNT_RX_COUNT_RX   0
2030 #define  STM_USB_BDT_COUNT_RX_COUNT_RX_MASK     0x1ff
2031
2032 #define STM_USB_BDT_SIZE        8
2033
2034 extern uint8_t stm_usb_sram[];
2035
2036 struct stm_exti {
2037         vuint32_t       imr;
2038         vuint32_t       emr;
2039         vuint32_t       rtsr;
2040         vuint32_t       ftsr;
2041
2042         vuint32_t       swier;
2043         vuint32_t       pr;
2044 };
2045
2046 extern struct stm_exti stm_exti;
2047
2048 #endif /* _STM32F0_H_ */