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   1 /*
   2  * Copyright © 2015 Keith Packard <keithp@keithp.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; version 2 of the License.
   7  *
   8  * This program is distributed in the hope that it will be useful, but
   9  * WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  11  * General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along
  14  * with this program; if not, write to the Free Software Foundation, Inc.,
  15  * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  16  */
  17
  18 #ifndef _STM32F0_H_
  19 #define _STM32F0_H_
  20
  21 #include <stdint.h>
  22
  23 typedef volatile uint32_t       vuint32_t;
  24 typedef volatile void *         vvoid_t;
  25 typedef volatile uint16_t       vuint16_t;
  26 typedef volatile uint8_t        vuint8_t;
  27
  28 struct stm_gpio {
  29         vuint32_t       moder;
  30         vuint32_t       otyper;
  31         vuint32_t       ospeedr;
  32         vuint32_t       pupdr;
  33
  34         vuint32_t       idr;
  35         vuint32_t       odr;
  36         vuint32_t       bsrr;
  37         vuint32_t       lckr;
  38
  39         vuint32_t       afrl;
  40         vuint32_t       afrh;
  41         vuint32_t       brr;
  42 };
  43
  44 #define STM_MODER_SHIFT(pin)            ((pin) << 1)
  45 #define STM_MODER_MASK                  3
  46 #define STM_MODER_INPUT                 0
  47 #define STM_MODER_OUTPUT                1
  48 #define STM_MODER_ALTERNATE             2
  49 #define STM_MODER_ANALOG                3
  50
  51 static inline void
  52 stm_moder_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
  53         gpio->moder = ((gpio->moder &
  54                         ~(STM_MODER_MASK << STM_MODER_SHIFT(pin))) |
  55                        value << STM_MODER_SHIFT(pin));
  56 }
  57
  58 static inline uint32_t
  59 stm_moder_get(struct stm_gpio *gpio, int pin) {
  60         return (gpio->moder >> STM_MODER_SHIFT(pin)) & STM_MODER_MASK;
  61 }
  62
  63 #define STM_OTYPER_SHIFT(pin)           (pin)
  64 #define STM_OTYPER_MASK                 1
  65 #define STM_OTYPER_PUSH_PULL            0
  66 #define STM_OTYPER_OPEN_DRAIN           1
  67
  68 static inline void
  69 stm_otyper_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
  70         gpio->otyper = ((gpio->otyper &
  71                          ~(STM_OTYPER_MASK << STM_OTYPER_SHIFT(pin))) |
  72                         value << STM_OTYPER_SHIFT(pin));
  73 }
  74
  75 static inline uint32_t
  76 stm_otyper_get(struct stm_gpio *gpio, int pin) {
  77         return (gpio->otyper >> STM_OTYPER_SHIFT(pin)) & STM_OTYPER_MASK;
  78 }
  79
  80 #define STM_OSPEEDR_SHIFT(pin)          ((pin) << 1)
  81 #define STM_OSPEEDR_MASK                3
  82 #define STM_OSPEEDR_LOW                 0       /* 2MHz */
  83 #define STM_OSPEEDR_MEDIUM              1       /* 10MHz */
  84 #define STM_OSPEEDR_HIGH                3       /* 10-50MHz */
  85
  86 static inline void
  87 stm_ospeedr_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
  88         gpio->ospeedr = ((gpio->ospeedr &
  89                         ~(STM_OSPEEDR_MASK << STM_OSPEEDR_SHIFT(pin))) |
  90                        value << STM_OSPEEDR_SHIFT(pin));
  91 }
  92
  93 static inline uint32_t
  94 stm_ospeedr_get(struct stm_gpio *gpio, int pin) {
  95         return (gpio->ospeedr >> STM_OSPEEDR_SHIFT(pin)) & STM_OSPEEDR_MASK;
  96 }
  97
  98 #define STM_PUPDR_SHIFT(pin)            ((pin) << 1)
  99 #define STM_PUPDR_MASK                  3
 100 #define STM_PUPDR_NONE                  0
 101 #define STM_PUPDR_PULL_UP               1
 102 #define STM_PUPDR_PULL_DOWN             2
 103 #define STM_PUPDR_RESERVED              3
 104
 105 static inline void
 106 stm_pupdr_set(struct stm_gpio *gpio, int pin, uint32_t value) {
 107         gpio->pupdr = ((gpio->pupdr &
 108                         ~(STM_PUPDR_MASK << STM_PUPDR_SHIFT(pin))) |
 109                        value << STM_PUPDR_SHIFT(pin));
 110 }
 111
 112 static inline uint32_t
 113 stm_pupdr_get(struct stm_gpio *gpio, int pin) {
 114         return (gpio->pupdr >> STM_PUPDR_SHIFT(pin)) & STM_PUPDR_MASK;
 115 }
 116
 117 #define STM_AFR_SHIFT(pin)              ((pin) << 2)
 118 #define STM_AFR_MASK                    0xf
 119 #define STM_AFR_NONE                    0
 120 #define STM_AFR_AF0                     0x0
 121 #define STM_AFR_AF1                     0x1
 122 #define STM_AFR_AF2                     0x2
 123 #define STM_AFR_AF3                     0x3
 124 #define STM_AFR_AF4                     0x4
 125 #define STM_AFR_AF5                     0x5
 126 #define STM_AFR_AF6                     0x6
 127 #define STM_AFR_AF7                     0x7
 128
 129 static inline void
 130 stm_afr_set(struct stm_gpio *gpio, int pin, uint32_t value) {
 131         /*
 132          * Set alternate pin mode too
 133          */
 134         stm_moder_set(gpio, pin, STM_MODER_ALTERNATE);
 135         if (pin < 8)
 136                 gpio->afrl = ((gpio->afrl &
 137                                ~(STM_AFR_MASK << STM_AFR_SHIFT(pin))) |
 138                               value << STM_AFR_SHIFT(pin));
 139         else {
 140                 pin -= 8;
 141                 gpio->afrh = ((gpio->afrh &
 142                                ~(STM_AFR_MASK << STM_AFR_SHIFT(pin))) |
 143                               value << STM_AFR_SHIFT(pin));
 144         }
 145 }
 146
 147 static inline uint32_t
 148 stm_afr_get(struct stm_gpio *gpio, int pin) {
 149         if (pin < 8)
 150                 return (gpio->afrl >> STM_AFR_SHIFT(pin)) & STM_AFR_MASK;
 151         else {
 152                 pin -= 8;
 153                 return (gpio->afrh >> STM_AFR_SHIFT(pin)) & STM_AFR_MASK;
 154         }
 155 }
 156
 157 static inline void
 158 stm_gpio_set(struct stm_gpio *gpio, int pin, uint8_t value) {
 159         /* Use the bit set/reset register to do this atomically */
 160         gpio->bsrr = ((uint32_t) (value ^ 1) << (pin + 16)) | ((uint32_t) value << pin);
 161 }
 162
 163 static inline uint8_t
 164 stm_gpio_get(struct stm_gpio *gpio, int pin) {
 165         return (gpio->idr >> pin) & 1;
 166 }
 167
 168 static inline uint16_t
 169 stm_gpio_get_all(struct stm_gpio *gpio) {
 170         return gpio->idr;
 171 }
 172
 173 /*
 174  * We can't define these in registers.ld or our fancy
 175  * ao_enable_gpio macro will expand into a huge pile of code
 176  * as the compiler won't do correct constant folding and
 177  * dead-code elimination
 178  */
 179
 180 extern struct stm_gpio stm_gpioa;
 181 extern struct stm_gpio stm_gpiob;
 182 extern struct stm_gpio stm_gpioc;
 183 extern struct stm_gpio stm_gpiof;
 184
 185 #define stm_gpiof  (*((struct stm_gpio *) 0x48001400))
 186 #define stm_gpioc  (*((struct stm_gpio *) 0x48000800))
 187 #define stm_gpiob  (*((struct stm_gpio *) 0x48000400))
 188 #define stm_gpioa  (*((struct stm_gpio *) 0x48000000))
 189
 190 /* Flash interface */
 191
 192 struct stm_flash {
 193         vuint32_t       acr;
 194         vuint32_t       keyr;
 195         vuint32_t       optkeyr;
 196         vuint32_t       sr;
 197
 198         vuint32_t       cr;
 199         vuint32_t       ar;
 200         vuint32_t       unused_0x18;
 201         vuint32_t       obr;
 202
 203         vuint32_t       wrpr;
 204 };
 205
 206 extern struct stm_flash stm_flash;
 207
 208 #define STM_FLASH_ACR_PRFTBS    (5)
 209 #define STM_FLASH_ACR_PRFTBE    (4)
 210 #define STM_FLASH_ACR_LATENCY   (0)
 211 #define  STM_FLASH_ACR_LATENCY_0                0
 212 #define  STM_FLASH_ACR_LATENCY_1                1
 213
 214 #define STM_FLASH_PECR_OBL_LAUNCH       18
 215 #define STM_FLASH_PECR_ERRIE            17
 216 #define STM_FLASH_PECR_EOPIE            16
 217 #define STM_FLASH_PECR_FPRG             10
 218 #define STM_FLASH_PECR_ERASE            9
 219 #define STM_FLASH_PECR_FTDW             8
 220 #define STM_FLASH_PECR_DATA             4
 221 #define STM_FLASH_PECR_PROG             3
 222 #define STM_FLASH_PECR_OPTLOCK          2
 223 #define STM_FLASH_PECR_PRGLOCK          1
 224 #define STM_FLASH_PECR_PELOCK           0
 225
 226 #define STM_FLASH_SR_EOP                5
 227 #define STM_FLASH_SR_WRPRTERR           4
 228 #define STM_FLASH_SR_PGERR              2
 229 #define STM_FLASH_SR_BSY                0
 230
 231 #define STM_FLASH_CR_OBL_LAUNCH         13
 232 #define STM_FLASH_CR_EOPIE              12
 233 #define STM_FLASH_CR_ERRIE              10
 234 #define STM_FLASH_CR_OPTWRE             9
 235 #define STM_FLASH_CR_LOCK               7
 236 #define STM_FLASH_CR_STRT               6
 237 #define STM_FLASH_CR_OPTER              5
 238 #define STM_FLASH_CR_OPTPG              4
 239 #define STM_FLASH_CR_MER                2
 240 #define STM_FLASH_CR_PER                1
 241 #define STM_FLASH_CR_PG                 0
 242
 243 #define STM_FLASH_OBR_DATA1             24
 244 #define STM_FLASH_OBR_DATA0             16
 245 #define STM_FLASH_OBR_BOOT_SEL          15
 246 #define STM_FLASH_OBR_RAM_PARITY_CHECK  14
 247 #define STM_FLASH_OBR_VDDA_MONITOR      13
 248 #define STM_FLASH_OBR_NBOOT1            12
 249 #define STM_FLASH_OBR_NBOOT0            11
 250 #define STM_FLASH_OBR_NRST_STDBY        10
 251 #define STM_FLASH_OBR_NRST_STOP         9
 252 #define STM_FLASH_OBR_WDG_SW            8
 253 #define STM_FLASH_OBR_RDPRT             1
 254 #define  STM_FLASH_OBR_RDPRT_LEVEL0             0
 255 #define  STM_FLASH_OBR_RDPRT_LEVEL1             1
 256 #define  STM_FLASH_OBR_RDPRT_LEVEL2             3
 257 #define STM_FLASH_OBR_OPTERR            0
 258
 259 #define STM_FLASH_KEYR_KEY1     0x45670123
 260 #define STM_FLASH_KEYR_KEY2     0xcdef89ab
 261
 262 struct stm_rcc {
 263         vuint32_t       cr;
 264         vuint32_t       cfgr;
 265         vuint32_t       cir;
 266         vuint32_t       apb2rstr;
 267
 268         vuint32_t       apb1rstr;
 269         vuint32_t       ahbenr;
 270         vuint32_t       apb2enr;
 271         vuint32_t       apb1enr;
 272
 273         vuint32_t       bdcr;
 274         vuint32_t       csr;
 275         vuint32_t       ahbrstr;
 276         vuint32_t       cfgr2;
 277
 278         vuint32_t       cfgr3;
 279         vuint32_t       cr2;
 280 };
 281
 282 extern struct stm_rcc stm_rcc;
 283
 284 /* Nominal high speed internal oscillator frequency is 16MHz */
 285 #define STM_HSI_FREQ            16000000
 286
 287 #define STM_RCC_CR_PLLRDY       (25)
 288 #define STM_RCC_CR_PLLON        (24)
 289 #define STM_RCC_CR_CSSON        (19)
 290 #define STM_RCC_CR_HSEBYP       (18)
 291 #define STM_RCC_CR_HSERDY       (17)
 292 #define STM_RCC_CR_HSEON        (16)
 293 #define STM_RCC_CR_HSICAL       (8)
 294 #define STM_RCC_CR_HSITRIM      (3)
 295 #define STM_RCC_CR_HSIRDY       (1)
 296 #define STM_RCC_CR_HSION        (0)
 297
 298 #define STM_RCC_CFGR_PLL_NODIV  (31)
 299 #define  STM_RCC_CFGR_PLL_NODIV_DIV_1   1
 300 #define  STM_RCC_CFGR_PLL_NODIV_DIV_2   0
 301
 302 #define STM_RCC_CFGR_MCOPRE     (28)
 303 #define  STM_RCC_CFGR_MCOPRE_DIV_1      0
 304 #define  STM_RCC_CFGR_MCOPRE_DIV_2      1
 305 #define  STM_RCC_CFGR_MCOPRE_DIV_4      2
 306 #define  STM_RCC_CFGR_MCOPRE_DIV_8      3
 307 #define  STM_RCC_CFGR_MCOPRE_DIV_16     4
 308 #define  STM_RCC_CFGR_MCOPRE_DIV_32     5
 309 #define  STM_RCC_CFGR_MCOPRE_DIV_64     6
 310 #define  STM_RCC_CFGR_MCOPRE_DIV_128    7
 311 #define  STM_RCC_CFGR_MCOPRE_DIV_MASK   7
 312
 313 #define STM_RCC_CFGR_MCO        (24)
 314 # define STM_RCC_CFGR_MCO_DISABLE       0
 315
 316 #define STM_RCC_CFGR_PLLMUL     (18)
 317 #define  STM_RCC_CFGR_PLLMUL_2          0
 318 #define  STM_RCC_CFGR_PLLMUL_3          1
 319 #define  STM_RCC_CFGR_PLLMUL_4          2
 320 #define  STM_RCC_CFGR_PLLMUL_5          3
 321 #define  STM_RCC_CFGR_PLLMUL_6          4
 322 #define  STM_RCC_CFGR_PLLMUL_7          5
 323 #define  STM_RCC_CFGR_PLLMUL_8          6
 324 #define  STM_RCC_CFGR_PLLMUL_9          7
 325 #define  STM_RCC_CFGR_PLLMUL_10         8
 326 #define  STM_RCC_CFGR_PLLMUL_11         9
 327 #define  STM_RCC_CFGR_PLLMUL_12         10
 328 #define  STM_RCC_CFGR_PLLMUL_13         11
 329 #define  STM_RCC_CFGR_PLLMUL_14         12
 330 #define  STM_RCC_CFGR_PLLMUL_15         13
 331 #define  STM_RCC_CFGR_PLLMUL_16         14
 332 #define  STM_RCC_CFGR_PLLMUL_MASK       0xf
 333
 334 #define STM_RCC_CFGR_PLLXTPRE   (17)
 335
 336 #define STM_RCC_CFGR_PLLSRC     (15)
 337 # define STM_RCC_CFGR_PLLSRC_HSI_DIV_2  0
 338 # define STM_RCC_CFGR_PLLSRC_HSI        1
 339 # define STM_RCC_CFGR_PLLSRC_HSE        2
 340 # define STM_RCC_CFGR_PLLSRC_HSI48      3
 341
 342 #define STM_RCC_CFGR_ADCPRE     (14)
 343
 344 #define STM_RCC_CFGR_PPRE       (8)
 345 #define  STM_RCC_CFGR_PPRE_DIV_1        0
 346 #define  STM_RCC_CFGR_PPRE_DIV_2        4
 347 #define  STM_RCC_CFGR_PPRE_DIV_4        5
 348 #define  STM_RCC_CFGR_PPRE_DIV_8        6
 349 #define  STM_RCC_CFGR_PPRE_DIV_16       7
 350 #define  STM_RCC_CFGR_PPRE_MASK         7
 351
 352 #define STM_RCC_CFGR_HPRE       (4)
 353 #define  STM_RCC_CFGR_HPRE_DIV_1        0
 354 #define  STM_RCC_CFGR_HPRE_DIV_2        8
 355 #define  STM_RCC_CFGR_HPRE_DIV_4        9
 356 #define  STM_RCC_CFGR_HPRE_DIV_8        0xa
 357 #define  STM_RCC_CFGR_HPRE_DIV_16       0xb
 358 #define  STM_RCC_CFGR_HPRE_DIV_64       0xc
 359 #define  STM_RCC_CFGR_HPRE_DIV_128      0xd
 360 #define  STM_RCC_CFGR_HPRE_DIV_256      0xe
 361 #define  STM_RCC_CFGR_HPRE_DIV_512      0xf
 362 #define  STM_RCC_CFGR_HPRE_MASK         0xf
 363
 364 #define STM_RCC_CFGR_SWS        (2)
 365 #define  STM_RCC_CFGR_SWS_HSI           0
 366 #define  STM_RCC_CFGR_SWS_HSE           1
 367 #define  STM_RCC_CFGR_SWS_PLL           2
 368 #define  STM_RCC_CFGR_SWS_HSI48         3
 369 #define  STM_RCC_CFGR_SWS_MASK          3
 370
 371 #define STM_RCC_CFGR_SW         (0)
 372 #define  STM_RCC_CFGR_SW_HSI            0
 373 #define  STM_RCC_CFGR_SW_HSE            1
 374 #define  STM_RCC_CFGR_SW_PLL            2
 375 #define  STM_RCC_CFGR_SW_HSI48          3
 376 #define  STM_RCC_CFGR_SW_MASK           3
 377
 378 #define STM_RCC_APB2RSTR_DBGMCURST      22
 379 #define STM_RCC_APB2RSTR_TIM17RST       18
 380 #define STM_RCC_APB2RSTR_TIM16RST       17
 381 #define STM_RCC_APB2RSTR_TIM15RST       16
 382 #define STM_RCC_APB2RSTR_USART1RST      14
 383 #define STM_RCC_APB2RSTR_SPI1RST        12
 384 #define STM_RCC_APB2RSTR_TIM1RST        11
 385 #define STM_RCC_APB2RSTR_ADCRST         9
 386 #define STM_RCC_APB2RSTR_USART8RST      7
 387 #define STM_RCC_APB2RSTR_USART7RST      6
 388 #define STM_RCC_APB2RSTR_USART6RST      5
 389 #define STM_RCC_APB2RSTR_SYSCFGRST      1
 390
 391 #define STM_RCC_APB1RSTR_CECRST         30
 392 #define STM_RCC_APB1RSTR_DACRST         29
 393 #define STM_RCC_APB1RSTR_PWRRST         28
 394 #define STM_RCC_APB1RSTR_CRSRST         27
 395 #define STM_RCC_APB1RSTR_CANRST         25
 396 #define STM_RCC_APB1RSTR_USBRST         23
 397 #define STM_RCC_APB1RSTR_I2C2RST        22
 398 #define STM_RCC_APB1RSTR_I1C1RST        21
 399 #define STM_RCC_APB1RSTR_USART5RST      20
 400 #define STM_RCC_APB1RSTR_USART4RST      19
 401 #define STM_RCC_APB1RSTR_USART3RST      18
 402 #define STM_RCC_APB1RSTR_USART2RST      17
 403 #define STM_RCC_APB1RSTR_SPI2RST        14
 404 #define STM_RCC_APB1RSTR_WWDGRST        11
 405 #define STM_RCC_APB1RSTR_TIM14RST       8
 406 #define STM_RCC_APB1RSTR_TIM7RST        5
 407 #define STM_RCC_APB1RSTR_TIM6RST        4
 408 #define STM_RCC_APB1RSTR_TIM3RST        1
 409 #define STM_RCC_APB1RSTR_TIM2RST        0
 410
 411 #define STM_RCC_AHBENR_TSCEN    24
 412 #define STM_RCC_AHBENR_IOPFEN   22
 413 #define STM_RCC_AHBENR_IOPEEN   21
 414 #define STM_RCC_AHBENR_IOPDEN   20
 415 #define STM_RCC_AHBENR_IOPCEN   19
 416 #define STM_RCC_AHBENR_IOPBEN   18
 417 #define STM_RCC_AHBENR_IOPAEN   17
 418 #define STM_RCC_AHBENR_CRCEN    6
 419 #define STM_RCC_AHBENR_FLITFEN  4
 420 #define STM_RCC_AHBENR_SRAMEN   2
 421 #define STM_RCC_AHBENR_DMA2EN   1
 422 #define STM_RCC_AHBENR_DMAEN    0
 423
 424 #define STM_RCC_APB2ENR_DBGMCUEN        22
 425 #define STM_RCC_APB2ENR_TIM17EN         18
 426 #define STM_RCC_APB2ENR_TIM16EN         17
 427 #define STM_RCC_APB2ENR_TIM15EN         16
 428 #define STM_RCC_APB2ENR_USART1EN        14
 429 #define STM_RCC_APB2ENR_SPI1EN          12
 430 #define STM_RCC_APB2ENR_TIM1EN          11
 431 #define STM_RCC_APB2ENR_ADCEN           9
 432 #define STM_RCC_APB2ENR_USART8EN        7
 433 #define STM_RCC_APB2ENR_USART7EN        6
 434 #define STM_RCC_APB2ENR_USART6EN        5
 435 #define STM_RCC_APB2ENR_SYSCFGCOMPEN    0
 436
 437 #define STM_RCC_APB1ENR_CECEN           30
 438 #define STM_RCC_APB1ENR_DACEN           29
 439 #define STM_RCC_APB1ENR_PWREN           28
 440 #define STM_RCC_APB1ENR_CRSEN           27
 441 #define STM_RCC_APB1ENR_CANEN           25
 442 #define STM_RCC_APB1ENR_USBEN           23
 443 #define STM_RCC_APB1ENR_I2C2EN          22
 444 #define STM_RCC_APB1ENR_IC21EN          21
 445 #define STM_RCC_APB1ENR_USART5EN        20
 446 #define STM_RCC_APB1ENR_USART4EN        19
 447 #define STM_RCC_APB1ENR_USART3EN        18
 448 #define STM_RCC_APB1ENR_USART2EN        17
 449 #define STM_RCC_APB1ENR_SPI2EN          14
 450 #define STM_RCC_APB1ENR_WWDGEN          11
 451 #define STM_RCC_APB1ENR_TIM14EN         8
 452 #define STM_RCC_APB1ENR_TIM7EN          5
 453 #define STM_RCC_APB1ENR_TIM6EN          4
 454 #define STM_RCC_APB1ENR_TIM3EN          1
 455 #define STM_RCC_APB1ENR_TIM2EN          0
 456
 457 #define STM_RCC_CSR_LPWRRSTF            (31)
 458 #define STM_RCC_CSR_WWDGRSTF            (30)
 459 #define STM_RCC_CSR_IWDGRSTF            (29)
 460 #define STM_RCC_CSR_SFTRSTF             (28)
 461 #define STM_RCC_CSR_PORRSTF             (27)
 462 #define STM_RCC_CSR_PINRSTF             (26)
 463 #define STM_RCC_CSR_OBLRSTF             (25)
 464 #define STM_RCC_CSR_RMVF                (24)
 465 #define STM_RCC_CSR_V18PWRRSTF          (23)
 466 #define STM_RCC_CSR_LSIRDY              (1)
 467 #define STM_RCC_CSR_LSION               (0)
 468
 469 #define STM_RCC_CR2_HSI48CAL            24
 470 #define STM_RCC_CR2_HSI48RDY            17
 471 #define STM_RCC_CR2_HSI48ON             16
 472 #define STM_RCC_CR2_HSI14CAL            8
 473 #define STM_RCC_CR2_HSI14TRIM           3
 474 #define STM_RCC_CR2_HSI14DIS            2
 475 #define STM_RCC_CR2_HSI14RDY            1
 476 #define STM_RCC_CR2_HSI14ON             0
 477
 478 #define STM_RCC_CFGR3_USART3SW          18
 479 #define STM_RCC_CFGR3_USART2SW          16
 480 #define STM_RCC_CFGR3_ADCSW             8
 481 #define STM_RCC_CFGR3_USBSW             7
 482 #define STM_RCC_CFGR3_CECSW             6
 483 #define STM_RCC_CFGR3_I2C1SW            4
 484 #define STM_RCC_CFGR3_USART1SW          0
 485
 486 struct stm_crs {
 487         vuint32_t       cr;
 488         vuint32_t       cfgr;
 489         vuint32_t       isr;
 490         vuint32_t       icr;
 491 };
 492
 493 extern struct stm_crs stm_crs;
 494
 495 #define STM_CRS_CR_TRIM         8
 496 #define STM_CRS_CR_SWSYNC       7
 497 #define STM_CRS_CR_AUTOTRIMEN   6
 498 #define STM_CRS_CR_CEN          5
 499 #define STM_CRS_CR_ESYNCIE      3
 500 #define STM_CRS_CR_ERRIE        2
 501 #define STM_CRS_CR_SYNCWARNIE   1
 502 #define STM_CRS_CR_SYNCOKIE     0
 503
 504 #define STM_CRS_CFGR_SYNCPOL    31
 505 #define STM_CRS_CFGR_SYNCSRC    28
 506 #define  STM_CRS_CFGR_SYNCSRC_GPIO      0
 507 #define  STM_CRS_CFGR_SYNCSRC_LSE       1
 508 #define  STM_CRS_CFGR_SYNCSRC_USB       2
 509 #define STM_CRS_CFGR_SYNCDIV    24
 510 #define  STM_CRS_CFGR_SYNCDIV_1         0
 511 #define  STM_CRS_CFGR_SYNCDIV_2         1
 512 #define  STM_CRS_CFGR_SYNCDIV_4         2
 513 #define  STM_CRS_CFGR_SYNCDIV_8         3
 514 #define  STM_CRS_CFGR_SYNCDIV_16        4
 515 #define  STM_CRS_CFGR_SYNCDIV_32        5
 516 #define  STM_CRS_CFGR_SYNCDIV_64        6
 517 #define  STM_CRS_CFGR_SYNCDIV_128       7
 518 #define STM_CRS_CFGR_FELIM      16
 519 #define STM_CRS_CFGR_RELOAD     0
 520
 521 #define STM_CRS_ISR_FECAP       16
 522 #define STM_CRS_ISR_FEDIR       15
 523 #define STM_CRS_ISR_TRIMOVF     10
 524 #define STM_CRS_ISR_SYNCMISS    9
 525 #define STM_CRS_ISR_SYNCERR     8
 526 #define STM_CRS_ISR_ESYNCF      3
 527 #define STM_CRS_ISR_ERRF        2
 528 #define STM_CRS_ISR_SYNCWARNF   1
 529 #define STM_CRS_ISR_SYNCOKF     0
 530
 531 #define STM_CRS_ICR_ESYNCC      3
 532 #define STM_CRS_ICR_ERRC        2
 533 #define STM_CRS_ICR_SYNCWARNC   1
 534 #define STM_CRS_ICR_SYNCOKC     0
 535
 536 struct stm_pwr {
 537         vuint32_t       cr;
 538         vuint32_t       csr;
 539 };
 540
 541 extern struct stm_pwr stm_pwr;
 542
 543 #define STM_PWR_CR_DBP          (8)
 544
 545 #define STM_PWR_CR_PLS          (5)
 546 #define  STM_PWR_CR_PLS_2_0     0
 547 #define  STM_PWR_CR_PLS_2_1     1
 548 #define  STM_PWR_CR_PLS_2_2     2
 549 #define  STM_PWR_CR_PLS_2_3     3
 550 #define  STM_PWR_CR_PLS_2_4     4
 551 #define  STM_PWR_CR_PLS_2_5     5
 552 #define  STM_PWR_CR_PLS_2_6     6
 553 #define  STM_PWR_CR_PLS_EXT     7
 554 #define  STM_PWR_CR_PLS_MASK    7
 555
 556 #define STM_PWR_CR_PVDE         (4)
 557 #define STM_PWR_CR_CSBF         (3)
 558 #define STM_PWR_CR_CWUF         (2)
 559 #define STM_PWR_CR_PDDS         (1)
 560 #define STM_PWR_CR_LPSDSR       (0)
 561
 562 #define STM_PWR_CSR_EWUP3       (10)
 563 #define STM_PWR_CSR_EWUP2       (9)
 564 #define STM_PWR_CSR_EWUP1       (8)
 565 #define STM_PWR_CSR_REGLPF      (5)
 566 #define STM_PWR_CSR_VOSF        (4)
 567 #define STM_PWR_CSR_VREFINTRDYF (3)
 568 #define STM_PWR_CSR_PVDO        (2)
 569 #define STM_PWR_CSR_SBF         (1)
 570 #define STM_PWR_CSR_WUF         (0)
 571
 572 struct stm_crc {
 573         union {
 574                 vuint32_t       u32;
 575                 vuint16_t       u16;
 576                 vuint8_t        u8;
 577         }               dr;
 578         vuint32_t       idr;
 579         vuint32_t       cr;
 580         uint32_t        _0c;
 581
 582         vuint32_t       init;
 583         vuint32_t       pol;
 584 };
 585
 586 extern struct stm_crc   stm_crc;
 587
 588 #define stm_crc (*((struct stm_crc *) 0x40023000))
 589
 590 #define STM_CRC_CR_REV_OUT      7
 591 #define STM_CRC_CR_REV_IN       5
 592 #define  STM_CRC_CR_REV_IN_NONE         0
 593 #define  STM_CRC_CR_REV_IN_BY_BYTE      1
 594 #define  STM_CRC_CR_REV_IN_BY_HALF_WORD 2
 595 #define  STM_CRC_CR_REV_IN_BY_WORD      3
 596 #define STM_CRC_CR_POLYSIZE     3
 597 #define  STM_CRC_CR_POLYSIZE_32         0
 598 #define  STM_CRC_CR_POLYSIZE_16         1
 599 #define  STM_CRC_CR_POLYSIZE_8          2
 600 #define  STM_CRC_CR_POLYSIZE_7          3
 601 #define STM_CRC_CR_RESET        0
 602
 603 /* The SYSTICK starts at 0xe000e010 */
 604
 605 struct stm_systick {
 606         vuint32_t       csr;
 607         vuint32_t       rvr;
 608         vuint32_t       cvr;
 609         vuint32_t       calib;
 610 };
 611
 612 extern struct stm_systick stm_systick;
 613
 614 #define STM_SYSTICK_CSR_ENABLE          0
 615 #define STM_SYSTICK_CSR_TICKINT         1
 616 #define STM_SYSTICK_CSR_CLKSOURCE       2
 617 #define  STM_SYSTICK_CSR_CLKSOURCE_EXTERNAL             0
 618 #define  STM_SYSTICK_CSR_CLKSOURCE_HCLK_8               1
 619 #define STM_SYSTICK_CSR_COUNTFLAG       16
 620
 621 /* The NVIC starts at 0xe000e100, so add that to the offsets to find the absolute address */
 622
 623 struct stm_nvic {
 624         vuint32_t       iser;           /* 0x000 0xe000e100 Set Enable Register */
 625
 626         uint8_t         _unused020[0x080 - 0x004];
 627
 628         vuint32_t       icer;           /* 0x080 0xe000e180 Clear Enable Register */
 629
 630         uint8_t         _unused0a0[0x100 - 0x084];
 631
 632         vuint32_t       ispr;           /* 0x100 0xe000e200 Set Pending Register */
 633
 634         uint8_t         _unused120[0x180 - 0x104];
 635
 636         vuint32_t       icpr;           /* 0x180 0xe000e280 Clear Pending Register */
 637
 638         uint8_t         _unused1a0[0x300 - 0x184];
 639
 640         vuint32_t       ipr[8];         /* 0x300 0xe000e400 Priority Register */
 641 };
 642
 643 extern struct stm_nvic stm_nvic;
 644
 645 #define IRQ_MASK(irq)   (1 << (irq))
 646 #define IRQ_BOOL(v,irq) (((v) >> (irq)) & 1)
 647
 648 static inline void
 649 stm_nvic_set_enable(int irq) {
 650         stm_nvic.iser = IRQ_MASK(irq);
 651 }
 652
 653 static inline void
 654 stm_nvic_clear_enable(int irq) {
 655         stm_nvic.icer = IRQ_MASK(irq);
 656 }
 657
 658 static inline int
 659 stm_nvic_enabled(int irq) {
 660         return IRQ_BOOL(stm_nvic.iser, irq);
 661 }
 662
 663 static inline void
 664 stm_nvic_set_pending(int irq) {
 665         stm_nvic.ispr = IRQ_MASK(irq);
 666 }
 667
 668 static inline void
 669 stm_nvic_clear_pending(int irq) {
 670         stm_nvic.icpr = IRQ_MASK(irq);
 671 }
 672
 673 static inline int
 674 stm_nvic_pending(int irq) {
 675         return IRQ_BOOL(stm_nvic.ispr, irq);
 676 }
 677
 678 #define IRQ_PRIO_REG(irq)       ((irq) >> 2)
 679 #define IRQ_PRIO_BIT(irq)       (((irq) & 3) << 3)
 680 #define IRQ_PRIO_MASK(irq)      (0xff << IRQ_PRIO_BIT(irq))
 681
 682 static inline void
 683 stm_nvic_set_priority(int irq, uint8_t prio) {
 684         int             n = IRQ_PRIO_REG(irq);
 685         uint32_t        v;
 686
 687         v = stm_nvic.ipr[n];
 688         v &= ~IRQ_PRIO_MASK(irq);
 689         v |= (prio) << IRQ_PRIO_BIT(irq);
 690         stm_nvic.ipr[n] = v;
 691 }
 692
 693 static inline uint8_t
 694 stm_nvic_get_priority(int irq) {
 695         return (stm_nvic.ipr[IRQ_PRIO_REG(irq)] >> IRQ_PRIO_BIT(irq)) & IRQ_PRIO_MASK(0);
 696 }
 697
 698 struct stm_scb {
 699         vuint32_t       cpuid;
 700         vuint32_t       icsr;
 701         vuint32_t       vtor;
 702         vuint32_t       aircr;
 703
 704         vuint32_t       scr;
 705         vuint32_t       ccr;
 706         vuint32_t       shpr1;
 707         vuint32_t       shpr2;
 708
 709         vuint32_t       shpr3;
 710         vuint32_t       shcrs;
 711         vuint32_t       cfsr;
 712         vuint32_t       hfsr;
 713
 714         uint32_t        unused_30;
 715         vuint32_t       mmfar;
 716         vuint32_t       bfar;
 717 };
 718
 719 extern struct stm_scb stm_scb;
 720
 721 #define STM_SCB_AIRCR_VECTKEY           16
 722 #define  STM_SCB_AIRCR_VECTKEY_KEY              0x05fa
 723 #define STM_SCB_AIRCR_PRIGROUP          8
 724 #define STM_SCB_AIRCR_SYSRESETREQ       2
 725 #define STM_SCB_AIRCR_VECTCLRACTIVE     1
 726 #define STM_SCB_AIRCR_VECTRESET         0
 727
 728 #define isr(name) void stm_ ## name ## _isr(void);
 729
 730 isr(nmi)
 731 isr(hardfault)
 732 isr(memmanage)
 733 isr(busfault)
 734 isr(usagefault)
 735 isr(svc)
 736 isr(debugmon)
 737 isr(pendsv)
 738 isr(systick)
 739 isr(wwdg)
 740 isr(pvd)
 741 isr(tamper_stamp)
 742 isr(rtc_wkup)
 743 isr(flash)
 744 isr(rcc)
 745 isr(exti0)
 746 isr(exti1)
 747 isr(exti2)
 748 isr(exti3)
 749 isr(exti4)
 750 isr(dma1_channel1)
 751 isr(dma1_channel2)
 752 isr(dma1_channel3)
 753 isr(dma1_channel4)
 754 isr(dma1_channel5)
 755 isr(dma1_channel6)
 756 isr(dma1_channel7)
 757 isr(adc1)
 758 isr(usb_hp)
 759 isr(usb_lp)
 760 isr(dac)
 761 isr(comp)
 762 isr(exti9_5)
 763 isr(lcd)
 764 isr(tim9)
 765 isr(tim10)
 766 isr(tim11)
 767 isr(tim2)
 768 isr(tim3)
 769 isr(tim4)
 770 isr(i2c1_ev)
 771 isr(i2c1_er)
 772 isr(i2c2_ev)
 773 isr(i2c2_er)
 774 isr(spi1)
 775 isr(spi2)
 776 isr(usart1)
 777 isr(usart2)
 778 isr(usart3)
 779 isr(exti15_10)
 780 isr(rtc_alarm)
 781 isr(usb_fs_wkup)
 782 isr(tim6)
 783 isr(tim7)
 784
 785 #undef isr
 786
 787 #define STM_ISR_WWDG_POS                0
 788 #define STM_ISR_PVD_VDDIO2_POS          1
 789 #define STM_ISR_RTC_POS                 2
 790 #define STM_ISR_FLASH_POS               3
 791 #define STM_ISR_RCC_CRS_POS             4
 792 #define STM_ISR_EXTI0_1_POS             5
 793 #define STM_ISR_EXTI2_3_POS             6
 794 #define STM_ISR_EXTI4_15_POS            7
 795 #define STM_ISR_TSC_POS                 8
 796 #define STM_ISR_DMA_CH1_POS             9
 797 #define STM_ISR_DMA_CH2_3_DMA2_CH1_2_POS        10
 798 #define STM_ISR_DMA_CH44_5_6_7_DMA2_CH3_4_5_POS 11
 799 #define STM_ISR_ADC_COMP_POS            12
 800 #define STM_ISR_TIM1_BRK_UP_TRG_COM_POS 13
 801 #define STM_ISR_TIM1_CC_POS             14
 802 #define STM_ISR_TIM2_POS                15
 803 #define STM_ISR_TIM3_POS                16
 804 #define STM_ISR_TIM6_DAC_POS            17
 805 #define STM_ISR_TIM7_POS                18
 806 #define STM_ISR_TIM14_POS               19
 807 #define STM_ISR_TIM15_POS               20
 808 #define STM_ISR_TIM16_POS               21
 809 #define STM_ISR_TIM17_POS               22
 810 #define STM_ISR_I2C1_POS                23
 811 #define STM_ISR_I2C2_POS                24
 812 #define STM_ISR_SPI1_POS                25
 813 #define STM_ISR_SPI2_POS                26
 814 #define STM_ISR_USART1_POS              27
 815 #define STM_ISR_USART2_POS              28
 816 #define STM_ISR_UASART3_4_5_6_7_8_POS   29
 817 #define STM_ISR_CEC_CAN_POS             30
 818 #define STM_ISR_USB_POS                 31
 819
 820 struct stm_syscfg {
 821         vuint32_t       cfgr1;
 822         vuint32_t       exticr[4];
 823         vuint32_t       cfgr2;
 824 };
 825
 826 extern struct stm_syscfg stm_syscfg;
 827
 828 #define STM_SYSCFG_CFGR1_TIM3_DMA_RMP   30
 829 #define STM_SYSCFG_CFGR1_TIM2_DMA_RMP   29
 830 #define STM_SYSCFG_CFGR1_TIM1_DMA_RMP   28
 831 #define STM_SYSCFG_CFGR1_I2C1_DMA_RMP   27
 832 #define STM_SYSCFG_CFGR1_USART3_DMA_RMP 26
 833 #define STM_SYSCFG_CFGR1_USART2_DMA_RMP 25
 834 #define STM_SYSCFG_CFGR1_SPI2_DMA_RMP   24
 835 #define STM_SYSCFG_CFGR1_I2C_PA10_FMP   23
 836 #define STM_SYSCFG_CFGR1_I2C_PA9_FMP    22
 837 #define STM_SYSCFG_CFGR1_I2C2_FMP       21
 838 #define STM_SYSCFG_CFGR1_I2C1_FMP       20
 839 #define STM_SYSCFG_CFGR1_I2C_PB9_FMP    19
 840 #define STM_SYSCFG_CFGR1_I2C_PB8_FMP    18
 841 #define STM_SYSCFG_CFGR1_I2C_PB7_FMP    17
 842 #define STM_SYSCFG_CFGR1_I2C_PB6_FMP    16
 843 #define STM_SYSCFG_CFGR1_TIM17_DMA_RMP2 14
 844 #define STM_SYSCFG_CFGR1_TIM16_DMA_RMP2 13
 845 #define STM_SYSCFG_CFGR1_TIM17_DMA_RMP  12
 846 #define STM_SYSCFG_CFGR1_TIM16_DMA_RMP  11
 847 #define STM_SYSCFG_CFGR1_USART1_RX_DMA_RMP      10
 848 #define STM_SYSCFG_CFGR1_USART1_TX_DMA_RMP      9
 849 #define STM_SYSCFG_CFGR1_ADC_DMA_RMP            8
 850 #define STM_SYSCFG_CFGR1_IRDA_ENV_SEL   6
 851 #define  STM_SYSCFG_CFGR1_IRDA_ENV_SEL_TIMER16  0
 852 #define  STM_SYSCFG_CFGR1_IRDA_ENV_SEL_USART1   1
 853 #define  STM_SYSCFG_CFGR1_IRDA_ENV_SEL_USART4   2
 854 #define STM_SYSCFG_CFGR1_PA11_PA12_RMP  4
 855 #define STM_SYSCFG_CFGR1_MEM_MODE       0
 856 #define  STM_SYSCFG_CFGR1_MEM_MODE_MAIN_FLASH   0
 857 #define  STM_SYSCFG_CFGR1_MEM_MODE_SYSTEM_FLASH 1
 858 #define  STM_SYSCFG_CFGR1_MEM_MODE_SRAM         3
 859 #define  STM_SYSCFG_CFGR1_MEM_MODE_MASK         3
 860
 861 #if 0
 862 static inline void
 863 stm_exticr_set(struct stm_gpio *gpio, int pin) {
 864         uint8_t reg = pin >> 2;
 865         uint8_t shift = (pin & 3) << 2;
 866         uint8_t val = 0;
 867
 868         /* Enable SYSCFG */
 869         stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_SYSCFGCOMPEN);
 870
 871         if (gpio == &stm_gpioa)
 872                 val = STM_SYSCFG_EXTICR_PA;
 873         else if (gpio == &stm_gpiob)
 874                 val = STM_SYSCFG_EXTICR_PB;
 875         else if (gpio == &stm_gpioc)
 876                 val = STM_SYSCFG_EXTICR_PC;
 877         else if (gpio == &stm_gpiof)
 878                 val = STM_SYSCFG_EXTICR_PF;
 879
 880         stm_syscfg.exticr[reg] = (stm_syscfg.exticr[reg] & ~(0xf << shift)) | val << shift;
 881 }
 882 #endif
 883
 884
 885 struct stm_dma_channel {
 886         vuint32_t       ccr;
 887         vuint32_t       cndtr;
 888         vvoid_t         cpar;
 889         vvoid_t         cmar;
 890         vuint32_t       reserved;
 891 };
 892
 893 #define STM_NUM_DMA     6
 894
 895 struct stm_dma {
 896         vuint32_t               isr;
 897         vuint32_t               ifcr;
 898         struct stm_dma_channel  channel[STM_NUM_DMA];
 899 };
 900
 901 extern struct stm_dma stm_dma;
 902
 903 /* DMA channels go from 1 to 6, instead of 0 to 5 (sigh)
 904  */
 905
 906 #define STM_DMA_INDEX(channel)          ((channel) - 1)
 907
 908 #define STM_DMA_ISR(index)              ((index) << 2)
 909 #define STM_DMA_ISR_MASK                        0xf
 910 #define STM_DMA_ISR_TEIF                        3
 911 #define STM_DMA_ISR_HTIF                        2
 912 #define STM_DMA_ISR_TCIF                        1
 913 #define STM_DMA_ISR_GIF                         0
 914
 915 #define STM_DMA_IFCR(index)             ((index) << 2)
 916 #define STM_DMA_IFCR_MASK                       0xf
 917 #define STM_DMA_IFCR_CTEIF                      3
 918 #define STM_DMA_IFCR_CHTIF                      2
 919 #define STM_DMA_IFCR_CTCIF                      1
 920 #define STM_DMA_IFCR_CGIF                       0
 921
 922 #define STM_DMA_CCR_MEM2MEM             (14)
 923
 924 #define STM_DMA_CCR_PL                  (12)
 925 #define  STM_DMA_CCR_PL_LOW                     (0)
 926 #define  STM_DMA_CCR_PL_MEDIUM                  (1)
 927 #define  STM_DMA_CCR_PL_HIGH                    (2)
 928 #define  STM_DMA_CCR_PL_VERY_HIGH               (3)
 929 #define  STM_DMA_CCR_PL_MASK                    (3)
 930
 931 #define STM_DMA_CCR_MSIZE               (10)
 932 #define  STM_DMA_CCR_MSIZE_8                    (0)
 933 #define  STM_DMA_CCR_MSIZE_16                   (1)
 934 #define  STM_DMA_CCR_MSIZE_32                   (2)
 935 #define  STM_DMA_CCR_MSIZE_MASK                 (3)
 936
 937 #define STM_DMA_CCR_PSIZE               (8)
 938 #define  STM_DMA_CCR_PSIZE_8                    (0)
 939 #define  STM_DMA_CCR_PSIZE_16                   (1)
 940 #define  STM_DMA_CCR_PSIZE_32                   (2)
 941 #define  STM_DMA_CCR_PSIZE_MASK                 (3)
 942
 943 #define STM_DMA_CCR_MINC                (7)
 944 #define STM_DMA_CCR_PINC                (6)
 945 #define STM_DMA_CCR_CIRC                (5)
 946 #define STM_DMA_CCR_DIR                 (4)
 947 #define  STM_DMA_CCR_DIR_PER_TO_MEM             0
 948 #define  STM_DMA_CCR_DIR_MEM_TO_PER             1
 949 #define STM_DMA_CCR_TEIE                (3)
 950 #define STM_DMA_CCR_HTIE                (2)
 951 #define STM_DMA_CCR_TCIE                (1)
 952 #define STM_DMA_CCR_EN                  (0)
 953
 954 /* DMA channel assignments. When a peripheral has multiple channels
 955  * (indicated with _<number>), then it can be configured to either
 956  * channel using syscfg.cfgr1
 957  */
 958
 959 #define STM_DMA_CHANNEL_ADC_1           1
 960 #define STM_DMA_CHANNEL_ADC_2           2
 961
 962 #define STM_DMA_CHANNEL_SPI1_RX         2
 963 #define STM_DMA_CHANNEL_SPI1_TX         3
 964
 965 #define STM_DMA_CHANNEL_SPI2_RX         4
 966 #define STM_DMA_CHANNEL_SPI2_TX         5
 967
 968 #define STM_DMA_CHANNEL_USART1_TX_1     2
 969 #define STM_DMA_CHANNEL_USART1_RX_1     3
 970 #define STM_DMA_CHANNEL_USART1_TX_2     4
 971 #define STM_DMA_CHANNEL_USART1_RX_2     5
 972
 973 #define STM_DMA_CHANNEL_USART2_RX       4
 974 #define STM_DMA_CHANNEL_USART2_TX       5
 975
 976 #define STM_DMA_CHANNEL_I2C1_TX         2
 977 #define STM_DMA_CHANNEL_I2C1_RX         3
 978
 979 #define STM_DMA_CHANNEL_I2C2_TX         4
 980 #define STM_DMA_CHANNEL_I2C2_RX         5
 981
 982 #define STM_DMA_CHANNEL_TIM1_CH1        2
 983 #define STM_DMA_CHANNEL_TIM1_CH2        3
 984 #define STM_DMA_CHANNEL_TIM1_CH4        4
 985 #define STM_DMA_CHANNEL_TIM1_TRIG       4
 986 #define STM_DMA_CHANNEL_TIM1_COM        4
 987 #define STM_DMA_CHANNEL_TIM1_CH3        5
 988 #define STM_DMA_CHANNEL_TIM1_UP         5
 989
 990 #define STM_DMA_CHANNEL_TIM2_CH3        1
 991 #define STM_DMA_CHANNEL_TIM2_UP         2
 992 #define STM_DMA_CHANNEL_TIM2_CH2        3
 993 #define STM_DMA_CHANNEL_TIM2_CH4        4
 994 #define STM_DMA_CHANNEL_TIM2_CH1        5
 995
 996 #define STM_DMA_CHANNEL_TIM3_CH3        2
 997 #define STM_DMA_CHANNEL_TIM3_CH4        3
 998 #define STM_DMA_CHANNEL_TIM3_UP         3
 999 #define STM_DMA_CHANNEL_TIM3_CH1        4
1000 #define STM_DMA_CHANNEL_TIM3_TRIG       4
1001
1002 #define STM_DMA_CHANNEL_TIM6_UP_DAC     2
1003
1004 #define STM_DMA_CHANNEL_TIM15_CH1       5
1005 #define STM_DMA_CHANNEL_TIM15_UP        5
1006 #define STM_DMA_CHANNEL_TIM15_TRIG      5
1007 #define STM_DMA_CHANNEL_TIM15_COM       5
1008
1009 #define STM_DMA_CHANNEL_TIM16_CH1_1     3
1010 #define STM_DMA_CHANNEL_TIM16_UP_1      3
1011 #define STM_DMA_CHANNEL_TIM16_CH1_2     4
1012 #define STM_DMA_CHANNEL_TIM16_UP_2      4
1013
1014 #define STM_DMA_CHANNEL_TIM17_CH1_1     1
1015 #define STM_DMA_CHANNEL_TIM17_UP_1      1
1016 #define STM_DMA_CHANNEL_TIM17_CH1_2     2
1017 #define STM_DMA_CHANNEL_TIM17_UP_2      2
1018
1019 /*
1020  * Only spi channel 1 and 2 can use DMA
1021  */
1022 #define STM_NUM_SPI     2
1023
1024 struct stm_spi {
1025         vuint32_t       cr1;
1026         vuint32_t       cr2;
1027         vuint32_t       sr;
1028         vuint32_t       dr;
1029         vuint32_t       crcpr;
1030         vuint32_t       rxcrcr;
1031         vuint32_t       txcrcr;
1032 };
1033
1034 extern struct stm_spi stm_spi1, stm_spi2, stm_spi3;
1035
1036 /* SPI channels go from 1 to 3, instead of 0 to 2 (sigh)
1037  */
1038
1039 #define STM_SPI_INDEX(channel)          ((channel) - 1)
1040
1041 #define STM_SPI_CR1_BIDIMODE            15
1042 #define STM_SPI_CR1_BIDIOE              14
1043 #define STM_SPI_CR1_CRCEN               13
1044 #define STM_SPI_CR1_CRCNEXT             12
1045 #define STM_SPI_CR1_DFF                 11
1046 #define STM_SPI_CR1_RXONLY              10
1047 #define STM_SPI_CR1_SSM                 9
1048 #define STM_SPI_CR1_SSI                 8
1049 #define STM_SPI_CR1_LSBFIRST            7
1050 #define STM_SPI_CR1_SPE                 6
1051 #define STM_SPI_CR1_BR                  3
1052 #define  STM_SPI_CR1_BR_PCLK_2                  0
1053 #define  STM_SPI_CR1_BR_PCLK_4                  1
1054 #define  STM_SPI_CR1_BR_PCLK_8                  2
1055 #define  STM_SPI_CR1_BR_PCLK_16                 3
1056 #define  STM_SPI_CR1_BR_PCLK_32                 4
1057 #define  STM_SPI_CR1_BR_PCLK_64                 5
1058 #define  STM_SPI_CR1_BR_PCLK_128                6
1059 #define  STM_SPI_CR1_BR_PCLK_256                7
1060 #define  STM_SPI_CR1_BR_MASK                    7
1061
1062 #define STM_SPI_CR1_MSTR                2
1063 #define STM_SPI_CR1_CPOL                1
1064 #define STM_SPI_CR1_CPHA                0
1065
1066 #define STM_SPI_CR2_TXEIE       7
1067 #define STM_SPI_CR2_RXNEIE      6
1068 #define STM_SPI_CR2_ERRIE       5
1069 #define STM_SPI_CR2_SSOE        2
1070 #define STM_SPI_CR2_TXDMAEN     1
1071 #define STM_SPI_CR2_RXDMAEN     0
1072
1073 #define STM_SPI_SR_BSY          7
1074 #define STM_SPI_SR_OVR          6
1075 #define STM_SPI_SR_MODF         5
1076 #define STM_SPI_SR_CRCERR       4
1077 #define STM_SPI_SR_TXE          1
1078 #define STM_SPI_SR_RXNE         0
1079
1080 struct stm_adc {
1081         vuint32_t       isr;
1082         vuint32_t       ier;
1083         vuint32_t       cr;
1084         vuint32_t       cfgr1;
1085
1086         vuint32_t       cfgr2;
1087         vuint32_t       smpr;
1088         vuint32_t       r_18;
1089         vuint32_t       r_1c;
1090
1091         vuint32_t       tr;
1092         vuint32_t       r_24;
1093         vuint32_t       chselr;
1094         vuint32_t       r_2c;
1095
1096         vuint32_t       r_30[4];
1097
1098         vuint32_t       dr;
1099
1100         uint8_t         r_44[0x308 - 0x44];
1101         vuint32_t       ccr;
1102 };
1103
1104 extern struct stm_adc stm_adc;
1105
1106 #define STM_ADC_ISR_AWD         7
1107 #define STM_ADC_ISR_OVR         4
1108 #define STM_ADC_ISR_EOSEQ       3
1109 #define STM_ADC_ISR_EOC         2
1110 #define STM_ADC_ISR_EOSMP       1
1111 #define STM_ADC_ISR_ADRDY       0
1112
1113 #define STM_ADC_IER_AWDIE       7
1114 #define STM_ADC_IER_OVRIE       4
1115 #define STM_ADC_IER_EOSEQIE     3
1116 #define STM_ADC_IER_EOCIE       2
1117 #define STM_ADC_IER_EOSMPIE     1
1118 #define STM_ADC_IER_ADRDYIE     0
1119
1120 #define STM_ADC_CR_ADCAL        31
1121 #define STM_ADC_CR_ADSTP        4
1122 #define STM_ADC_CR_ADSTART      2
1123 #define STM_ADC_CR_ADDIS        1
1124 #define STM_ADC_CR_ADEN         0
1125
1126 #define STM_ADC_CFGR1_AWDCH     26
1127 #define STM_ADC_CFGR1_AWDEN     23
1128 #define STM_ADC_CFGR1_AWDSGL    22
1129 #define STM_ADC_CFGR1_DISCEN    16
1130 #define STM_ADC_CFGR1_AUTOOFF   15
1131 #define STM_ADC_CFGR1_WAIT      14
1132 #define STM_ADC_CFGR1_CONT      13
1133 #define STM_ADC_CFGR1_OVRMOD    12
1134 #define STM_ADC_CFGR1_EXTEN     10
1135 #define  STM_ADC_CFGR1_EXTEN_DISABLE    0
1136 #define  STM_ADC_CFGR1_EXTEN_RISING     1
1137 #define  STM_ADC_CFGR1_EXTEN_FALLING    2
1138 #define  STM_ADC_CFGR1_EXTEN_BOTH       3
1139 #define  STM_ADC_CFGR1_EXTEN_MASK       3
1140
1141 #define STM_ADC_CFGR1_EXTSEL    6
1142 #define STM_ADC_CFGR1_ALIGN     5
1143 #define STM_ADC_CFGR1_RES       3
1144 #define  STM_ADC_CFGR1_RES_12           0
1145 #define  STM_ADC_CFGR1_RES_10           1
1146 #define  STM_ADC_CFGR1_RES_8            2
1147 #define  STM_ADC_CFGR1_RES_6            3
1148 #define  STM_ADC_CFGR1_RES_MASK         3
1149 #define STM_ADC_CFGR1_SCANDIR   2
1150 #define  STM_ADC_CFGR1_SCANDIR_UP       0
1151 #define  STM_ADC_CFGR1_SCANDIR_DOWN     1
1152 #define STM_ADC_CFGR1_DMACFG    1
1153 #define  STM_ADC_CFGR1_DMACFG_ONESHOT   0
1154 #define  STM_ADC_CFGR1_DMACFG_CIRCULAR  1
1155 #define STM_ADC_CFGR1_DMAEN     0
1156
1157 #define STM_ADC_CFGR2_CKMODE    30
1158 #define  STM_ADC_CFGR2_CKMODE_ADCCLK    0
1159 #define  STM_ADC_CFGR2_CKMODE_PCLK_2    1
1160 #define  STM_ADC_CFGR2_CKMODE_PCLK_4    2
1161
1162 #define STM_ADC_SMPR_SMP        0
1163 #define  STM_ADC_SMPR_SMP_1_5           0
1164 #define  STM_ADC_SMPR_SMP_7_5           1
1165 #define  STM_ADC_SMPR_SMP_13_5          2
1166 #define  STM_ADC_SMPR_SMP_28_5          3
1167 #define  STM_ADC_SMPR_SMP_41_5          4
1168 #define  STM_ADC_SMPR_SMP_55_5          5
1169 #define  STM_ADC_SMPR_SMP_71_5          6
1170 #define  STM_ADC_SMPR_SMP_239_5         7
1171
1172 #define STM_ADC_TR_HT           16
1173 #define STM_ADC_TR_LT           0
1174
1175 #define STM_ADC_CCR_VBATEN      24
1176 #define STM_ADC_CCR_TSEN        23
1177 #define STM_ADC_CCR_VREFEN      22
1178
1179 struct stm_cal {
1180         uint16_t        ts_cal_cold;    /* 30°C */
1181         uint16_t        vrefint_cal;
1182         uint16_t        unused_c0;
1183         uint16_t        ts_cal_hot;     /* 110°C */
1184 };
1185
1186 extern struct stm_cal   stm_cal;
1187
1188 #define stm_temp_cal_cold       30
1189 #define stm_temp_cal_hot        110
1190
1191 struct stm_dbgmcu {
1192         uint32_t        idcode;
1193 };
1194
1195 extern struct stm_dbgmcu        stm_dbgmcu;
1196
1197 static inline uint16_t
1198 stm_dev_id(void) {
1199         return stm_dbgmcu.idcode & 0xfff;
1200 }
1201
1202 struct stm_flash_size {
1203         uint16_t        f_size;
1204 };
1205
1206 extern struct stm_flash_size    stm_flash_size_04x;
1207
1208 /* Returns flash size in bytes */
1209 extern uint32_t
1210 stm_flash_size(void);
1211
1212 struct stm_device_id {
1213         uint32_t        u_id0;
1214         uint32_t        u_id1;
1215         uint32_t        u_id2;
1216 };
1217
1218 extern struct stm_device_id     stm_device_id;
1219
1220 #define STM_NUM_I2C     2
1221
1222 #define STM_I2C_INDEX(channel)  ((channel) - 1)
1223
1224 struct stm_i2c {
1225         vuint32_t       cr1;
1226         vuint32_t       cr2;
1227         vuint32_t       oar1;
1228         vuint32_t       oar2;
1229         vuint32_t       dr;
1230         vuint32_t       sr1;
1231         vuint32_t       sr2;
1232         vuint32_t       ccr;
1233         vuint32_t       trise;
1234 };
1235
1236 extern struct stm_i2c stm_i2c1, stm_i2c2;
1237
1238 #define STM_I2C_CR1_SWRST       15
1239 #define STM_I2C_CR1_ALERT       13
1240 #define STM_I2C_CR1_PEC         12
1241 #define STM_I2C_CR1_POS         11
1242 #define STM_I2C_CR1_ACK         10
1243 #define STM_I2C_CR1_STOP        9
1244 #define STM_I2C_CR1_START       8
1245 #define STM_I2C_CR1_NOSTRETCH   7
1246 #define STM_I2C_CR1_ENGC        6
1247 #define STM_I2C_CR1_ENPEC       5
1248 #define STM_I2C_CR1_ENARP       4
1249 #define STM_I2C_CR1_SMBTYPE     3
1250 #define STM_I2C_CR1_SMBUS       1
1251 #define STM_I2C_CR1_PE          0
1252
1253 #define STM_I2C_CR2_LAST        12
1254 #define STM_I2C_CR2_DMAEN       11
1255 #define STM_I2C_CR2_ITBUFEN     10
1256 #define STM_I2C_CR2_ITEVTEN     9
1257 #define STM_I2C_CR2_ITERREN     8
1258 #define STM_I2C_CR2_FREQ        0
1259 #define  STM_I2C_CR2_FREQ_2_MHZ         2
1260 #define  STM_I2C_CR2_FREQ_4_MHZ         4
1261 #define  STM_I2C_CR2_FREQ_8_MHZ         8
1262 #define  STM_I2C_CR2_FREQ_16_MHZ        16
1263 #define  STM_I2C_CR2_FREQ_32_MHZ        32
1264 #define  STM_I2C_CR2_FREQ_MASK          0x3f
1265
1266 #define STM_I2C_SR1_SMBALERT    15
1267 #define STM_I2C_SR1_TIMEOUT     14
1268 #define STM_I2C_SR1_PECERR      12
1269 #define STM_I2C_SR1_OVR         11
1270 #define STM_I2C_SR1_AF          10
1271 #define STM_I2C_SR1_ARLO        9
1272 #define STM_I2C_SR1_BERR        8
1273 #define STM_I2C_SR1_TXE         7
1274 #define STM_I2C_SR1_RXNE        6
1275 #define STM_I2C_SR1_STOPF       4
1276 #define STM_I2C_SR1_ADD10       3
1277 #define STM_I2C_SR1_BTF         2
1278 #define STM_I2C_SR1_ADDR        1
1279 #define STM_I2C_SR1_SB          0
1280
1281 #define STM_I2C_SR2_PEC         8
1282 #define  STM_I2C_SR2_PEC_MASK   0xff00
1283 #define STM_I2C_SR2_DUALF       7
1284 #define STM_I2C_SR2_SMBHOST     6
1285 #define STM_I2C_SR2_SMBDEFAULT  5
1286 #define STM_I2C_SR2_GENCALL     4
1287 #define STM_I2C_SR2_TRA         2
1288 #define STM_I2C_SR2_BUSY        1
1289 #define STM_I2C_SR2_MSL         0
1290
1291 #define STM_I2C_CCR_FS          15
1292 #define STM_I2C_CCR_DUTY        14
1293 #define STM_I2C_CCR_CCR         0
1294 #define  STM_I2C_CCR_MASK       0x7ff
1295
1296 struct stm_tim234 {
1297         vuint32_t       cr1;
1298         vuint32_t       cr2;
1299         vuint32_t       smcr;
1300         vuint32_t       dier;
1301
1302         vuint32_t       sr;
1303         vuint32_t       egr;
1304         vuint32_t       ccmr1;
1305         vuint32_t       ccmr2;
1306
1307         vuint32_t       ccer;
1308         vuint32_t       cnt;
1309         vuint32_t       psc;
1310         vuint32_t       arr;
1311
1312         uint32_t        reserved_30;
1313         vuint32_t       ccr1;
1314         vuint32_t       ccr2;
1315         vuint32_t       ccr3;
1316
1317         vuint32_t       ccr4;
1318         uint32_t        reserved_44;
1319         vuint32_t       dcr;
1320         vuint32_t       dmar;
1321
1322         uint32_t        reserved_50;
1323 };
1324
1325 extern struct stm_tim234 stm_tim2, stm_tim3, stm_tim4;
1326
1327 #define STM_TIM234_CR1_CKD      8
1328 #define  STM_TIM234_CR1_CKD_1           0
1329 #define  STM_TIM234_CR1_CKD_2           1
1330 #define  STM_TIM234_CR1_CKD_4           2
1331 #define  STM_TIM234_CR1_CKD_MASK        3
1332 #define STM_TIM234_CR1_ARPE     7
1333 #define STM_TIM234_CR1_CMS      5
1334 #define  STM_TIM234_CR1_CMS_EDGE        0
1335 #define  STM_TIM234_CR1_CMS_CENTER_1    1
1336 #define  STM_TIM234_CR1_CMS_CENTER_2    2
1337 #define  STM_TIM234_CR1_CMS_CENTER_3    3
1338 #define  STM_TIM234_CR1_CMS_MASK        3
1339 #define STM_TIM234_CR1_DIR      4
1340 #define  STM_TIM234_CR1_DIR_UP          0
1341 #define  STM_TIM234_CR1_DIR_DOWN        1
1342 #define STM_TIM234_CR1_OPM      3
1343 #define STM_TIM234_CR1_URS      2
1344 #define STM_TIM234_CR1_UDIS     1
1345 #define STM_TIM234_CR1_CEN      0
1346
1347 #define STM_TIM234_CR2_TI1S     7
1348 #define STM_TIM234_CR2_MMS      4
1349 #define  STM_TIM234_CR2_MMS_RESET               0
1350 #define  STM_TIM234_CR2_MMS_ENABLE              1
1351 #define  STM_TIM234_CR2_MMS_UPDATE              2
1352 #define  STM_TIM234_CR2_MMS_COMPARE_PULSE       3
1353 #define  STM_TIM234_CR2_MMS_COMPARE_OC1REF      4
1354 #define  STM_TIM234_CR2_MMS_COMPARE_OC2REF      5
1355 #define  STM_TIM234_CR2_MMS_COMPARE_OC3REF      6
1356 #define  STM_TIM234_CR2_MMS_COMPARE_OC4REF      7
1357 #define  STM_TIM234_CR2_MMS_MASK                7
1358 #define STM_TIM234_CR2_CCDS     3
1359
1360 #define STM_TIM234_SMCR_ETP     15
1361 #define STM_TIM234_SMCR_ECE     14
1362 #define STM_TIM234_SMCR_ETPS    12
1363 #define  STM_TIM234_SMCR_ETPS_OFF               0
1364 #define  STM_TIM234_SMCR_ETPS_DIV_2             1
1365 #define  STM_TIM234_SMCR_ETPS_DIV_4             2
1366 #define  STM_TIM234_SMCR_ETPS_DIV_8             3
1367 #define  STM_TIM234_SMCR_ETPS_MASK              3
1368 #define STM_TIM234_SMCR_ETF     8
1369 #define  STM_TIM234_SMCR_ETF_NONE               0
1370 #define  STM_TIM234_SMCR_ETF_INT_N_2            1
1371 #define  STM_TIM234_SMCR_ETF_INT_N_4            2
1372 #define  STM_TIM234_SMCR_ETF_INT_N_8            3
1373 #define  STM_TIM234_SMCR_ETF_DTS_2_N_6          4
1374 #define  STM_TIM234_SMCR_ETF_DTS_2_N_8          5
1375 #define  STM_TIM234_SMCR_ETF_DTS_4_N_6          6
1376 #define  STM_TIM234_SMCR_ETF_DTS_4_N_8          7
1377 #define  STM_TIM234_SMCR_ETF_DTS_8_N_6          8
1378 #define  STM_TIM234_SMCR_ETF_DTS_8_N_8          9
1379 #define  STM_TIM234_SMCR_ETF_DTS_16_N_5         10
1380 #define  STM_TIM234_SMCR_ETF_DTS_16_N_6         11
1381 #define  STM_TIM234_SMCR_ETF_DTS_16_N_8         12
1382 #define  STM_TIM234_SMCR_ETF_DTS_32_N_5         13
1383 #define  STM_TIM234_SMCR_ETF_DTS_32_N_6         14
1384 #define  STM_TIM234_SMCR_ETF_DTS_32_N_8         15
1385 #define  STM_TIM234_SMCR_ETF_MASK               15
1386 #define STM_TIM234_SMCR_MSM     7
1387 #define STM_TIM234_SMCR_TS      4
1388 #define  STM_TIM234_SMCR_TS_ITR0                0
1389 #define  STM_TIM234_SMCR_TS_ITR1                1
1390 #define  STM_TIM234_SMCR_TS_ITR2                2
1391 #define  STM_TIM234_SMCR_TS_ITR3                3
1392 #define  STM_TIM234_SMCR_TS_TI1F_ED             4
1393 #define  STM_TIM234_SMCR_TS_TI1FP1              5
1394 #define  STM_TIM234_SMCR_TS_TI2FP2              6
1395 #define  STM_TIM234_SMCR_TS_ETRF                7
1396 #define  STM_TIM234_SMCR_TS_MASK                7
1397 #define STM_TIM234_SMCR_OCCS    3
1398 #define STM_TIM234_SMCR_SMS     0
1399 #define  STM_TIM234_SMCR_SMS_DISABLE            0
1400 #define  STM_TIM234_SMCR_SMS_ENCODER_MODE_1     1
1401 #define  STM_TIM234_SMCR_SMS_ENCODER_MODE_2     2
1402 #define  STM_TIM234_SMCR_SMS_ENCODER_MODE_3     3
1403 #define  STM_TIM234_SMCR_SMS_RESET_MODE         4
1404 #define  STM_TIM234_SMCR_SMS_GATED_MODE         5
1405 #define  STM_TIM234_SMCR_SMS_TRIGGER_MODE       6
1406 #define  STM_TIM234_SMCR_SMS_EXTERNAL_CLOCK     7
1407 #define  STM_TIM234_SMCR_SMS_MASK               7
1408
1409 #define STM_TIM234_SR_CC4OF     12
1410 #define STM_TIM234_SR_CC3OF     11
1411 #define STM_TIM234_SR_CC2OF     10
1412 #define STM_TIM234_SR_CC1OF     9
1413 #define STM_TIM234_SR_TIF       6
1414 #define STM_TIM234_SR_CC4IF     4
1415 #define STM_TIM234_SR_CC3IF     3
1416 #define STM_TIM234_SR_CC2IF     2
1417 #define STM_TIM234_SR_CC1IF     1
1418 #define STM_TIM234_SR_UIF       0
1419
1420 #define STM_TIM234_EGR_TG       6
1421 #define STM_TIM234_EGR_CC4G     4
1422 #define STM_TIM234_EGR_CC3G     3
1423 #define STM_TIM234_EGR_CC2G     2
1424 #define STM_TIM234_EGR_CC1G     1
1425 #define STM_TIM234_EGR_UG       0
1426
1427 #define STM_TIM234_CCMR1_OC2CE  15
1428 #define STM_TIM234_CCMR1_OC2M   12
1429 #define  STM_TIM234_CCMR1_OC2M_FROZEN                   0
1430 #define  STM_TIM234_CCMR1_OC2M_SET_HIGH_ON_MATCH        1
1431 #define  STM_TIM234_CCMR1_OC2M_SET_LOW_ON_MATCH         2
1432 #define  STM_TIM234_CCMR1_OC2M_TOGGLE                   3
1433 #define  STM_TIM234_CCMR1_OC2M_FORCE_LOW                4
1434 #define  STM_TIM234_CCMR1_OC2M_FORCE_HIGH               5
1435 #define  STM_TIM234_CCMR1_OC2M_PWM_MODE_1               6
1436 #define  STM_TIM234_CCMR1_OC2M_PWM_MODE_2               7
1437 #define  STM_TIM234_CCMR1_OC2M_MASK                     7
1438 #define STM_TIM234_CCMR1_OC2PE  11
1439 #define STM_TIM234_CCMR1_OC2FE  10
1440 #define STM_TIM234_CCMR1_CC2S   8
1441 #define  STM_TIM234_CCMR1_CC2S_OUTPUT                   0
1442 #define  STM_TIM234_CCMR1_CC2S_INPUT_TI2                1
1443 #define  STM_TIM234_CCMR1_CC2S_INPUT_TI1                2
1444 #define  STM_TIM234_CCMR1_CC2S_INPUT_TRC                3
1445 #define  STM_TIM234_CCMR1_CC2S_MASK                     3
1446
1447 #define STM_TIM234_CCMR1_OC1CE  7
1448 #define STM_TIM234_CCMR1_OC1M   4
1449 #define  STM_TIM234_CCMR1_OC1M_FROZEN                   0
1450 #define  STM_TIM234_CCMR1_OC1M_SET_HIGH_ON_MATCH        1
1451 #define  STM_TIM234_CCMR1_OC1M_SET_LOW_ON_MATCH         2
1452 #define  STM_TIM234_CCMR1_OC1M_TOGGLE                   3
1453 #define  STM_TIM234_CCMR1_OC1M_FORCE_LOW                4
1454 #define  STM_TIM234_CCMR1_OC1M_FORCE_HIGH               5
1455 #define  STM_TIM234_CCMR1_OC1M_PWM_MODE_1               6
1456 #define  STM_TIM234_CCMR1_OC1M_PWM_MODE_2               7
1457 #define  STM_TIM234_CCMR1_OC1M_MASK                     7
1458 #define STM_TIM234_CCMR1_OC1PE  11
1459 #define STM_TIM234_CCMR1_OC1FE  2
1460 #define STM_TIM234_CCMR1_CC1S   0
1461 #define  STM_TIM234_CCMR1_CC1S_OUTPUT                   0
1462 #define  STM_TIM234_CCMR1_CC1S_INPUT_TI1                1
1463 #define  STM_TIM234_CCMR1_CC1S_INPUT_TI2                2
1464 #define  STM_TIM234_CCMR1_CC1S_INPUT_TRC                3
1465 #define  STM_TIM234_CCMR1_CC1S_MASK                     3
1466
1467 #define STM_TIM234_CCMR2_OC4CE  15
1468 #define STM_TIM234_CCMR2_OC4M   12
1469 #define  STM_TIM234_CCMR2_OC4M_FROZEN                   0
1470 #define  STM_TIM234_CCMR2_OC4M_SET_HIGH_ON_MATCH        1
1471 #define  STM_TIM234_CCMR2_OC4M_SET_LOW_ON_MATCH         2
1472 #define  STM_TIM234_CCMR2_OC4M_TOGGLE                   3
1473 #define  STM_TIM234_CCMR2_OC4M_FORCE_LOW                4
1474 #define  STM_TIM234_CCMR2_OC4M_FORCE_HIGH               5
1475 #define  STM_TIM234_CCMR2_OC4M_PWM_MODE_1               6
1476 #define  STM_TIM234_CCMR2_OC4M_PWM_MODE_2               7
1477 #define  STM_TIM234_CCMR2_OC4M_MASK                     7
1478 #define STM_TIM234_CCMR2_OC4PE  11
1479 #define STM_TIM234_CCMR2_OC4FE  10
1480 #define STM_TIM234_CCMR2_CC4S   8
1481 #define  STM_TIM234_CCMR2_CC4S_OUTPUT                   0
1482 #define  STM_TIM234_CCMR2_CC4S_INPUT_TI4                1
1483 #define  STM_TIM234_CCMR2_CC4S_INPUT_TI3                2
1484 #define  STM_TIM234_CCMR2_CC4S_INPUT_TRC                3
1485 #define  STM_TIM234_CCMR2_CC4S_MASK                     3
1486
1487 #define STM_TIM234_CCMR2_OC3CE  7
1488 #define STM_TIM234_CCMR2_OC3M   4
1489 #define  STM_TIM234_CCMR2_OC3M_FROZEN                   0
1490 #define  STM_TIM234_CCMR2_OC3M_SET_HIGH_ON_MATCH        1
1491 #define  STM_TIM234_CCMR2_OC3M_SET_LOW_ON_MATCH         2
1492 #define  STM_TIM234_CCMR2_OC3M_TOGGLE                   3
1493 #define  STM_TIM234_CCMR2_OC3M_FORCE_LOW                4
1494 #define  STM_TIM234_CCMR2_OC3M_FORCE_HIGH               5
1495 #define  STM_TIM234_CCMR2_OC3M_PWM_MODE_1               6
1496 #define  STM_TIM234_CCMR2_OC3M_PWM_MODE_2               7
1497 #define  STM_TIM234_CCMR2_OC3M_MASK                     7
1498 #define STM_TIM234_CCMR2_OC3PE  11
1499 #define STM_TIM234_CCMR2_OC3FE  2
1500 #define STM_TIM234_CCMR2_CC3S   0
1501 #define  STM_TIM234_CCMR2_CC3S_OUTPUT                   0
1502 #define  STM_TIM234_CCMR2_CC3S_INPUT_TI3                1
1503 #define  STM_TIM234_CCMR2_CC3S_INPUT_TI4                2
1504 #define  STM_TIM234_CCMR2_CC3S_INPUT_TRC                3
1505 #define  STM_TIM234_CCMR2_CC3S_MASK                     3
1506
1507 #define STM_TIM234_CCER_CC4NP   15
1508 #define STM_TIM234_CCER_CC4P    13
1509 #define STM_TIM234_CCER_CC4E    12
1510 #define STM_TIM234_CCER_CC3NP   11
1511 #define STM_TIM234_CCER_CC3P    9
1512 #define STM_TIM234_CCER_CC3E    8
1513 #define STM_TIM234_CCER_CC2NP   7
1514 #define STM_TIM234_CCER_CC2P    5
1515 #define STM_TIM234_CCER_CC2E    4
1516 #define STM_TIM234_CCER_CC1NP   3
1517 #define STM_TIM234_CCER_CC1P    1
1518 #define STM_TIM234_CCER_CC1E    0
1519
1520 struct stm_usb {
1521         struct {
1522                 vuint16_t       r;
1523                 uint16_t        _;
1524         } epr[8];
1525         uint8_t         reserved_20[0x40 - 0x20];
1526         vuint16_t       cntr;
1527         uint16_t        reserved_42;
1528         vuint16_t       istr;
1529         uint16_t        reserved_46;
1530         vuint16_t       fnr;
1531         uint16_t        reserved_4a;
1532         vuint16_t       daddr;
1533         uint16_t        reserved_4e;
1534         vuint16_t       btable;
1535         uint16_t        reserved_52;
1536         vuint16_t       lpmcsr;
1537         uint16_t        reserved_56;
1538         vuint16_t       bcdr;
1539         uint16_t        reserved_5a;
1540 };
1541
1542 extern struct stm_usb stm_usb;
1543
1544 #define STM_USB_EPR_CTR_RX      15
1545 #define  STM_USB_EPR_CTR_RX_WRITE_INVARIANT             1
1546 #define STM_USB_EPR_DTOG_RX     14
1547 #define STM_USB_EPR_DTOG_RX_WRITE_INVARIANT             0
1548 #define STM_USB_EPR_STAT_RX     12
1549 #define  STM_USB_EPR_STAT_RX_DISABLED                   0
1550 #define  STM_USB_EPR_STAT_RX_STALL                      1
1551 #define  STM_USB_EPR_STAT_RX_NAK                        2
1552 #define  STM_USB_EPR_STAT_RX_VALID                      3
1553 #define  STM_USB_EPR_STAT_RX_MASK                       3
1554 #define  STM_USB_EPR_STAT_RX_WRITE_INVARIANT            0
1555 #define STM_USB_EPR_SETUP       11
1556 #define STM_USB_EPR_EP_TYPE     9
1557 #define  STM_USB_EPR_EP_TYPE_BULK                       0
1558 #define  STM_USB_EPR_EP_TYPE_CONTROL                    1
1559 #define  STM_USB_EPR_EP_TYPE_ISO                        2
1560 #define  STM_USB_EPR_EP_TYPE_INTERRUPT                  3
1561 #define  STM_USB_EPR_EP_TYPE_MASK                       3
1562 #define STM_USB_EPR_EP_KIND     8
1563 #define  STM_USB_EPR_EP_KIND_DBL_BUF                    1       /* Bulk */
1564 #define  STM_USB_EPR_EP_KIND_STATUS_OUT                 1       /* Control */
1565 #define STM_USB_EPR_CTR_TX      7
1566 #define  STM_USB_CTR_TX_WRITE_INVARIANT                 1
1567 #define STM_USB_EPR_DTOG_TX     6
1568 #define  STM_USB_EPR_DTOG_TX_WRITE_INVARIANT            0
1569 #define STM_USB_EPR_STAT_TX     4
1570 #define  STM_USB_EPR_STAT_TX_DISABLED                   0
1571 #define  STM_USB_EPR_STAT_TX_STALL                      1
1572 #define  STM_USB_EPR_STAT_TX_NAK                        2
1573 #define  STM_USB_EPR_STAT_TX_VALID                      3
1574 #define  STM_USB_EPR_STAT_TX_WRITE_INVARIANT            0
1575 #define  STM_USB_EPR_STAT_TX_MASK                       3
1576 #define STM_USB_EPR_EA          0
1577 #define  STM_USB_EPR_EA_MASK                            0xf
1578
1579 #define STM_USB_CNTR_CTRM       15
1580 #define STM_USB_CNTR_PMAOVRM    14
1581 #define STM_USB_CNTR_ERRM       13
1582 #define STM_USB_CNTR_WKUPM      12
1583 #define STM_USB_CNTR_SUSPM      11
1584 #define STM_USB_CNTR_RESETM     10
1585 #define STM_USB_CNTR_SOFM       9
1586 #define STM_USB_CNTR_ESOFM      8
1587 #define STM_USB_CNTR_RESUME     4
1588 #define STM_USB_CNTR_FSUSP      3
1589 #define STM_USB_CNTR_LP_MODE    2
1590 #define STM_USB_CNTR_PDWN       1
1591 #define STM_USB_CNTR_FRES       0
1592
1593 #define STM_USB_ISTR_CTR        15
1594 #define STM_USB_ISTR_PMAOVR     14
1595 #define STM_USB_ISTR_ERR        13
1596 #define STM_USB_ISTR_WKUP       12
1597 #define STM_USB_ISTR_SUSP       11
1598 #define STM_USB_ISTR_RESET      10
1599 #define STM_USB_ISTR_SOF        9
1600 #define STM_USB_ISTR_ESOF       8
1601 #define STM_USB_L1REQ           7
1602 #define STM_USB_ISTR_DIR        4
1603 #define STM_USB_ISTR_EP_ID      0
1604 #define  STM_USB_ISTR_EP_ID_MASK                0xf
1605
1606 #define STM_USB_FNR_RXDP        15
1607 #define STM_USB_FNR_RXDM        14
1608 #define STM_USB_FNR_LCK         13
1609 #define STM_USB_FNR_LSOF        11
1610 #define  STM_USB_FNR_LSOF_MASK                  0x3
1611 #define STM_USB_FNR_FN          0
1612 #define  STM_USB_FNR_FN_MASK                    0x7ff
1613
1614 #define STM_USB_DADDR_EF        7
1615 #define STM_USB_DADDR_ADD       0
1616 #define  STM_USB_DADDR_ADD_MASK                 0x7f
1617
1618 #define STM_USB_BCDR_DPPU       15
1619 #define STM_USB_BCDR_PS2DET     7
1620 #define STM_USB_BCDR_SDET       6
1621 #define STM_USB_BCDR_PDET       5
1622 #define STM_USB_BCDR_DCDET      4
1623 #define STM_USB_BCDR_SDEN       3
1624 #define STM_USB_BCDR_PDEN       2
1625 #define STM_USB_BCDR_DCDEN      1
1626 #define STM_USB_BCDR_BCDEN      0
1627
1628 union stm_usb_bdt {
1629         struct {
1630                 vuint16_t       addr_tx;
1631                 vuint16_t       count_tx;
1632                 vuint16_t       addr_rx;
1633                 vuint16_t       count_rx;
1634         } single;
1635         struct {
1636                 vuint16_t       addr;
1637                 vuint16_t       count;
1638         } double_tx[2];
1639         struct {
1640                 vuint16_t       addr;
1641                 vuint16_t       count;
1642         } double_rx[2];
1643 };
1644
1645 #define STM_USB_BDT_COUNT_RX_BL_SIZE    15
1646 #define STM_USB_BDT_COUNT_RX_NUM_BLOCK  10
1647 #define  STM_USB_BDT_COUNT_RX_NUM_BLOCK_MASK    0x1f
1648 #define STM_USB_BDT_COUNT_RX_COUNT_RX   0
1649 #define  STM_USB_BDT_COUNT_RX_COUNT_RX_MASK     0x1ff
1650
1651 #define STM_USB_BDT_SIZE        8
1652
1653 extern uint8_t stm_usb_sram[];
1654
1655 struct stm_exti {
1656         vuint32_t       imr;
1657         vuint32_t       emr;
1658         vuint32_t       rtsr;
1659         vuint32_t       ftsr;
1660
1661         vuint32_t       swier;
1662         vuint32_t       pr;
1663 };
1664
1665 extern struct stm_exti stm_exti;
1666
1667 #endif /* _STM32F0_H_ */