git.gag.com Git - fw/altos/blob - src/stm32f4/ao_timer.c

   1 /*
   2  * Copyright © 2018 Keith Packard <keithp@keithp.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful, but
  10  * WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  12  * General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along
  15  * with this program; if not, write to the Free Software Foundation, Inc.,
  16  * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  17  */
  18
  19 #include "ao.h"
  20 #include <ao_task.h>
  21
  22 #ifndef HAS_TICK
  23 #define HAS_TICK 1
  24 #endif
  25
  26 #if HAS_TICK || defined(AO_TIMER_HOOK)
  27
  28 #if HAS_TICK
  29 volatile AO_TICK_TYPE ao_tick_count;
  30
  31 AO_TICK_TYPE
  32 ao_time(void)
  33 {
  34         return ao_tick_count;
  35 }
  36 #endif
  37
  38 #if AO_DATA_ALL
  39 volatile uint8_t        ao_data_interval = 1;
  40 volatile uint8_t        ao_data_count;
  41 #endif
  42
  43 void stm_systick_isr(void)
  44 {
  45         ao_validate_cur_stack();
  46         if (stm_systick.csr & (1 << STM_SYSTICK_CSR_COUNTFLAG)) {
  47 #if HAS_TICK
  48                 ++ao_tick_count;
  49 #endif
  50 #if HAS_TASK_QUEUE
  51                 if (ao_task_alarm_tick && (int16_t) (ao_tick_count - ao_task_alarm_tick) >= 0)
  52                         ao_task_check_alarm((uint16_t) ao_tick_count);
  53 #endif
  54 #if AO_DATA_ALL
  55                 if (++ao_data_count == ao_data_interval) {
  56                         ao_data_count = 0;
  57 #if HAS_FAKE_FLIGHT
  58                         if (ao_fake_flight_active)
  59                                 ao_fake_flight_poll();
  60                         else
  61 #endif
  62                                 ao_adc_poll();
  63 #if (AO_DATA_ALL & ~(AO_DATA_ADC))
  64                         ao_wakeup((void *) &ao_data_count);
  65 #endif
  66                 }
  67 #endif
  68 #ifdef AO_TIMER_HOOK
  69                 AO_TIMER_HOOK;
  70 #endif
  71         }
  72 }
  73
  74 #if HAS_ADC
  75 void
  76 ao_timer_set_adc_interval(uint8_t interval)
  77 {
  78         ao_arch_critical(
  79                 ao_data_interval = interval;
  80                 ao_data_count = 0;
  81                 );
  82 }
  83 #endif
  84
  85 #define SYSTICK_RELOAD ((AO_SYSTICK / 8) / 100 - 1)
  86
  87 void
  88 ao_timer_init(void)
  89 {
  90         stm_systick.rvr = SYSTICK_RELOAD;
  91         stm_systick.cvr = 0;
  92         stm_systick.csr = ((1 << STM_SYSTICK_CSR_ENABLE) |
  93                            (1 << STM_SYSTICK_CSR_TICKINT) |
  94                            (STM_SYSTICK_CSR_CLKSOURCE_AHB_8 << STM_SYSTICK_CSR_CLKSOURCE));
  95         stm_scb.shpr3 |= AO_STM_NVIC_CLOCK_PRIORITY << 24;
  96 }
  97
  98 #endif
  99
 100 void
 101 ao_clock_init(void)
 102 {
 103         uint32_t        cfgr;
 104         uint32_t        pllcfgr;
 105
 106         /* Switch to HSI while messing about */
 107         stm_rcc.cr |= (1 << STM_RCC_CR_HSION);
 108         while (!(stm_rcc.cr & (1 << STM_RCC_CR_HSIRDY)))
 109                 ao_arch_nop();
 110
 111         stm_rcc.cfgr = (stm_rcc.cfgr & ~(STM_RCC_CFGR_SW_MASK << STM_RCC_CFGR_SW)) |
 112                 (STM_RCC_CFGR_SW_HSI << STM_RCC_CFGR_SW);
 113
 114         /* wait for system to switch to HSI */
 115         while ((stm_rcc.cfgr & (STM_RCC_CFGR_SWS_MASK << STM_RCC_CFGR_SWS)) !=
 116                (STM_RCC_CFGR_SWS_HSI << STM_RCC_CFGR_SWS))
 117                 ao_arch_nop();
 118
 119         /* reset everything but the HSI selection and status */
 120         stm_rcc.cfgr &= (uint32_t)0x0000000f;
 121
 122         /* reset everything but HSI */
 123         stm_rcc.cr &= 0x0000ffff;
 124
 125         /* Disable and clear all interrupts */
 126         stm_rcc.cir = 0xffff0000;
 127
 128 #if AO_HSE
 129 #if AO_HSE_BYPASS
 130         stm_rcc.cr |= (1 << STM_RCC_CR_HSEBYP);
 131 #else
 132         stm_rcc.cr &= ~(1 << STM_RCC_CR_HSEBYP);
 133 #endif
 134         /* Enable HSE clock */
 135         stm_rcc.cr |= (1 << STM_RCC_CR_HSEON);
 136         while (!(stm_rcc.cr & (1 << STM_RCC_CR_HSERDY)))
 137                 asm("nop");
 138
 139 #endif
 140
 141         /* Set flash latency to tolerate SYSCLK */
 142
 143 #define FLASH_LATENCY   ((AO_SYSCLK - 1) / 25000000)
 144
 145         /* Enable icache, dcache and prefetch. Set latency */
 146         stm_flash.acr = ((1 << STM_FLASH_ACR_DCEN) |
 147                          (1 << STM_FLASH_ACR_ICEN) |
 148                          (1 << STM_FLASH_ACR_PRFTEN) |
 149                          (FLASH_LATENCY << STM_FLASH_ACR_LATENCY));
 150
 151         /* Enable power interface clock */
 152         stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_PWREN);
 153
 154 #if AO_SYSCLK <= 64000000
 155 #define VOS_SCALE_MODE  STM_PWR_CR_VOS_SCALE_MODE_1
 156 #elif AO_SYSCLK <= 84000000
 157 #define VOS_SCALE_MODE  STM_PWR_CR_VOS_SCALE_MODE_2
 158 #else
 159 #define VOS_SCALE_MODE  STM_PWR_CR_VOS_SCALE_MODE_1
 160 #endif
 161
 162         /* Set voltage scale mode */
 163         stm_pwr.cr = ((stm_pwr.cr & ~(STM_PWR_CR_VOS_SCALE_MODE_MASK)) |
 164                       (VOS_SCALE_MODE << STM_PWR_CR_VOS));
 165
 166         /* HCLK */
 167         cfgr = stm_rcc.cfgr;
 168         cfgr &= ~(STM_RCC_CFGR_HPRE_MASK << STM_RCC_CFGR_HPRE);
 169         cfgr |= (AO_RCC_CFGR_HPRE_DIV << STM_RCC_CFGR_HPRE);
 170         stm_rcc.cfgr = cfgr;
 171
 172         /* APB1 Prescaler = AO_APB1_PRESCALER */
 173         cfgr = stm_rcc.cfgr;
 174         cfgr &= ~(STM_RCC_CFGR_PPRE1_MASK << STM_RCC_CFGR_PPRE1);
 175         cfgr |= (AO_RCC_CFGR_PPRE1_DIV << STM_RCC_CFGR_PPRE1);
 176         stm_rcc.cfgr = cfgr;
 177
 178         /* APB2 Prescaler = AO_APB2_PRESCALER */
 179         cfgr = stm_rcc.cfgr;
 180         cfgr &= ~(STM_RCC_CFGR_PPRE2_MASK << STM_RCC_CFGR_PPRE2);
 181         cfgr |= (AO_RCC_CFGR_PPRE2_DIV << STM_RCC_CFGR_PPRE2);
 182         stm_rcc.cfgr = cfgr;
 183
 184         /* Clock configuration register DCKCFGR2; mostly make sure USB
 185          * gets clocked from PLL_Q
 186          */
 187         stm_rcc.dckcfgr2 = ((STM_RCC_DCKCFGR2_LPTIMER1SEL_APB << STM_RCC_DCKCFGR2_LPTIMER1SEL) |
 188                             (STM_RCC_DCKCFGR2_SDIOSEL_CK_48MHZ << STM_RCC_DCKCFGR2_SDIOSEL) |
 189                             (STM_RCC_DCKCFGR2_CK48MSEL_PLL_Q << STM_RCC_DCKCFGR2_CK48MSEL) |
 190                             (STM_RCC_DCKCFGR2_I2CFMP1SEL_APB << STM_RCC_DCKCFGR2_I2CFMP1SEL));
 191
 192         /* Disable the PLL */
 193         stm_rcc.cr &= ~(1 << STM_RCC_CR_PLLON);
 194         while (stm_rcc.cr & (1 << STM_RCC_CR_PLLRDY))
 195                 asm("nop");
 196
 197         /* PLL1VCO */
 198         pllcfgr = stm_rcc.pllcfgr;
 199         pllcfgr &= ~(STM_RCC_PLLCFGR_PLLM_MASK << STM_RCC_PLLCFGR_PLLM);
 200         pllcfgr &= ~(STM_RCC_PLLCFGR_PLLN_MASK << STM_RCC_PLLCFGR_PLLN);
 201         pllcfgr &= ~(STM_RCC_PLLCFGR_PLLP_MASK << STM_RCC_PLLCFGR_PLLP);
 202         pllcfgr &= ~(STM_RCC_PLLCFGR_PLLQ_MASK << STM_RCC_PLLCFGR_PLLQ);
 203         pllcfgr &= ~(STM_RCC_PLLCFGR_PLLR_MASK << STM_RCC_PLLCFGR_PLLR);
 204
 205         pllcfgr |= (AO_PLL_M << STM_RCC_PLLCFGR_PLLM);
 206         pllcfgr |= (AO_PLL1_N << STM_RCC_PLLCFGR_PLLN);
 207 #if AO_PLL1_P == 2
 208 #define AO_RCC_PLLCFGR_PLLP     STM_RCC_PLLCFGR_PLLP_DIV_2
 209 #endif
 210 #if AO_PLL1_P == 4
 211 #define AO_RCC_PLLCFGR_PLLP     STM_RCC_PLLCFGR_PLLP_DIV_4
 212 #endif
 213 #if AO_PLL1_P == 6
 214 #define AO_RCC_PLLCFGR_PLLP     STM_RCC_PLLCFGR_PLLP_DIV_6
 215 #endif
 216 #if AO_PLL1_P == 8
 217 #define AO_RCC_PLLCFGR_PLLP     STM_RCC_PLLCFGR_PLLP_DIV_8
 218 #endif
 219         pllcfgr |= (AO_RCC_PLLCFGR_PLLP << STM_RCC_PLLCFGR_PLLP);
 220         pllcfgr |= (AO_PLL1_Q << STM_RCC_PLLCFGR_PLLQ);
 221         pllcfgr |= (AO_PLL1_R << STM_RCC_PLLCFGR_PLLR);
 222         /* PLL source */
 223         pllcfgr &= ~(1 << STM_RCC_PLLCFGR_PLLSRC);
 224 #if AO_HSI
 225         pllcfgr |= (STM_RCC_PLLCFGR_PLLSRC_HSI << STM_RCC_PLLCFGR_PLLSRC);
 226 #endif
 227 #if AO_HSE
 228         pllcfgr |= (STM_RCC_PLLCFGR_PLLSRC_HSE << STM_RCC_PLLCFGR_PLLSRC);
 229 #endif
 230         stm_rcc.pllcfgr = pllcfgr;
 231
 232         /* Enable the PLL and wait for it */
 233         stm_rcc.cr |= (1 << STM_RCC_CR_PLLON);
 234         while (!(stm_rcc.cr & (1 << STM_RCC_CR_PLLRDY)))
 235                 asm("nop");
 236
 237         /* Switch to the PLL for the system clock */
 238
 239         cfgr = stm_rcc.cfgr;
 240         cfgr &= ~(STM_RCC_CFGR_SW_MASK << STM_RCC_CFGR_SW);
 241         cfgr |= (STM_RCC_CFGR_SW_PLL << STM_RCC_CFGR_SW);
 242         stm_rcc.cfgr = cfgr;
 243         for (;;) {
 244                 uint32_t        c, part, mask, val;
 245
 246                 c = stm_rcc.cfgr;
 247                 mask = (STM_RCC_CFGR_SWS_MASK << STM_RCC_CFGR_SWS);
 248                 val = (STM_RCC_CFGR_SWS_PLL << STM_RCC_CFGR_SWS);
 249                 part = c & mask;
 250                 if (part == val)
 251                         break;
 252         }
 253
 254 #if AO_HSE
 255         /* Disable HSI clock */
 256         stm_rcc.cr &= ~(1 << STM_RCC_CR_HSION);
 257 #endif
 258
 259         /* Clear reset flags */
 260         stm_rcc.csr |= (1 << STM_RCC_CSR_RMVF);
 261
 262 #if DEBUG_THE_CLOCK
 263         /* Output PLL clock on PA8 and SYCLK on PC9 for measurments */
 264
 265         stm_rcc.ahb1enr |= ((1 << STM_RCC_AHB1ENR_IOPAEN) |
 266                             (1 << STM_RCC_AHB1ENR_IOPCEN));
 267
 268         stm_afr_set(&stm_gpioa, 8, STM_AFR_AF0);
 269         stm_moder_set(&stm_gpioa, 8, STM_MODER_ALTERNATE);
 270         stm_ospeedr_set(&stm_gpioa, 8, STM_OSPEEDR_HIGH);
 271
 272         stm_afr_set(&stm_gpioc, 9, STM_AFR_AF0);
 273         stm_moder_set(&stm_gpioc, 9, STM_MODER_ALTERNATE);
 274         stm_ospeedr_set(&stm_gpioc, 9, STM_OSPEEDR_HIGH);
 275
 276         cfgr = stm_rcc.cfgr;
 277         cfgr &= 0x001fffff;
 278         cfgr |= ((0 << STM_RCC_CFGR_MCO2) |
 279                  (6 << STM_RCC_CFGR_MCO2PRE) |
 280                  (6 << STM_RCC_CFGR_MCO1PRE) |
 281                  (2 << STM_RCC_CFGR_MCO1));
 282         stm_rcc.cfgr = cfgr;
 283 #endif
 284 }