2 * Copyright © 2012 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
20 static volatile __data uint16_t ao_tick_count;
22 uint16_t ao_time(void)
31 static __xdata uint8_t ao_forever;
34 ao_delay(uint16_t ticks)
37 ao_sleep(&ao_forever);
41 volatile __data uint8_t ao_adc_interval = 1;
42 volatile __data uint8_t ao_adc_count;
49 void stm_tim6_isr(void)
53 if (++ao_adc_count == ao_adc_interval) {
62 ao_timer_set_adc_interval(uint8_t interval) __critical
64 ao_adc_interval = interval;
69 #define TIMER_10kHz (STM_APB1 / 10000)
74 stm_nvic_set_enable(STM_ISR_TIM6_POS);
75 stm_nvic_set_priority(STM_ISR_TIM6_POS, 1);
78 stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_TIM6EN);
80 stm_tim6.psc = TIMER_10kHz;
84 /* Enable update interrupt */
85 stm_tim6.dier = (1 << STM_TIM67_DIER_UIE);
87 /* Poke timer to reload values */
88 stm_tim6.egr |= (1 << STM_TIM67_EGR_UG);
90 stm_tim6.cr2 = (STM_TIM67_CR2_MMS_RESET << STM_TIM67_CR2_MMS);
93 stm_tim6.cr1 = ((0 << STM_TIM67_CR1_ARPE) |
94 (0 << STM_TIM67_CR1_OPM) |
95 (1 << STM_TIM67_CR1_URS) |
96 (0 << STM_TIM67_CR1_UDIS) |
97 (1 << STM_TIM67_CR1_CEN));
106 /* Set flash latency to tolerate 32MHz SYSCLK -> 1 wait state */
107 uint32_t acr = stm_flash.acr;
109 /* Enable 64-bit access and prefetch */
110 acr |= (1 << STM_FLASH_ACR_ACC64) | (1 << STM_FLASH_ACR_PRFEN);
113 /* Enable 1 wait state so the CPU can run at 32MHz */
114 /* (haven't managed to run the CPU at 32MHz yet, it's at 16MHz) */
115 acr |= (1 << STM_FLASH_ACR_LATENCY);
118 /* HCLK to 16MHz -> AHB prescaler = /1 */
120 cfgr &= ~(STM_RCC_CFGR_HPRE_MASK << STM_RCC_CFGR_HPRE);
121 cfgr |= (STM_RCC_CFGR_HPRE_DIV_1 << STM_RCC_CFGR_HPRE);
123 while ((stm_rcc.cfgr & (STM_RCC_CFGR_HPRE_MASK << STM_RCC_CFGR_HPRE)) !=
124 (STM_RCC_CFGR_HPRE_DIV_1 << STM_RCC_CFGR_HPRE))
126 #define STM_AHB_PRESCALER 1
128 /* PCLK1 to 16MHz -> APB1 Prescaler = 1 */
130 cfgr &= ~(STM_RCC_CFGR_PPRE1_MASK << STM_RCC_CFGR_PPRE1);
131 cfgr |= (STM_RCC_CFGR_PPRE1_DIV_1 << STM_RCC_CFGR_PPRE1);
133 #define STM_APB1_PRESCALER 1
135 /* PCLK2 to 16MHz -> APB2 Prescaler = 1 */
137 cfgr &= ~(STM_RCC_CFGR_PPRE2_MASK << STM_RCC_CFGR_PPRE2);
138 cfgr |= (STM_RCC_CFGR_PPRE2_DIV_1 << STM_RCC_CFGR_PPRE2);
140 #define STM_APB2_PRESCALER 1
142 /* Enable power interface clock */
143 stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_PWREN);
145 /* Set voltage range to 1.8V */
147 /* poll VOSF bit in PWR_CSR. Wait until it is reset to 0 */
148 while ((stm_pwr.csr & (1 << STM_PWR_CSR_VOSF)) != 0)
151 /* Configure voltage scaling range */
153 cr &= ~(STM_PWR_CR_VOS_MASK << STM_PWR_CR_VOS);
154 cr |= (STM_PWR_CR_VOS_1_8 << STM_PWR_CR_VOS);
157 /* poll VOSF bit in PWR_CSR. Wait until it is reset to 0 */
158 while ((stm_pwr.csr & (1 << STM_PWR_CSR_VOSF)) != 0)
161 /* Enable HSI RC clock 16MHz */
162 if (!(stm_rcc.cr & (1 << STM_RCC_CR_HSIRDY))) {
163 stm_rcc.cr |= (1 << STM_RCC_CR_HSION);
164 while (!(stm_rcc.cr & (1 << STM_RCC_CR_HSIRDY)))
167 #define STM_HSI 16000000
169 /* Switch to direct HSI for SYSCLK */
170 if ((stm_rcc.cfgr & (STM_RCC_CFGR_SWS_MASK << STM_RCC_CFGR_SWS)) !=
171 (STM_RCC_CFGR_SWS_HSI << STM_RCC_CFGR_SWS)) {
173 cfgr &= ~(STM_RCC_CFGR_SW_MASK << STM_RCC_CFGR_SW);
174 cfgr |= (STM_RCC_CFGR_SW_HSI << STM_RCC_CFGR_SW);
176 while ((stm_rcc.cfgr & (STM_RCC_CFGR_SWS_MASK << STM_RCC_CFGR_SWS)) !=
177 (STM_RCC_CFGR_SWS_HSI << STM_RCC_CFGR_SWS))
181 /* Disable the PLL */
182 stm_rcc.cr &= ~(1 << STM_RCC_CR_PLLON);
183 while (stm_rcc.cr & (1 << STM_RCC_CR_PLLRDY))
186 /* PLLVCO to 96MHz (for USB) -> PLLMUL = 6, PLLDIV = 4 */
188 cfgr &= ~(STM_RCC_CFGR_PLLMUL_MASK << STM_RCC_CFGR_PLLMUL);
189 cfgr &= ~(STM_RCC_CFGR_PLLDIV_MASK << STM_RCC_CFGR_PLLDIV);
191 // cfgr |= (STM_RCC_CFGR_PLLMUL_6 << STM_RCC_CFGR_PLLMUL);
192 // cfgr |= (STM_RCC_CFGR_PLLDIV_3 << STM_RCC_CFGR_PLLDIV);
194 cfgr |= (STM_RCC_CFGR_PLLMUL_6 << STM_RCC_CFGR_PLLMUL);
195 cfgr |= (STM_RCC_CFGR_PLLDIV_4 << STM_RCC_CFGR_PLLDIV);
200 /* PLL source to HSI */
201 cfgr &= ~(1 << STM_RCC_CFGR_PLLSRC);
203 #define STM_PLLSRC STM_HSI
207 /* Enable the PLL and wait for it */
208 stm_rcc.cr |= (1 << STM_RCC_CR_PLLON);
209 while (!(stm_rcc.cr & (1 << STM_RCC_CR_PLLRDY)))
212 /* Switch to the PLL for the system clock */
215 cfgr &= ~(STM_RCC_CFGR_SW_MASK << STM_RCC_CFGR_SW);
216 cfgr |= (STM_RCC_CFGR_SW_PLL << STM_RCC_CFGR_SW);
219 uint32_t c, part, mask, val;
222 mask = (STM_RCC_CFGR_SWS_MASK << STM_RCC_CFGR_SWS);
223 val = (STM_RCC_CFGR_SWS_PLL << STM_RCC_CFGR_SWS);