#define STM_RCC_APB1ENR_SPI3EN 15
#define STM_RCC_APB1ENR_SPI2EN 14
#define STM_RCC_APB1ENR_WWDGEN 11
-#define STM_RCC_APB1ENR_TIM14EN 8
-#define STM_RCC_APB1ENR_TIM13EN 7
-#define STM_RCC_APB1ENR_TIM12EN 6
#define STM_RCC_APB1ENR_TIM7EN 5
#define STM_RCC_APB1ENR_TIM6EN 4
#define STM_RCC_APB1ENR_TIM5EN 3
#define STM_AFIO_MAPR_CAN_REMAP_PA11_PA12 0
#define STM_AFIO_MAPR_CAN_REMAP_PB8_PB9 2
#define STM_AFIO_MAPR_CAN_REMAP_PD0_PD1 3
-#define STM_AFIO_MAPR_CAN_REMAP_MASK 3
+#define STM_AFIO_MAPR_CAN_REMAP_MASK 3UL
#define STM_AFIO_MAPR_TIM4_REMAP 12
#define STM_AFIO_MAPR_TIM3_REMAP 10
#define STM_AFIO_MAPR_TIM3_REMAP_PA6_PA7_PB0_PB1 0
#define STM_AFIO_MAPR_TIM3_REMAP_PB4_PB5_PB0_PB1 2
#define STM_AFIO_MAPR_TIM3_REMAP_PC6_PC7_PC8_PC9 3
-#define STM_AFIO_MAPR_TIM3_REMAP_MASK 3
+#define STM_AFIO_MAPR_TIM3_REMAP_MASK 3UL
#define STM_AFIO_MAPR_TIM2_REMAP 8
#define STM_AFIO_MAPR_TIM2_REMAP_PA0_PA1_PA2_PA3 0
#define STM_AFIO_MAPR_TIM2_REMAP_PA15_PB3_PA2_PA3 1
#define STM_AFIO_MAPR_TIM2_REMAP_PA0_PA1_PB10_PB11 2
#define STM_AFIO_MAPR_TIM2_REMAP_PA15_PB3_PB10_PB11 3
-#define STM_AFIO_MAPR_TIM2_REMAP_MASK 3
+#define STM_AFIO_MAPR_TIM2_REMAP_MASK 3UL
#define STM_AFIO_MAPR_TIM1_REMAP 6
#define STM_AFIO_MAPR_TIM1_REMAP_PA12_PA8_PA9_PA10_PA11_PB12_PB13_PB14_PB15 0
#define STM_AFIO_MAPR_TIM1_REMAP_PA12_PA8_PA9_PA10_PA11_PA6_PA7_PB0_PB1 1
#define STM_ADC_CR1_AWDCH 0
#define STM_ADC_CR1_AWDCH_MASK 0x1fUL
-#define STM_ADC_CR2_TSVREF 23
+#define STM_ADC_CR2_TSVREFE 23
#define STM_ADC_CR2_SWSTART 22
#define STM_ADC_CR2_JWSTART 21
#define STM_ADC_CR2_EXTTRIG 20
uint8_t shift = (pin & 3) << 2;
uint8_t val = 0;
- /* Enable AFIO */
- stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_AFIOEN);
-
if (gpio == &stm_gpioa)
val = STM_AFIO_EXTICR_PA;
else if (gpio == &stm_gpiob)