2 * Copyright © 2012 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
19 #ifndef _AO_ARCH_FUNCS_H_
20 #define _AO_ARCH_FUNCS_H_
27 /* PCLK is set to 48MHz (HCLK 48MHz, HPRE 1, PPRE 1) */
29 #define _AO_SPI_SPEED_24MHz STM_SPI_CR1_BR_PCLK_2
30 #define _AO_SPI_SPEED_12MHz STM_SPI_CR1_BR_PCLK_4
31 #define _AO_SPI_SPEED_6MHz STM_SPI_CR1_BR_PCLK_8
32 #define _AO_SPI_SPEED_3MHz STM_SPI_CR1_BR_PCLK_16
33 #define _AO_SPI_SPEED_1500kHz STM_SPI_CR1_BR_PCLK_32
34 #define _AO_SPI_SPEED_750kHz STM_SPI_CR1_BR_PCLK_64
35 #define _AO_SPI_SPEED_375kHz STM_SPI_CR1_BR_PCLK_128
36 #define _AO_SPI_SPEED_187500Hz STM_SPI_CR1_BR_PCLK_256
38 static inline uint32_t
39 ao_spi_speed(int index, uint32_t hz)
42 if (hz >=24000000) return _AO_SPI_SPEED_24MHz;
43 if (hz >=12000000) return _AO_SPI_SPEED_12MHz;
44 if (hz >= 6000000) return _AO_SPI_SPEED_6MHz;
45 if (hz >= 3000000) return _AO_SPI_SPEED_3MHz;
46 if (hz >= 1500000) return _AO_SPI_SPEED_1500kHz;
47 if (hz >= 750000) return _AO_SPI_SPEED_750kHz;
48 if (hz >= 375000) return _AO_SPI_SPEED_375kHz;
49 return _AO_SPI_SPEED_187500Hz;
52 #define AO_SPI_CONFIG_1 0x00
53 #define AO_SPI_1_CONFIG_PA5_PA6_PA7 AO_SPI_CONFIG_1
54 #define AO_SPI_2_CONFIG_PB13_PB14_PB15 AO_SPI_CONFIG_1
56 #define AO_SPI_CONFIG_2 0x04
57 #define AO_SPI_1_CONFIG_PB3_PB4_PB5 AO_SPI_CONFIG_2
58 #define AO_SPI_2_CONFIG_PD1_PD3_PD4 AO_SPI_CONFIG_2
60 #define AO_SPI_CONFIG_3 0x08
61 #define AO_SPI_1_CONFIG_PE13_PE14_PE15 AO_SPI_CONFIG_3
63 #define AO_SPI_CONFIG_NONE 0x0c
65 #define AO_SPI_INDEX_MASK 0x01
66 #define AO_SPI_CONFIG_MASK 0x0c
68 #define AO_SPI_1_PA5_PA6_PA7 (STM_SPI_INDEX(1) | AO_SPI_1_CONFIG_PA5_PA6_PA7)
69 #define AO_SPI_1_PB3_PB4_PB5 (STM_SPI_INDEX(1) | AO_SPI_1_CONFIG_PB3_PB4_PB5)
70 #define AO_SPI_1_PE13_PE14_PE15 (STM_SPI_INDEX(1) | AO_SPI_1_CONFIG_PE13_PE14_PE15)
72 #define AO_SPI_2_PB13_PB14_PB15 (STM_SPI_INDEX(2) | AO_SPI_2_CONFIG_PB13_PB14_PB15)
73 #define AO_SPI_2_PD1_PD3_PD4 (STM_SPI_INDEX(2) | AO_SPI_2_CONFIG_PD1_PD3_PD4)
75 #define AO_SPI_INDEX(id) ((id) & AO_SPI_INDEX_MASK)
76 #define AO_SPI_CONFIG(id) ((id) & AO_SPI_CONFIG_MASK)
77 #define AO_SPI_PIN_CONFIG(id) ((id) & (AO_SPI_INDEX_MASK | AO_SPI_CONFIG_MASK))
79 #define AO_SPI_CPOL_BIT 4
80 #define AO_SPI_CPHA_BIT 5
81 #define AO_SPI_CPOL(id) ((uint32_t) (((id) >> AO_SPI_CPOL_BIT) & 1))
82 #define AO_SPI_CPHA(id) ((uint32_t) (((id) >> AO_SPI_CPHA_BIT) & 1))
84 #define AO_SPI_MAKE_MODE(pol,pha) (((pol) << AO_SPI_CPOL_BIT) | ((pha) << AO_SPI_CPHA_BIT))
85 #define AO_SPI_MODE_0 AO_SPI_MAKE_MODE(0,0)
86 #define AO_SPI_MODE_1 AO_SPI_MAKE_MODE(0,1)
87 #define AO_SPI_MODE_2 AO_SPI_MAKE_MODE(1,0)
88 #define AO_SPI_MODE_3 AO_SPI_MAKE_MODE(1,1)
91 ao_spi_try_get(uint8_t spi_index, uint32_t speed, uint8_t task_id);
94 ao_spi_get(uint8_t spi_index, uint32_t speed);
97 ao_spi_put(uint8_t spi_index);
100 ao_spi_put_pins(uint8_t spi_index);
103 ao_spi_send(const void *block, uint16_t len, uint8_t spi_index);
106 ao_spi_send_fixed(uint8_t value, uint16_t len, uint8_t spi_index);
109 ao_spi_send_sync(const void *block, uint16_t len, uint8_t spi_index);
112 ao_spi_start_bytes(uint8_t spi_index);
115 ao_spi_stop_bytes(uint8_t spi_index);
118 ao_spi_send_byte(uint8_t byte, uint8_t spi_index)
120 struct stm_spi *stm_spi;
122 switch (AO_SPI_INDEX(spi_index)) {
131 while (!(stm_spi->sr & (1 << STM_SPI_SR_TXE)))
134 while (!(stm_spi->sr & (1 << STM_SPI_SR_RXNE)))
139 static inline uint8_t
140 ao_spi_recv_byte(uint8_t spi_index)
142 struct stm_spi *stm_spi;
144 switch (AO_SPI_INDEX(spi_index)) {
153 while (!(stm_spi->sr & (1 << STM_SPI_SR_TXE)))
156 while (!(stm_spi->sr & (1 << STM_SPI_SR_RXNE)))
158 return (uint8_t) stm_spi->dr;
162 ao_spi_recv(void *block, uint16_t len, uint8_t spi_index);
165 ao_spi_duplex(void *out, void *in, uint16_t len, uint8_t spi_index);
170 #define ao_spi_set_cs(reg,mask) ((reg)->bsrr = ((uint32_t) (mask)) << 16)
171 #define ao_spi_clr_cs(reg,mask) ((reg)->bsrr = (mask))
173 #define ao_spi_get_mask(reg,mask,bus, speed) do { \
174 ao_spi_get(bus, speed); \
175 ao_spi_set_cs(reg,mask); \
178 static inline uint8_t
179 ao_spi_try_get_mask(struct stm_gpio *reg, uint16_t mask, uint8_t bus, uint32_t speed, uint8_t task_id)
181 if (!ao_spi_try_get(bus, speed, task_id))
183 ao_spi_set_cs(reg, mask);
187 #define ao_spi_put_mask(reg,mask,bus) do { \
188 ao_spi_clr_cs(reg,mask); \
192 #define ao_spi_get_bit(reg,bit,bus,speed) ao_spi_get_mask(reg,(1<<bit),bus,speed)
193 #define ao_spi_put_bit(reg,bit,bus) ao_spi_put_mask(reg,(1<<bit),bus)
195 #if AO_POWER_MANAGEMENT
196 extern struct ao_power ao_power_gpioa;
197 extern struct ao_power ao_power_gpiob;
198 extern struct ao_power ao_power_gpioc;
199 extern struct ao_power ao_power_gpiof;
202 static inline void ao_enable_port(struct stm_gpio *port)
204 if ((port) == &stm_gpioa) {
205 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_IOPAEN);
206 ao_power_register(&ao_power_gpioa);
207 } else if ((port) == &stm_gpiob) {
208 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_IOPBEN);
209 ao_power_register(&ao_power_gpiob);
210 } else if ((port) == &stm_gpioc) {
211 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_IOPCEN);
212 ao_power_register(&ao_power_gpioc);
213 } else if ((port) == &stm_gpiof) {
214 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_IOPFEN);
215 ao_power_register(&ao_power_gpiof);
219 static inline void ao_disable_port(struct stm_gpio *port)
221 if ((port) == &stm_gpioa) {
222 stm_rcc.ahbenr &= ~(1UL << STM_RCC_AHBENR_IOPAEN);
223 ao_power_unregister(&ao_power_gpioa);
224 } else if ((port) == &stm_gpiob) {
225 stm_rcc.ahbenr &= ~(1UL << STM_RCC_AHBENR_IOPBEN);
226 ao_power_unregister(&ao_power_gpiob);
227 } else if ((port) == &stm_gpioc) {
228 stm_rcc.ahbenr &= ~(1UL << STM_RCC_AHBENR_IOPCEN);
229 ao_power_unregister(&ao_power_gpioc);
230 } else if ((port) == &stm_gpiof) {
231 stm_rcc.ahbenr &= ~(1UL << STM_RCC_AHBENR_IOPFEN);
232 ao_power_unregister(&ao_power_gpiof);
236 #define ao_gpio_set(port, bit, v) stm_gpio_set(port, bit, v)
238 #define ao_gpio_get(port, bit) stm_gpio_get(port, bit)
240 #define ao_enable_output(port,bit,v) do { \
241 ao_enable_port(port); \
242 ao_gpio_set(port, bit, v); \
243 stm_moder_set(port, bit, STM_MODER_OUTPUT);\
246 #define ao_gpio_set_mode(port,bit,mode) do { \
247 if (mode == AO_EXTI_MODE_PULL_UP) \
248 stm_pupdr_set(port, bit, STM_PUPDR_PULL_UP); \
249 else if (mode == AO_EXTI_MODE_PULL_DOWN) \
250 stm_pupdr_set(port, bit, STM_PUPDR_PULL_DOWN); \
252 stm_pupdr_set(port, bit, STM_PUPDR_NONE); \
255 #define ao_enable_input(port,bit,mode) do { \
256 ao_enable_port(port); \
257 stm_moder_set(port, bit, STM_MODER_INPUT); \
258 ao_gpio_set_mode(port, bit, mode); \
261 #define ao_enable_cs(port,bit) do { \
262 ao_enable_output(port, bit, 1); \
265 #define ao_spi_init_cs(port, mask) do { \
266 ao_enable_port(port); \
267 if ((mask) & 0x0001) ao_enable_cs(port, 0); \
268 if ((mask) & 0x0002) ao_enable_cs(port, 1); \
269 if ((mask) & 0x0004) ao_enable_cs(port, 2); \
270 if ((mask) & 0x0008) ao_enable_cs(port, 3); \
271 if ((mask) & 0x0010) ao_enable_cs(port, 4); \
272 if ((mask) & 0x0020) ao_enable_cs(port, 5); \
273 if ((mask) & 0x0040) ao_enable_cs(port, 6); \
274 if ((mask) & 0x0080) ao_enable_cs(port, 7); \
275 if ((mask) & 0x0100) ao_enable_cs(port, 8); \
276 if ((mask) & 0x0200) ao_enable_cs(port, 9); \
277 if ((mask) & 0x0400) ao_enable_cs(port, 10);\
278 if ((mask) & 0x0800) ao_enable_cs(port, 11);\
279 if ((mask) & 0x1000) ao_enable_cs(port, 12);\
280 if ((mask) & 0x2000) ao_enable_cs(port, 13);\
281 if ((mask) & 0x4000) ao_enable_cs(port, 14);\
282 if ((mask) & 0x8000) ao_enable_cs(port, 15);\
288 extern uint8_t ao_dma_done[STM_NUM_DMA];
291 ao_dma_set_transfer(uint8_t index,
292 volatile void *peripheral,
298 ao_dma_set_isr(uint8_t index, void (*isr)(int index));
301 ao_dma_start(uint8_t index);
304 ao_dma_done_transfer(uint8_t index);
307 ao_dma_abort(uint8_t index);
310 ao_dma_alloc(uint8_t index);
318 ao_i2c_get(uint8_t i2c_index);
321 ao_i2c_start(uint8_t i2c_index, uint16_t address);
324 ao_i2c_put(uint8_t i2c_index);
327 ao_i2c_send(void *block, uint16_t len, uint8_t i2c_index, uint8_t stop);
330 ao_i2c_recv(void *block, uint16_t len, uint8_t i2c_index, uint8_t stop);
335 /* ao_serial_stm.c */
337 #if USE_SERIAL_1_FLOW && USE_SERIAL_1_SW_FLOW || USE_SERIAL_2_FLOW && USE_SERIAL_2_SW_FLOW
338 #define HAS_SERIAL_SW_FLOW 1
340 #define HAS_SERIAL_SW_FLOW 0
343 #if USE_SERIAL_2_FLOW && !USE_SERIAL_2_SW_FLOW
344 #define USE_SERIAL_2_HW_FLOW 1
347 #if USE_SERIAL_1_FLOW && !USE_SERIAL_1_SW_FLOW
348 #define USE_SERIAL_1_HW_FLOW 1
351 #if USE_SERIAL_1_HW_FLOW || USE_SERIAL_2_HW_FLOW
352 #define HAS_SERIAL_HW_FLOW 1
354 #define HAS_SERIAL_HW_FLOW 0
357 struct ao_stm_usart {
358 struct ao_fifo rx_fifo;
359 struct ao_fifo tx_fifo;
360 struct stm_usart *reg;
363 #if HAS_SERIAL_SW_FLOW
364 /* RTS - 0 if we have FIFO space, 1 if not
365 * CTS - 0 if we can send, 0 if not
367 struct stm_gpio *gpio_rts;
368 struct stm_gpio *gpio_cts;
376 extern struct ao_stm_usart ao_stm_usart1;
380 extern struct ao_stm_usart ao_stm_usart2;
384 extern struct ao_stm_usart ao_stm_usart3;
387 #define ARM_PUSH32(stack, val) (*(--(stack)) = (val))
389 typedef uint32_t ao_arch_irq_t;
391 static inline uint32_t
392 ao_arch_irqsave(void) {
394 asm("mrs %0,primask" : "=&r" (primask));
395 ao_arch_block_interrupts();
400 ao_arch_irqrestore(uint32_t primask) {
401 asm("msr primask,%0" : : "r" (primask));
405 ao_arch_memory_barrier(void) {
406 asm volatile("" ::: "memory");
411 ao_arch_init_stack(struct ao_task *task, uint32_t *sp, void *start)
413 uint32_t a = (uint32_t) start;
416 /* Return address (goes into LR) */
419 /* Clear register values r0-r7 */
427 /* PRIMASK with interrupts enabled */
433 static inline void ao_arch_save_regs(void) {
434 /* Save general registers */
435 asm("push {r0-r7,lr}\n");
442 asm("mrs r0,primask");
446 static inline void ao_arch_save_stack(void) {
448 asm("mov %0,sp" : "=&r" (sp) );
449 ao_cur_task->sp32 = (sp);
450 if (sp < &ao_cur_task->stack32[0])
451 ao_panic (AO_PANIC_STACK);
454 static inline void ao_arch_restore_stack(void) {
456 asm("mov sp, %0" : : "r" (ao_cur_task->sp32) );
458 /* Restore PRIMASK */
460 asm("msr primask,r0");
464 asm("msr apsr_nczvq,r0");
466 /* Restore general registers */
467 asm("pop {r0-r7,pc}\n");
470 static inline void ao_sleep_mode(void) {
473 WFI (Wait for Interrupt) or WFE (Wait for Event) while:
474 – Set SLEEPDEEP in Cortex ® -M0 System Control register
475 – Set PDDS bit in Power Control register (PWR_CR)
476 – Clear WUF bit in Power Control/Status register (PWR_CSR)
479 ao_arch_block_interrupts();
481 /* Enable power interface clock */
482 stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_PWREN);
484 stm_scb.scr |= (1 << STM_SCB_SCR_SLEEPDEEP);
486 stm_pwr.cr |= (1 << STM_PWR_CR_PDDS) | (1 << STM_PWR_CR_LPDS);
488 stm_pwr.cr |= (1 << STM_PWR_CR_CWUF);
498 #ifndef HAS_SAMPLE_PROFILE
499 #define HAS_SAMPLE_PROFILE 0
502 #if !HAS_SAMPLE_PROFILE
503 #define HAS_ARCH_START_SCHEDULER 1
505 static inline void ao_arch_start_scheduler(void) {
509 asm("mrs %0,msp" : "=&r" (sp));
510 asm("msr psp,%0" : : "r" (sp));
511 asm("mrs %0,control" : "=&r" (control));
513 asm("msr control,%0" : : "r" (control));
518 #define ao_arch_isr_stack()
522 #define ao_arch_wait_interrupt() do { \
524 ao_arch_release_interrupts(); \
525 asm(".global ao_idle_loc\nao_idle_loc:"); \
526 ao_arch_block_interrupts(); \
529 #define ao_arch_critical(b) do { \
530 uint32_t __mask = ao_arch_irqsave(); \
531 do { b } while (0); \
532 ao_arch_irqrestore(__mask); \
539 ao_usb_alloc(uint16_t *buffers[2]);
542 ao_usb_alloc2(uint16_t *buffers[2]);
545 ao_usb_write(uint16_t len);
548 ao_usb_write2(uint16_t len);
549 #endif /* AO_USB_DIRECTIO */
554 ao_debug_out(char c);
556 #endif /* _AO_ARCH_FUNCS_H_ */