2 * Copyright © 2012 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
20 struct ao_spi_stm_info {
21 uint8_t miso_dma_index;
22 uint8_t mosi_dma_index;
23 struct stm_spi *stm_spi;
26 uint8_t ao_spi_mutex[STM_NUM_SPI];
28 static const struct ao_spi_stm_info ao_spi_stm_info[STM_NUM_SPI] = {
30 .miso_dma_index = STM_DMA_INDEX(STM_DMA_CHANNEL_SPI1_RX),
31 .mosi_dma_index = STM_DMA_INDEX(STM_DMA_CHANNEL_SPI1_TX),
35 .miso_dma_index = STM_DMA_INDEX(STM_DMA_CHANNEL_SPI2_RX),
36 .mosi_dma_index = STM_DMA_INDEX(STM_DMA_CHANNEL_SPI2_TX),
41 static uint8_t spi_dev_null;
44 ao_spi_send(void *block, uint16_t len, uint8_t spi_index)
46 struct stm_spi *stm_spi = ao_spi_stm_info[spi_index].stm_spi;
47 uint8_t mosi_dma_index = ao_spi_stm_info[spi_index].mosi_dma_index;
48 uint8_t miso_dma_index = ao_spi_stm_info[spi_index].miso_dma_index;
50 /* Set up the transmit DMA to deliver data */
51 ao_dma_set_transfer(mosi_dma_index,
55 (0 << STM_DMA_CCR_MEM2MEM) |
56 (STM_DMA_CCR_PL_MEDIUM << STM_DMA_CCR_PL) |
57 (STM_DMA_CCR_MSIZE_8 << STM_DMA_CCR_MSIZE) |
58 (STM_DMA_CCR_PSIZE_8 << STM_DMA_CCR_PSIZE) |
59 (1 << STM_DMA_CCR_MINC) |
60 (0 << STM_DMA_CCR_PINC) |
61 (0 << STM_DMA_CCR_CIRC) |
62 (STM_DMA_CCR_DIR_MEM_TO_PER << STM_DMA_CCR_DIR));
67 /* Set up the receive DMA -- when this is done, we know the SPI unit
68 * is idle. Without this, we'd have to poll waiting for the BSY bit to
71 ao_dma_set_transfer(miso_dma_index,
75 (0 << STM_DMA_CCR_MEM2MEM) |
76 (STM_DMA_CCR_PL_MEDIUM << STM_DMA_CCR_PL) |
77 (STM_DMA_CCR_MSIZE_8 << STM_DMA_CCR_MSIZE) |
78 (STM_DMA_CCR_PSIZE_8 << STM_DMA_CCR_PSIZE) |
79 (0 << STM_DMA_CCR_MINC) |
80 (0 << STM_DMA_CCR_PINC) |
81 (0 << STM_DMA_CCR_CIRC) |
82 (STM_DMA_CCR_DIR_PER_TO_MEM << STM_DMA_CCR_DIR));
83 stm_spi->cr2 = ((0 << STM_SPI_CR2_TXEIE) |
84 (0 << STM_SPI_CR2_RXNEIE) |
85 (0 << STM_SPI_CR2_ERRIE) |
86 (0 << STM_SPI_CR2_SSOE) |
87 (1 << STM_SPI_CR2_TXDMAEN) |
88 (1 << STM_SPI_CR2_RXDMAEN));
89 ao_dma_start(miso_dma_index);
90 ao_dma_start(mosi_dma_index);
92 while (!ao_dma_done[miso_dma_index])
93 ao_sleep(&ao_dma_done[miso_dma_index]);
95 ao_dma_done_transfer(mosi_dma_index);
96 ao_dma_done_transfer(miso_dma_index);
100 ao_spi_recv(void *block, uint16_t len, uint8_t spi_index)
102 struct stm_spi *stm_spi = ao_spi_stm_info[spi_index].stm_spi;
103 uint8_t mosi_dma_index = ao_spi_stm_info[spi_index].mosi_dma_index;
104 uint8_t miso_dma_index = ao_spi_stm_info[spi_index].miso_dma_index;
106 /* Set up transmit DMA to make the SPI hardware actually run */
107 ao_dma_set_transfer(mosi_dma_index,
111 (0 << STM_DMA_CCR_MEM2MEM) |
112 (STM_DMA_CCR_PL_MEDIUM << STM_DMA_CCR_PL) |
113 (STM_DMA_CCR_MSIZE_8 << STM_DMA_CCR_MSIZE) |
114 (STM_DMA_CCR_PSIZE_8 << STM_DMA_CCR_PSIZE) |
115 (0 << STM_DMA_CCR_MINC) |
116 (0 << STM_DMA_CCR_PINC) |
117 (0 << STM_DMA_CCR_CIRC) |
118 (STM_DMA_CCR_DIR_MEM_TO_PER << STM_DMA_CCR_DIR));
123 /* Set up the receive DMA to capture data */
124 ao_dma_set_transfer(miso_dma_index,
128 (0 << STM_DMA_CCR_MEM2MEM) |
129 (STM_DMA_CCR_PL_MEDIUM << STM_DMA_CCR_PL) |
130 (STM_DMA_CCR_MSIZE_8 << STM_DMA_CCR_MSIZE) |
131 (STM_DMA_CCR_PSIZE_8 << STM_DMA_CCR_PSIZE) |
132 (1 << STM_DMA_CCR_MINC) |
133 (0 << STM_DMA_CCR_PINC) |
134 (0 << STM_DMA_CCR_CIRC) |
135 (STM_DMA_CCR_DIR_PER_TO_MEM << STM_DMA_CCR_DIR));
137 stm_spi->cr2 = ((0 << STM_SPI_CR2_TXEIE) |
138 (0 << STM_SPI_CR2_RXNEIE) |
139 (0 << STM_SPI_CR2_ERRIE) |
140 (0 << STM_SPI_CR2_SSOE) |
141 (1 << STM_SPI_CR2_TXDMAEN) |
142 (1 << STM_SPI_CR2_RXDMAEN));
143 ao_dma_start(miso_dma_index);
144 ao_dma_start(mosi_dma_index);
146 /* Wait until the SPI unit is done */
148 while (!ao_dma_done[miso_dma_index])
149 ao_sleep(&ao_dma_done[miso_dma_index]);
152 ao_dma_done_transfer(mosi_dma_index);
153 ao_dma_done_transfer(miso_dma_index);
157 ao_spi_get(uint8_t spi_index)
159 struct stm_spi *stm_spi = ao_spi_stm_info[spi_index].stm_spi;
161 ao_mutex_get(&ao_spi_mutex[spi_index]);
162 stm_spi->cr1 = ((0 << STM_SPI_CR1_BIDIMODE) | /* Three wire mode */
163 (0 << STM_SPI_CR1_BIDIOE) |
164 (0 << STM_SPI_CR1_CRCEN) | /* CRC disabled */
165 (0 << STM_SPI_CR1_CRCNEXT) |
166 (0 << STM_SPI_CR1_DFF) |
167 (0 << STM_SPI_CR1_RXONLY) |
168 (1 << STM_SPI_CR1_SSM) | /* Software SS handling */
169 (1 << STM_SPI_CR1_SSI) | /* ... */
170 (0 << STM_SPI_CR1_LSBFIRST) | /* Little endian */
171 (1 << STM_SPI_CR1_SPE) | /* Enable SPI unit */
172 (STM_SPI_CR1_BR_PCLK_4 << STM_SPI_CR1_BR) | /* baud rate to pclk/4 */
173 (1 << STM_SPI_CR1_MSTR) |
174 (0 << STM_SPI_CR1_CPOL) | /* Format 0 */
175 (0 << STM_SPI_CR1_CPHA));
179 ao_spi_put(uint8_t spi_index)
181 struct stm_spi *stm_spi = ao_spi_stm_info[spi_index].stm_spi;
184 ao_mutex_put(&ao_spi_mutex[spi_index]);
188 ao_spi_channel_init(uint8_t spi_index)
190 struct stm_spi *stm_spi = ao_spi_stm_info[spi_index].stm_spi;
194 stm_spi->cr2 = ((0 << STM_SPI_CR2_TXEIE) |
195 (0 << STM_SPI_CR2_RXNEIE) |
196 (0 << STM_SPI_CR2_ERRIE) |
197 (0 << STM_SPI_CR2_SSOE) |
198 (0 << STM_SPI_CR2_TXDMAEN) |
199 (0 << STM_SPI_CR2_RXDMAEN));
206 # if SPI_1_PA5_PA6_PA7
207 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOAEN);
208 stm_afr_set(&stm_gpioa, 5, STM_AFR_AF5);
209 stm_afr_set(&stm_gpioa, 6, STM_AFR_AF5);
210 stm_afr_set(&stm_gpioa, 7, STM_AFR_AF5);
212 # if SPI_1_PB3_PB4_PB5
213 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOBEN);
214 stm_afr_set(&stm_gpiob, 3, STM_AFR_AF5);
215 stm_afr_set(&stm_gpiob, 4, STM_AFR_AF5);
216 stm_afr_set(&stm_gpiob, 5, STM_AFR_AF5);
218 # if SPI_1_PE13_PE14_PE15
219 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOEEN);
220 stm_afr_set(&stm_gpioe, 13, STM_AFR_AF5);
221 stm_afr_set(&stm_gpioe, 14, STM_AFR_AF5);
222 stm_afr_set(&stm_gpioe, 15, STM_AFR_AF5);
224 # error "No SPI_1 port configuration specified"
229 stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_SPI1EN);
231 ao_spi_channel_init(0);
235 # if SPI_2_PB13_PB14_PB15
236 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOBEN);
237 stm_afr_set(&stm_gpiob, 13, STM_AFR_AF5);
238 stm_afr_set(&stm_gpiob, 14, STM_AFR_AF5);
239 stm_afr_set(&stm_gpiob, 15, STM_AFR_AF5);
241 # if SPI_2_PPD1_PD3_PD4
242 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIODEN);
243 stm_afr_set(&stm_gpiod, 1, STM_AFR_AF5);
244 stm_afr_set(&stm_gpiod, 3, STM_AFR_AF5);
245 stm_afr_set(&stm_gpiod, 4, STM_AFR_AF5);
247 # error "No SPI_2 port configuration specified"
251 stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_SPI2EN);
253 ao_spi_channel_init(1);