2 * Copyright © 2012 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
22 static uint8_t ao_adc_ready;
24 #define AO_ADC_CR2_VAL(start) ((HAS_ADC_TEMP << STM_ADC_CR2_TSVREFE) |\
25 ((start) << STM_ADC_CR2_SWSTART) | \
26 (0 << STM_ADC_CR2_JWSTART) | \
27 (0 << STM_ADC_CR2_EXTTRIG) | \
28 (STM_ADC_CR2_EXTSEL_SWSTART << STM_ADC_CR2_EXTSEL) | \
29 (0 << STM_ADC_CR2_JEXTTRIG) | \
30 (0 << STM_ADC_CR2_JEXTSEL) | \
31 (0 << STM_ADC_CR2_ALIGN) | \
32 (1 << STM_ADC_CR2_DMA) | \
33 (0 << STM_ADC_CR2_CONT) | \
34 (1 << STM_ADC_CR2_ADON))
37 * Callback from DMA ISR
39 * Mark time in ring, shut down DMA engine
41 static void ao_adc_done(int index)
44 AO_DATA_PRESENT(AO_DATA_ADC);
45 ao_dma_done_transfer(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1));
46 ao_data_fill(ao_data_head);
51 * Start the ADC sequence using the DMA engine
60 ao_dma_set_transfer(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1),
62 (void *) (&ao_data_ring[ao_data_head].adc),
64 (0 << STM_DMA_CCR_MEM2MEM) |
65 (STM_DMA_CCR_PL_HIGH << STM_DMA_CCR_PL) |
66 (STM_DMA_CCR_MSIZE_16 << STM_DMA_CCR_MSIZE) |
67 (STM_DMA_CCR_PSIZE_16 << STM_DMA_CCR_PSIZE) |
68 (1 << STM_DMA_CCR_MINC) |
69 (0 << STM_DMA_CCR_PINC) |
70 (0 << STM_DMA_CCR_CIRC) |
71 (STM_DMA_CCR_DIR_PER_TO_MEM << STM_DMA_CCR_DIR));
72 ao_dma_set_isr(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1), ao_adc_done);
73 ao_dma_start(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1));
75 stm_adc1.cr2 = AO_ADC_CR2_VAL(0);
76 stm_adc1.cr2 = AO_ADC_CR2_VAL(0);
77 stm_adc1.cr2 = AO_ADC_CR2_VAL(1);
80 #ifdef AO_ADC_SQ1_NAME
81 static const char *ao_adc_name[AO_NUM_ADC] = {
83 #ifdef AO_ADC_SQ2_NAME
86 #ifdef AO_ADC_SQ3_NAME
89 #ifdef AO_ADC_SQ4_NAME
92 #ifdef AO_ADC_SQ5_NAME
95 #ifdef AO_ADC_SQ6_NAME
98 #ifdef AO_ADC_SQ7_NAME
101 #ifdef AO_ADC_SQ8_NAME
104 #ifdef AO_ADC_SQ9_NAME
107 #ifdef AO_ADC_SQ10_NAME
110 #ifdef AO_ADC_SQ11_NAME
113 #ifdef AO_ADC_SQ12_NAME
116 #ifdef AO_ADC_SQ13_NAME
119 #ifdef AO_ADC_SQ14_NAME
122 #ifdef AO_ADC_SQ15_NAME
125 #ifdef AO_ADC_SQ16_NAME
128 #ifdef AO_ADC_SQ17_NAME
131 #ifdef AO_ADC_SQ18_NAME
134 #ifdef AO_ADC_SQ19_NAME
137 #ifdef AO_ADC_SQ20_NAME
140 #ifdef AO_ADC_SQ21_NAME
141 #error "too many ADC names"
149 struct ao_data packet;
155 ao_data_get(&packet);
157 AO_ADC_DUMP(&packet);
159 printf("tick: %5u", packet.tick);
160 d = (int16_t *) (&packet.adc);
161 for (i = 0; i < AO_NUM_ADC; i++) {
162 #ifdef AO_ADC_SQ1_NAME
164 printf (" %s: %5d", ao_adc_name[i], d[i]);
167 printf (" %2d: %5d", i, d[i]);
173 const struct ao_cmds ao_adc_cmds[] = {
174 { ao_adc_dump, "a\0Display current ADC values" },
179 adc_pin_set(struct stm_gpio *gpio, int pin)
181 ao_enable_port(gpio);
182 stm_gpio_conf(gpio, pin,
183 STM_GPIO_CR_MODE_INPUT,
184 STM_GPIO_CR_CNF_INPUT_ANALOG);
190 #ifdef AO_ADC_PIN0_PORT
191 adc_pin_set(AO_ADC_PIN0_PORT, AO_ADC_PIN0_PIN);
193 #ifdef AO_ADC_PIN1_PORT
194 adc_pin_set(AO_ADC_PIN1_PORT, AO_ADC_PIN1_PIN);
196 #ifdef AO_ADC_PIN2_PORT
197 adc_pin_set(AO_ADC_PIN2_PORT, AO_ADC_PIN2_PIN);
199 #ifdef AO_ADC_PIN3_PORT
200 adc_pin_set(AO_ADC_PIN3_PORT, AO_ADC_PIN3_PIN);
202 #ifdef AO_ADC_PIN4_PORT
203 adc_pin_set(AO_ADC_PIN4_PORT, AO_ADC_PIN4_PIN);
205 #ifdef AO_ADC_PIN5_PORT
206 adc_pin_set(AO_ADC_PIN5_PORT, AO_ADC_PIN5_PIN);
208 #ifdef AO_ADC_PIN6_PORT
209 adc_pin_set(AO_ADC_PIN6_PORT, AO_ADC_PIN6_PIN);
211 #ifdef AO_ADC_PIN7_PORT
212 adc_pin_set(AO_ADC_PIN7_PORT, AO_ADC_PIN7_PIN);
214 #ifdef AO_ADC_PIN8_PORT
215 adc_pin_set(AO_ADC_PIN8_PORT, AO_ADC_PIN8_PIN);
217 #ifdef AO_ADC_PIN9_PORT
218 adc_pin_set(AO_ADC_PIN9_PORT, AO_ADC_PIN9_PIN);
220 #ifdef AO_ADC_PIN10_PORT
221 adc_pin_set(AO_ADC_PIN10_PORT, AO_ADC_PIN10_PIN);
223 #ifdef AO_ADC_PIN11_PORT
224 adc_pin_set(AO_ADC_PIN11_PORT, AO_ADC_PIN11_PIN);
226 #ifdef AO_ADC_PIN12_PORT
227 adc_pin_set(AO_ADC_PIN12_PORT, AO_ADC_PIN12_PIN);
229 #ifdef AO_ADC_PIN13_PORT
230 adc_pin_set(AO_ADC_PIN13_PORT, AO_ADC_PIN13_PIN);
232 #ifdef AO_ADC_PIN14_PORT
233 adc_pin_set(AO_ADC_PIN14_PORT, AO_ADC_PIN14_PIN);
235 #ifdef AO_ADC_PIN15_PORT
236 adc_pin_set(AO_ADC_PIN15_PORT, AO_ADC_PIN15_PIN);
238 #ifdef AO_ADC_PIN16_PORT
239 adc_pin_set(AO_ADC_PIN16_PORT, AO_ADC_PIN16_PIN);
241 #ifdef AO_ADC_PIN17_PORT
242 adc_pin_set(AO_ADC_PIN17_PORT, AO_ADC_PIN17_PIN);
244 #ifdef AO_ADC_PIN18_PORT
245 adc_pin_set(AO_ADC_PIN18_PORT, AO_ADC_PIN18_PIN);
247 #ifdef AO_ADC_PIN19_PORT
248 adc_pin_set(AO_ADC_PIN19_PORT, AO_ADC_PIN19_PIN);
250 #ifdef AO_ADC_PIN20_PORT
251 adc_pin_set(AO_ADC_PIN20_PORT, AO_ADC_PIN20_PIN);
253 #ifdef AO_ADC_PIN21_PORT
254 adc_pin_set(AO_ADC_PIN21_PORT, AO_ADC_PIN21_PIN);
256 #ifdef AO_ADC_PIN22_PORT
257 adc_pin_set(AO_ADC_PIN22_PORT, AO_ADC_PIN22_PIN);
259 #ifdef AO_ADC_PIN23_PORT
260 adc_pin_set(AO_ADC_PIN23_PORT, AO_ADC_PIN23_PIN);
262 #ifdef AO_ADC_PIN24_PORT
263 #error "Too many ADC ports"
266 stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_ADC1EN);
268 /* Turn off ADC during configuration */
271 stm_adc1.cr1 = ((0 << STM_ADC_CR1_AWDEN ) |
272 (0 << STM_ADC_CR1_JAWDEN ) |
273 (STM_ADC_CR1_DUALMOD_INDEPENDENT << STM_ADC_CR1_DUALMOD ) |
274 (0 << STM_ADC_CR1_DISCNUM ) |
275 (0 << STM_ADC_CR1_JDISCEN ) |
276 (0 << STM_ADC_CR1_DISCEN ) |
277 (0 << STM_ADC_CR1_JAUTO ) |
278 (0 << STM_ADC_CR1_AWDSGL ) |
279 (1 << STM_ADC_CR1_SCAN ) |
280 (0 << STM_ADC_CR1_JEOCIE ) |
281 (0 << STM_ADC_CR1_AWDIE ) |
282 (0 << STM_ADC_CR1_EOCIE ) |
283 (0 << STM_ADC_CR1_AWDCH ));
285 /* 384 cycle sample time for everyone */
286 stm_adc1.smpr1 = 0x3ffff;
287 stm_adc1.smpr2 = 0x3fffffff;
289 stm_adc1.sqr1 = ((AO_NUM_ADC - 1) << 20);
291 stm_adc1.sqr3 |= (AO_ADC_SQ1 << 0);
294 stm_adc1.sqr3 |= (AO_ADC_SQ2 << 5);
297 stm_adc1.sqr3 |= (AO_ADC_SQ3 << 10);
300 stm_adc1.sqr3 |= (AO_ADC_SQ4 << 15);
303 stm_adc1.sqr3 |= (AO_ADC_SQ5 << 20);
306 stm_adc1.sqr3 |= (AO_ADC_SQ6 << 25);
309 stm_adc1.sqr2 |= (AO_ADC_SQ7 << 0);
312 stm_adc1.sqr2 |= (AO_ADC_SQ8 << 5);
315 stm_adc1.sqr2 |= (AO_ADC_SQ9 << 10);
318 stm_adc1.sqr2 |= (AO_ADC_SQ10 << 15);
321 stm_adc1.sqr2 |= (AO_ADC_SQ11 << 20);
324 stm_adc1.sqr2 |= (AO_ADC_SQ12 << 25);
327 stm_adc1.sqr1 |= (AO_ADC_SQ13 << 0);
330 stm_adc1.sqr1 |= (AO_ADC_SQ14 << 5);
333 stm_adc1.sqr1 |= (AO_ADC_SQ15 << 10);
336 stm_adc1.sqr1 |= (AO_ADC_SQ16 << 15);
339 #error "too many ADC channels"
343 #error Please define HAS_ADC_TEMP
346 stm_adc1.cr2 |= ((1 << STM_ADC_CR2_TSVREFE));
349 /* Clear any stale status bits */
352 ao_dma_alloc(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1));
354 ao_cmd_register(&ao_adc_cmds[0]);