altos/lpc: Adjust ADC clock from 450kHz to 4.5MHz

A missing zero. Also, let products change this value if desired to
improve high-impedence performance.

Signed-off-by: Keith Packard <keithp@keithp.com>

diff --git a/src/lpc/ao_adc_lpc.c b/src/lpc/ao_adc_lpc.c
index 29d3668cedb1fdff4824dfa5ba2494610604ab81..1fbf13660a5969739cf496d602acf699e4abb371 100644 (file)
--- a/src/lpc/ao_adc_lpc.c
+++ b/src/lpc/ao_adc_lpc.c
@@ -57,7 +57,10 @@
 /* ADC clock is divided by this value + 1, which ensures that
  * the ADC clock will be strictly less than 4.5MHz as required
  */
-#define AO_ADC_CLKDIV  (AO_LPC_SYSCLK / 450000)
+#ifndef AO_LPC_ADC_CLOCK
+#define AO_LPC_ADC_CLOCK       4500000
+#endif
+#define AO_ADC_CLKDIV  (AO_LPC_SYSCLK / AO_LPC_ADC_CLOCK)
 
 static uint8_t         ao_adc_ready;
 static uint8_t         ao_adc_sequence;