altos: Switch stm-demo to HSE clock, add USB

Requires that SB17 be soldered shut so that the MCO from the STlink
CPU is available the target for HSE input.

Signed-off-by: Keith Packard <keithp@keithp.com>

diff --git a/src/stm-demo/Makefile b/src/stm-demo/Makefile
index 2f156ea4436175752f1e3589950316bf67e57267..dd7e6e02310f65de516dfbeb1b1421a67bedecba 100644 (file)
--- a/src/stm-demo/Makefile
+++ b/src/stm-demo/Makefile
@@ -32,7 +32,8 @@ ALTOS_SRC = \
        ao_dma_stm.c \
        ao_spi_stm.c \
        ao_adc_stm.c \
-       ao_i2c_stm.c
+       ao_i2c_stm.c \
+       ao_usb_stm.c
 
 PRODUCT=StmDemo-v0.0
 PRODUCT_DEF=-DSTM_DEMO

diff --git a/src/stm-demo/ao_demo.c b/src/stm-demo/ao_demo.c
index 879f7f75bb4fbdb1cb3c71c67fddb43aa645439d..7bb53047e9310b169cc3b355090318e79924cf64 100644 (file)
--- a/src/stm-demo/ao_demo.c
+++ b/src/stm-demo/ao_demo.c
@@ -174,6 +174,7 @@ main(void)
        ao_timer_set_adc_interval(100);
 
        ao_adc_init();
+       ao_usb_init();
 
        ao_cmd_register(&ao_demo_cmds[0]);
        

diff --git a/src/stm-demo/ao_pins.h b/src/stm-demo/ao_pins.h
index 3192c2b702d19875c8a6d139c33af2c3f1736e29..1daab35165ba0efae56d45e167c4502abfa21cd7 100644 (file)
--- a/src/stm-demo/ao_pins.h
+++ b/src/stm-demo/ao_pins.h
@@ -18,22 +18,29 @@
 #ifndef _AO_PINS_H_
 #define _AO_PINS_H_
 
-/* No external crystal */
-#define AO_HSE         0
+/* Bridge SB17 on the board and use the MCO from the other chip */
+#define AO_HSE         8000000
+#define AO_HSE_BYPASS          1
 
+/* PLLVCO = 96MHz (so that USB will work) */
+#define AO_PLLMUL              12
+#define AO_RCC_CFGR_PLLMUL     (STM_RCC_CFGR_PLLMUL_12)
+
+/* SYSCLK = 32MHz */
+#define AO_PLLDIV              3
+#define AO_RCC_CFGR_PLLDIV     (STM_RCC_CFGR_PLLDIV_3)
+
+/* HCLK = 32MHZ (CPU clock) */
 #define AO_AHB_PRESCALER       1
 #define AO_RCC_CFGR_HPRE_DIV   STM_RCC_CFGR_HPRE_DIV_1
 
-#define AO_APB1_PRESCALER      2
-#define AO_RCC_CFGR_PPRE1_DIV  STM_RCC_CFGR_PPRE2_DIV_2
-
-#define AO_APB2_PRESCALER      2
-#define AO_RCC_CFGR_PPRE2_DIV  STM_RCC_CFGR_PPRE2_DIV_2
+/* Run APB1 at HCLK/1 */
+#define AO_APB1_PRESCALER      1
+#define AO_RCC_CFGR_PPRE1_DIV  STM_RCC_CFGR_PPRE2_DIV_1
 
-#define AO_PLLMUL              6
-#define AO_PLLDIV              4
-#define AO_RCC_CFGR_PLLMUL     (STM_RCC_CFGR_PLLMUL_6)
-#define AO_RCC_CFGR_PLLDIV     (STM_RCC_CFGR_PLLDIV_4)
+/* Run APB2 at HCLK/1 */
+#define AO_APB2_PRESCALER              1
+#define AO_RCC_CFGR_PPRE2_DIV  STM_RCC_CFGR_PPRE2_DIV_1
 
 #define HAS_SERIAL_1           1
 #define USE_SERIAL_1_STDIN     1
@@ -56,7 +63,7 @@
 
 #define HAS_SPI_2              0
 
-#define HAS_USB                        0
+#define HAS_USB                        1
 #define HAS_BEEP               0
 #define PACKET_HAS_SLAVE       0