From 6d1606895f70c6bca20c25084107f90bd0b613ec Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Wed, 11 Apr 2012 23:31:28 -0700 Subject: [PATCH] altos: Switch stm-demo to HSE clock, add USB Requires that SB17 be soldered shut so that the MCO from the STlink CPU is available the target for HSE input. Signed-off-by: Keith Packard --- src/stm-demo/Makefile | 3 ++- src/stm-demo/ao_demo.c | 1 + src/stm-demo/ao_pins.h | 31 +++++++++++++++++++------------ 3 files changed, 22 insertions(+), 13 deletions(-) diff --git a/src/stm-demo/Makefile b/src/stm-demo/Makefile index 2f156ea4..dd7e6e02 100644 --- a/src/stm-demo/Makefile +++ b/src/stm-demo/Makefile @@ -32,7 +32,8 @@ ALTOS_SRC = \ ao_dma_stm.c \ ao_spi_stm.c \ ao_adc_stm.c \ - ao_i2c_stm.c + ao_i2c_stm.c \ + ao_usb_stm.c PRODUCT=StmDemo-v0.0 PRODUCT_DEF=-DSTM_DEMO diff --git a/src/stm-demo/ao_demo.c b/src/stm-demo/ao_demo.c index 879f7f75..7bb53047 100644 --- a/src/stm-demo/ao_demo.c +++ b/src/stm-demo/ao_demo.c @@ -174,6 +174,7 @@ main(void) ao_timer_set_adc_interval(100); ao_adc_init(); + ao_usb_init(); ao_cmd_register(&ao_demo_cmds[0]); diff --git a/src/stm-demo/ao_pins.h b/src/stm-demo/ao_pins.h index 3192c2b7..1daab351 100644 --- a/src/stm-demo/ao_pins.h +++ b/src/stm-demo/ao_pins.h @@ -18,22 +18,29 @@ #ifndef _AO_PINS_H_ #define _AO_PINS_H_ -/* No external crystal */ -#define AO_HSE 0 +/* Bridge SB17 on the board and use the MCO from the other chip */ +#define AO_HSE 8000000 +#define AO_HSE_BYPASS 1 +/* PLLVCO = 96MHz (so that USB will work) */ +#define AO_PLLMUL 12 +#define AO_RCC_CFGR_PLLMUL (STM_RCC_CFGR_PLLMUL_12) + +/* SYSCLK = 32MHz */ +#define AO_PLLDIV 3 +#define AO_RCC_CFGR_PLLDIV (STM_RCC_CFGR_PLLDIV_3) + +/* HCLK = 32MHZ (CPU clock) */ #define AO_AHB_PRESCALER 1 #define AO_RCC_CFGR_HPRE_DIV STM_RCC_CFGR_HPRE_DIV_1 -#define AO_APB1_PRESCALER 2 -#define AO_RCC_CFGR_PPRE1_DIV STM_RCC_CFGR_PPRE2_DIV_2 - -#define AO_APB2_PRESCALER 2 -#define AO_RCC_CFGR_PPRE2_DIV STM_RCC_CFGR_PPRE2_DIV_2 +/* Run APB1 at HCLK/1 */ +#define AO_APB1_PRESCALER 1 +#define AO_RCC_CFGR_PPRE1_DIV STM_RCC_CFGR_PPRE2_DIV_1 -#define AO_PLLMUL 6 -#define AO_PLLDIV 4 -#define AO_RCC_CFGR_PLLMUL (STM_RCC_CFGR_PLLMUL_6) -#define AO_RCC_CFGR_PLLDIV (STM_RCC_CFGR_PLLDIV_4) +/* Run APB2 at HCLK/1 */ +#define AO_APB2_PRESCALER 1 +#define AO_RCC_CFGR_PPRE2_DIV STM_RCC_CFGR_PPRE2_DIV_1 #define HAS_SERIAL_1 1 #define USE_SERIAL_1_STDIN 1 @@ -56,7 +63,7 @@ #define HAS_SPI_2 0 -#define HAS_USB 0 +#define HAS_USB 1 #define HAS_BEEP 0 #define PACKET_HAS_SLAVE 0 -- 2.30.2