2 * Copyright © 2010 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
23 #define HAS_RADIO_RATE 1
24 #define HAS_TELEMETRY 0
29 #define BEEPER_CHANNEL 4
31 #define HAS_SERIAL_1 0
37 #define USE_INTERNAL_FLASH 1
38 #define IGNITE_ON_P0 0
39 #define PACKET_HAS_MASTER 0
40 #define PACKET_HAS_SLAVE 0
41 #define AO_DATA_RING 32
42 #define HAS_FIXED_PAD_BOX 1
44 /* 8MHz High speed external crystal */
45 #define AO_HSE 8000000
47 /* PLLVCO = 96MHz (so that USB will work) */
49 #define AO_RCC_CFGR_PLLMUL (STM_RCC_CFGR_PLLMUL_12)
51 #define AO_CC1200_FOSC 40000000
53 /* SYSCLK = 32MHz (no need to go faster than CPU) */
55 #define AO_RCC_CFGR_PLLDIV (STM_RCC_CFGR_PLLDIV_3)
57 /* HCLK = 32MHz (CPU clock) */
58 #define AO_AHB_PRESCALER 1
59 #define AO_RCC_CFGR_HPRE_DIV STM_RCC_CFGR_HPRE_DIV_1
61 /* Run APB1 at 16MHz (HCLK/2) */
62 #define AO_APB1_PRESCALER 2
63 #define AO_RCC_CFGR_PPRE1_DIV STM_RCC_CFGR_PPRE2_DIV_2
65 /* Run APB2 at 16MHz (HCLK/2) */
66 #define AO_APB2_PRESCALER 2
67 #define AO_RCC_CFGR_PPRE2_DIV STM_RCC_CFGR_PPRE2_DIV_2
70 #define USE_INTERNAL_FLASH 1
71 #define USE_EEPROM_CONFIG 1
72 #define USE_STORAGE_CONFIG 0
75 #define HAS_RADIO_RATE 1
76 #define HAS_TELEMETRY 0
80 #define SPI_1_PA5_PA6_PA7 0
81 #define SPI_1_PB3_PB4_PB5 0
82 #define SPI_1_PE13_PE14_PE15 0
84 #define HAS_SPI_2 1 /* CC1200 */
85 #define SPI_2_PB13_PB14_PB15 1
86 #define SPI_2_PD1_PD3_PD4 0
87 #define SPI_2_GPIO (&stm_gpiob)
91 #define SPI_2_OSPEEDR STM_OSPEEDR_10MHz
97 #define PACKET_HAS_SLAVE 0
98 #define PACKET_HAS_MASTER 0
100 #define FAST_TIMER_FREQ 10000 /* .1ms for debouncing */
106 #define M25_MAX_CHIPS 1
107 #define AO_M25_SPI_CS_PORT (&stm_gpioa)
108 #define AO_M25_SPI_CS_MASK (1 << 15)
109 #define AO_M25_SPI_BUS AO_SPI_2_PB13_PB14_PB15
112 * Radio is a cc1200 connected via SPI
115 #define AO_RADIO_CAL_DEFAULT 5695733
117 #define AO_FEC_DEBUG 0
118 #define AO_CC1200_SPI_CS_PORT (&stm_gpioa)
119 #define AO_CC1200_SPI_CS_PIN 7
120 #define AO_CC1200_SPI_BUS AO_SPI_2_PB13_PB14_PB15
121 #define AO_CC1200_SPI stm_spi2
122 #define AO_CC1200_SPI_SPEED AO_SPI_SPEED_FAST
124 #define AO_CC1200_INT_PORT (&stm_gpiob)
125 #define AO_CC1200_INT_PIN (11)
127 #define AO_CC1200_INT_GPIO 2
128 #define AO_CC1200_INT_GPIO_IOCFG CC1200_IOCFG2
130 #define LED_PORT_0 (&stm_gpioa)
131 #define LED_PORT_1 (&stm_gpiob)
133 #define LED_PORT_0_ENABLE STM_RCC_AHBENR_GPIOAEN
134 #define LED_PORT_1_ENABLE STM_RCC_AHBENR_GPIOBEN
136 /* Port A, pins 4-6 */
137 #define LED_PORT_0_SHIFT 4
138 #define LED_PORT_0_MASK 0x7
139 #define LED_PIN_GREEN 0
140 #define LED_PIN_AMBER 1
141 #define LED_PIN_RED 2
142 #define AO_LED_RED (1 << LED_PIN_RED)
143 #define AO_LED_AMBER (1 << LED_PIN_AMBER)
144 #define AO_LED_GREEN (1 << LED_PIN_GREEN)
146 /* Port B, pins 4-5 */
147 #define LED_PORT_1_SHIFT 0
148 #define LED_PORT_1_MASK (0x3 << 4)
149 #define LED_PIN_CONT_0 4
150 #define LED_PIN_ARMED 5
152 #define AO_LED_ARMED (1 << LED_PIN_ARMED)
153 #define AO_LED_CONTINUITY(c) (1 << (4 - (c)))
154 #define AO_LED_CONTINUITY_MASK (0x1 << 4)
156 #define LEDS_AVAILABLE (LED_PORT_0_MASK|LED_PORT_1_MASK)
160 #define AO_SIREN_PORT (&stm_gpiob)
161 #define AO_SIREN_PIN 8
165 #define AO_STROBE_PORT (&stm_gpiob)
166 #define AO_STROBE_PIN 9
168 #define SPI_CONST 0x00
171 #define AO_PAD_PORT (&stm_gpioa)
173 #define AO_PAD_PIN_0 1
174 #define AO_PAD_ADC_0 0
176 #define AO_PAD_ALL_PINS ((1 << AO_PAD_PIN_0))
177 #define AO_PAD_ALL_CHANNELS ((1 << 0))
179 /* test these values with real igniters */
180 #define AO_PAD_RELAY_CLOSED 3524
181 #define AO_PAD_NO_IGNITER 16904
182 #define AO_PAD_GOOD_IGNITER 22514
184 #define AO_PAD_ADC_PYRO 2
185 #define AO_PAD_ADC_BATT 8
187 #define AO_PAD_ADC_THRUST 3
188 #define AO_PAD_ADC_PRESSURE 18
190 #define AO_ADC_FIRST_PIN 0
194 #define AO_ADC_SQ1 AO_PAD_ADC_0
195 #define AO_ADC_SQ2 AO_PAD_ADC_PYRO
196 #define AO_ADC_SQ3 AO_PAD_ADC_BATT
197 #define AO_ADC_SQ4 AO_PAD_ADC_THRUST
198 #define AO_ADC_SQ5 AO_PAD_ADC_PRESSURE
200 #define AO_PYRO_R_PYRO_SENSE 200
201 #define AO_PYRO_R_SENSE_GND 22
203 #define AO_FIRE_R_POWER_FET 0
204 #define AO_FIRE_R_FET_SENSE 200
205 #define AO_FIRE_R_SENSE_GND 22
207 #define HAS_ADC_TEMP 0
210 int16_t sense[AO_PAD_NUM];
217 #define AO_ADC_DUMP(p) \
218 printf ("tick: %5u 0: %5d pyro: %5d batt %5d thrust %5d pressure %5d\n", \
226 #define AO_ADC_PINS ((1 << AO_PAD_ADC_0) | \
227 (1 << AO_PAD_ADC_PYRO) | \
228 (1 << AO_PAD_ADC_BATT) | \
229 (1 << AO_PAD_ADC_THRUST) | \
230 (1 << AO_PAD_ADC_PRESSURE))
232 #endif /* _AO_PINS_H_ */