2 * Copyright © 2012 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
20 #include "ao_product.h"
23 #define USB_DEBUG_DATA 0
27 #define USE_USB_STDIO 1
31 #define AO_USB_OUT_SLEEP_ADDR (&ao_stdin_ready)
33 #define AO_USB_OUT_SLEEP_ADDR (&ao_usb_out_avail)
37 #define debug(format, args...) printf(format, ## args);
39 #define debug(format, args...)
43 #define debug_data(format, args...) printf(format, ## args);
45 #define debug_data(format, args...)
49 uint8_t dir_type_recip;
56 static uint8_t ao_usb_ep0_state;
58 /* Pending EP0 IN data */
59 static const uint8_t *ao_usb_ep0_in_data; /* Remaining data */
60 static uint8_t ao_usb_ep0_in_len; /* Remaining amount */
62 /* Temp buffer for smaller EP0 in data */
63 static uint8_t ao_usb_ep0_in_buf[2];
65 /* Pending EP0 OUT data */
66 static uint8_t *ao_usb_ep0_out_data;
67 static uint8_t ao_usb_ep0_out_len;
70 * Objects allocated in special USB memory
73 /* Buffer description tables */
74 static union stm_usb_bdt *ao_usb_bdt;
75 /* USB address of end of allocated storage */
76 static uint16_t ao_usb_sram_addr;
78 /* Pointer to ep0 tx/rx buffers in USB memory */
79 static uint16_t *ao_usb_ep0_tx_buffer;
80 static uint16_t *ao_usb_ep0_rx_buffer;
82 /* Pointer to bulk data tx/rx buffers in USB memory */
83 static uint16_t ao_usb_in_tx_offset;
84 static uint16_t *ao_usb_in_tx_buffer;
85 static uint16_t *ao_usb_out_rx_buffer;
87 /* System ram shadow of USB buffer; writing individual bytes is
88 * too much of a pain (sigh) */
89 static uint8_t ao_usb_tx_buffer[AO_USB_IN_SIZE];
90 static uint8_t ao_usb_tx_count;
92 static uint8_t ao_usb_rx_buffer[AO_USB_OUT_SIZE];
93 static uint8_t ao_usb_rx_count, ao_usb_rx_pos;
96 * End point register indices
99 #define AO_USB_CONTROL_EPR 0
100 #define AO_USB_INT_EPR 1
101 #define AO_USB_OUT_EPR 2
102 #define AO_USB_IN_EPR 3
104 /* Marks when we don't need to send an IN packet.
105 * This happens only when the last IN packet is not full,
106 * otherwise the host will expect to keep seeing packets.
107 * Send a zero-length packet as required
109 static uint8_t ao_usb_in_flushed;
111 /* Marks when we have delivered an IN packet to the hardware
112 * and it has not been received yet. ao_sleep on this address
113 * to wait for it to be delivered.
115 static uint8_t ao_usb_in_pending;
117 /* Marks when an OUT packet has been received by the hardware
118 * but not pulled to the shadow buffer.
120 static uint8_t ao_usb_out_avail;
121 uint8_t ao_usb_running;
122 static uint8_t ao_usb_configuration;
124 #define AO_USB_EP0_GOT_RESET 1
125 #define AO_USB_EP0_GOT_SETUP 2
126 #define AO_USB_EP0_GOT_RX_DATA 4
127 #define AO_USB_EP0_GOT_TX_ACK 8
129 static uint8_t ao_usb_ep0_receive;
130 static uint8_t ao_usb_address;
131 static uint8_t ao_usb_address_pending;
133 static inline uint32_t set_toggle(uint32_t current_value,
135 uint32_t desired_value)
137 return (current_value ^ desired_value) & mask;
140 static inline uint16_t *ao_usb_packet_buffer_addr(uint16_t sram_addr)
142 return (uint16_t *) (stm_usb_sram + sram_addr);
146 static inline uint16_t ao_usb_packet_buffer_offset(uint16_t *addr)
148 return (uint16_t) ((uint8_t *) addr - stm_usb_sram);
152 static inline uint32_t ao_usb_epr_stat_rx(uint32_t epr) {
153 return (epr >> STM_USB_EPR_STAT_RX) & STM_USB_EPR_STAT_RX_MASK;
156 static inline uint32_t ao_usb_epr_stat_tx(uint32_t epr) {
157 return (epr >> STM_USB_EPR_STAT_TX) & STM_USB_EPR_STAT_TX_MASK;
160 static inline uint32_t ao_usb_epr_ctr_rx(uint32_t epr) {
161 return (epr >> STM_USB_EPR_CTR_RX) & 1;
164 static inline uint32_t ao_usb_epr_ctr_tx(uint32_t epr) {
165 return (epr >> STM_USB_EPR_CTR_TX) & 1;
168 static inline uint32_t ao_usb_epr_setup(uint32_t epr) {
169 return (epr >> STM_USB_EPR_SETUP) & 1;
172 static inline uint32_t ao_usb_epr_dtog_rx(uint32_t epr) {
173 return (epr >> STM_USB_EPR_DTOG_RX) & 1;
176 static inline uint32_t ao_usb_epr_dtog_tx(uint32_t epr) {
177 return (epr >> STM_USB_EPR_DTOG_TX) & 1;
181 * Set current device address and mark the
182 * interface as active
185 ao_usb_set_address(uint8_t address)
187 debug("ao_usb_set_address %02x\n", address);
188 stm_usb.daddr = (1 << STM_USB_DADDR_EF) | address;
189 ao_usb_address_pending = 0;
193 * Write these values to preserve register contents under HW changes
196 #define STM_USB_EPR_INVARIANT ((1 << STM_USB_EPR_CTR_RX) | \
197 (STM_USB_EPR_DTOG_RX_WRITE_INVARIANT << STM_USB_EPR_DTOG_RX) | \
198 (STM_USB_EPR_STAT_RX_WRITE_INVARIANT << STM_USB_EPR_STAT_RX) | \
199 (1 << STM_USB_EPR_CTR_TX) | \
200 (STM_USB_EPR_DTOG_TX_WRITE_INVARIANT << STM_USB_EPR_DTOG_TX) | \
201 (STM_USB_EPR_STAT_TX_WRITE_INVARIANT << STM_USB_EPR_STAT_TX))
203 #define STM_USB_EPR_INVARIANT_MASK ((1 << STM_USB_EPR_CTR_RX) | \
204 (STM_USB_EPR_DTOG_RX_MASK << STM_USB_EPR_DTOG_RX) | \
205 (STM_USB_EPR_STAT_RX_MASK << STM_USB_EPR_STAT_RX) | \
206 (1 << STM_USB_EPR_CTR_TX) | \
207 (STM_USB_EPR_DTOG_TX_MASK << STM_USB_EPR_DTOG_TX) | \
208 (STM_USB_EPR_STAT_TX_MASK << STM_USB_EPR_STAT_TX))
211 * These bits are purely under sw control, so preserve them in the
212 * register by re-writing what was read
214 #define STM_USB_EPR_PRESERVE_MASK ((STM_USB_EPR_EP_TYPE_MASK << STM_USB_EPR_EP_TYPE) | \
215 (1 << STM_USB_EPR_EP_KIND) | \
216 (STM_USB_EPR_EA_MASK << STM_USB_EPR_EA))
222 #define _tx_dbg0(msg) _dbg(__LINE__,msg,0)
223 #define _tx_dbg1(msg,value) _dbg(__LINE__,msg,value)
225 #define _tx_dbg0(msg)
226 #define _tx_dbg1(msg,value)
230 #define _rx_dbg0(msg) _dbg(__LINE__,msg,0)
231 #define _rx_dbg1(msg,value) _dbg(__LINE__,msg,value)
233 #define _rx_dbg0(msg)
234 #define _rx_dbg1(msg,value)
238 static void _dbg(int line, char *msg, uint32_t value);
242 * Set the state of the specified endpoint register to a new
243 * value. This is tricky because the bits toggle where the new
244 * value is one, and we need to write invariant values in other
245 * spots of the register. This hardware is strange...
248 _ao_usb_set_stat_tx(int ep, uint32_t stat_tx)
250 uint16_t epr_write, epr_old;
252 _tx_dbg1("set_stat_tx top", stat_tx);
253 epr_old = epr_write = stm_usb.epr[ep].r;
254 epr_write &= STM_USB_EPR_PRESERVE_MASK;
255 epr_write |= STM_USB_EPR_INVARIANT;
256 epr_write |= set_toggle(epr_old,
257 STM_USB_EPR_STAT_TX_MASK << STM_USB_EPR_STAT_TX,
258 stat_tx << STM_USB_EPR_STAT_TX);
259 stm_usb.epr[ep].r = epr_write;
260 _tx_dbg1("set_stat_tx bottom", epr_write);
264 ao_usb_set_stat_tx(int ep, uint32_t stat_tx)
266 ao_arch_block_interrupts();
267 _ao_usb_set_stat_tx(ep, stat_tx);
268 ao_arch_release_interrupts();
272 _ao_usb_set_stat_rx(int ep, uint32_t stat_rx) {
273 uint16_t epr_write, epr_old;
275 epr_write = epr_old = stm_usb.epr[ep].r;
276 epr_write &= STM_USB_EPR_PRESERVE_MASK;
277 epr_write |= STM_USB_EPR_INVARIANT;
278 epr_write |= set_toggle(epr_old,
279 STM_USB_EPR_STAT_RX_MASK << STM_USB_EPR_STAT_RX,
280 stat_rx << STM_USB_EPR_STAT_RX);
281 stm_usb.epr[ep].r = epr_write;
285 ao_usb_set_stat_rx(int ep, uint32_t stat_rx) {
286 ao_arch_block_interrupts();
287 _ao_usb_set_stat_rx(ep, stat_rx);
288 ao_arch_release_interrupts();
292 * Set just endpoint 0, for use during startup
296 ao_usb_init_ep(uint8_t ep, uint32_t addr, uint32_t type, uint32_t stat_rx, uint32_t stat_tx)
300 ao_arch_block_interrupts();
301 epr = stm_usb.epr[ep].r;
302 epr = ((0 << STM_USB_EPR_CTR_RX) |
303 (epr & (1 << STM_USB_EPR_DTOG_RX)) |
305 (STM_USB_EPR_STAT_RX_MASK << STM_USB_EPR_STAT_RX),
306 (stat_rx << STM_USB_EPR_STAT_RX)) |
307 (type << STM_USB_EPR_EP_TYPE) |
308 (0 << STM_USB_EPR_EP_KIND) |
309 (0 << STM_USB_EPR_CTR_TX) |
310 (epr & (1 << STM_USB_EPR_DTOG_TX)) |
312 (STM_USB_EPR_STAT_TX_MASK << STM_USB_EPR_STAT_TX),
313 (stat_tx << STM_USB_EPR_STAT_TX)) |
314 (addr << STM_USB_EPR_EA));
315 stm_usb.epr[ep].r = epr;
316 ao_arch_release_interrupts();
317 debug ("writing epr[%d] 0x%04x wrote 0x%04x\n",
318 ep, epr, stm_usb.epr[ep].r);
322 ao_usb_init_btable(void)
324 ao_usb_sram_addr = 0;
326 ao_usb_bdt = (void *) stm_usb_sram;
328 ao_usb_sram_addr += 8 * STM_USB_BDT_SIZE;
330 /* Set up EP 0 - a Control end point with 32 bytes of in and out buffers */
332 ao_usb_bdt[0].single.addr_tx = ao_usb_sram_addr;
333 ao_usb_bdt[0].single.count_tx = 0;
334 ao_usb_ep0_tx_buffer = ao_usb_packet_buffer_addr(ao_usb_sram_addr);
335 ao_usb_sram_addr += AO_USB_CONTROL_SIZE;
337 ao_usb_bdt[0].single.addr_rx = ao_usb_sram_addr;
338 ao_usb_bdt[0].single.count_rx = ((1 << STM_USB_BDT_COUNT_RX_BL_SIZE) |
339 (((AO_USB_CONTROL_SIZE / 32) - 1) << STM_USB_BDT_COUNT_RX_NUM_BLOCK));
340 ao_usb_ep0_rx_buffer = ao_usb_packet_buffer_addr(ao_usb_sram_addr);
341 ao_usb_sram_addr += AO_USB_CONTROL_SIZE;
350 ao_usb_init_btable();
352 /* buffer table is at the start of USB memory */
355 ao_usb_init_ep(AO_USB_CONTROL_EPR, AO_USB_CONTROL_EP,
356 STM_USB_EPR_EP_TYPE_CONTROL,
357 STM_USB_EPR_STAT_RX_VALID,
358 STM_USB_EPR_STAT_TX_NAK);
360 /* Clear all of the other endpoints */
361 for (e = 1; e < 8; e++) {
363 STM_USB_EPR_EP_TYPE_CONTROL,
364 STM_USB_EPR_STAT_RX_DISABLED,
365 STM_USB_EPR_STAT_TX_DISABLED);
368 ao_usb_set_address(0);
372 ao_usb_set_configuration(void)
374 debug ("ao_usb_set_configuration\n");
376 /* Set up the INT end point */
377 ao_usb_bdt[AO_USB_INT_EPR].single.addr_tx = ao_usb_sram_addr;
378 ao_usb_bdt[AO_USB_INT_EPR].single.count_tx = 0;
379 ao_usb_sram_addr += AO_USB_INT_SIZE;
381 ao_usb_init_ep(AO_USB_INT_EPR,
383 STM_USB_EPR_EP_TYPE_INTERRUPT,
384 STM_USB_EPR_STAT_RX_DISABLED,
385 STM_USB_EPR_STAT_TX_NAK);
387 /* Set up the OUT end point */
388 ao_usb_bdt[AO_USB_OUT_EPR].single.addr_rx = ao_usb_sram_addr;
389 ao_usb_bdt[AO_USB_OUT_EPR].single.count_rx = ((1 << STM_USB_BDT_COUNT_RX_BL_SIZE) |
390 (((AO_USB_OUT_SIZE / 32) - 1) << STM_USB_BDT_COUNT_RX_NUM_BLOCK));
391 ao_usb_out_rx_buffer = ao_usb_packet_buffer_addr(ao_usb_sram_addr);
392 ao_usb_sram_addr += AO_USB_OUT_SIZE;
394 ao_usb_init_ep(AO_USB_OUT_EPR,
396 STM_USB_EPR_EP_TYPE_BULK,
397 STM_USB_EPR_STAT_RX_VALID,
398 STM_USB_EPR_STAT_TX_DISABLED);
400 /* Set up the IN end point */
401 ao_usb_bdt[AO_USB_IN_EPR].single.addr_tx = ao_usb_sram_addr;
402 ao_usb_bdt[AO_USB_IN_EPR].single.count_tx = 0;
403 ao_usb_in_tx_offset = ao_usb_sram_addr;
404 ao_usb_in_tx_buffer = ao_usb_packet_buffer_addr(ao_usb_in_tx_offset);
405 ao_usb_sram_addr += AO_USB_IN_SIZE;
407 ao_usb_init_ep(AO_USB_IN_EPR,
409 STM_USB_EPR_EP_TYPE_BULK,
410 STM_USB_EPR_STAT_RX_DISABLED,
411 STM_USB_EPR_STAT_TX_NAK);
416 static uint16_t control_count;
417 static uint16_t int_count;
418 static uint16_t in_count;
419 static uint16_t out_count;
420 static uint16_t reset_count;
422 /* The USB memory must be accessed in 16-bit units
426 ao_usb_copy_tx(const uint8_t *src, uint16_t *base, uint16_t bytes)
429 *base++ = src[0] | (src[1] << 8);
438 ao_usb_copy_rx(uint8_t *dst, uint16_t *base, uint16_t bytes)
441 uint16_t s = *base++;
451 /* Send an IN data packet */
453 ao_usb_ep0_flush(void)
457 /* Check to see if the endpoint is still busy */
458 if (ao_usb_epr_stat_tx(stm_usb.epr[0].r) == STM_USB_EPR_STAT_TX_VALID) {
459 debug("EP0 not accepting IN data\n");
463 this_len = ao_usb_ep0_in_len;
464 if (this_len > AO_USB_CONTROL_SIZE)
465 this_len = AO_USB_CONTROL_SIZE;
467 if (this_len < AO_USB_CONTROL_SIZE)
468 ao_usb_ep0_state = AO_USB_EP0_IDLE;
470 ao_usb_ep0_in_len -= this_len;
472 debug_data ("Flush EP0 len %d:", this_len);
473 ao_usb_copy_tx(ao_usb_ep0_in_data, ao_usb_ep0_tx_buffer, this_len);
475 ao_usb_ep0_in_data += this_len;
477 /* Mark the endpoint as TX valid to send the packet */
478 ao_usb_bdt[AO_USB_CONTROL_EPR].single.count_tx = this_len;
479 ao_usb_set_stat_tx(AO_USB_CONTROL_EPR, STM_USB_EPR_STAT_TX_VALID);
480 debug ("queue tx. epr 0 now %08x\n", stm_usb.epr[AO_USB_CONTROL_EPR]);
483 /* Read data from the ep0 OUT fifo */
485 ao_usb_ep0_fill(void)
487 uint16_t len = ao_usb_bdt[0].single.count_rx & STM_USB_BDT_COUNT_RX_COUNT_RX_MASK;
489 if (len > ao_usb_ep0_out_len)
490 len = ao_usb_ep0_out_len;
491 ao_usb_ep0_out_len -= len;
493 /* Pull all of the data out of the packet */
494 debug_data ("Fill EP0 len %d:", len);
495 ao_usb_copy_rx(ao_usb_ep0_out_data, ao_usb_ep0_rx_buffer, len);
497 ao_usb_ep0_out_data += len;
500 ao_usb_set_stat_rx(0, STM_USB_EPR_STAT_RX_VALID);
504 ao_usb_ep0_in_reset(void)
506 ao_usb_ep0_in_data = ao_usb_ep0_in_buf;
507 ao_usb_ep0_in_len = 0;
511 ao_usb_ep0_in_queue_byte(uint8_t a)
513 if (ao_usb_ep0_in_len < sizeof (ao_usb_ep0_in_buf))
514 ao_usb_ep0_in_buf[ao_usb_ep0_in_len++] = a;
518 ao_usb_ep0_in_set(const uint8_t *data, uint8_t len)
520 ao_usb_ep0_in_data = data;
521 ao_usb_ep0_in_len = len;
525 ao_usb_ep0_out_set(uint8_t *data, uint8_t len)
527 ao_usb_ep0_out_data = data;
528 ao_usb_ep0_out_len = len;
532 ao_usb_ep0_in_start(uint16_t max)
534 /* Don't send more than asked for */
535 if (ao_usb_ep0_in_len > max)
536 ao_usb_ep0_in_len = max;
540 static struct ao_usb_line_coding ao_usb_line_coding = {115200, 0, 0, 8};
542 /* Walk through the list of descriptors and find a match
545 ao_usb_get_descriptor(uint16_t value)
547 const uint8_t *descriptor;
548 uint8_t type = value >> 8;
549 uint8_t index = value;
551 descriptor = ao_usb_descriptors;
552 while (descriptor[0] != 0) {
553 if (descriptor[1] == type && index-- == 0) {
555 if (type == AO_USB_DESC_CONFIGURATION)
559 ao_usb_ep0_in_set(descriptor, len);
562 descriptor += descriptor[0];
567 ao_usb_ep0_setup(void)
569 /* Pull the setup packet out of the fifo */
570 ao_usb_ep0_out_set((uint8_t *) &ao_usb_setup, 8);
572 if (ao_usb_ep0_out_len != 0) {
573 debug ("invalid setup packet length\n");
577 if ((ao_usb_setup.dir_type_recip & AO_USB_DIR_IN) || ao_usb_setup.length == 0)
578 ao_usb_ep0_state = AO_USB_EP0_DATA_IN;
580 ao_usb_ep0_state = AO_USB_EP0_DATA_OUT;
582 ao_usb_ep0_in_reset();
584 switch(ao_usb_setup.dir_type_recip & AO_USB_SETUP_TYPE_MASK) {
585 case AO_USB_TYPE_STANDARD:
586 debug ("Standard setup packet\n");
587 switch(ao_usb_setup.dir_type_recip & AO_USB_SETUP_RECIP_MASK) {
588 case AO_USB_RECIP_DEVICE:
589 debug ("Device setup packet\n");
590 switch(ao_usb_setup.request) {
591 case AO_USB_REQ_GET_STATUS:
592 debug ("get status\n");
593 ao_usb_ep0_in_queue_byte(0);
594 ao_usb_ep0_in_queue_byte(0);
596 case AO_USB_REQ_SET_ADDRESS:
597 debug ("set address %d\n", ao_usb_setup.value);
598 ao_usb_address = ao_usb_setup.value;
599 ao_usb_address_pending = 1;
601 case AO_USB_REQ_GET_DESCRIPTOR:
602 debug ("get descriptor %d\n", ao_usb_setup.value);
603 ao_usb_get_descriptor(ao_usb_setup.value);
605 case AO_USB_REQ_GET_CONFIGURATION:
606 debug ("get configuration %d\n", ao_usb_configuration);
607 ao_usb_ep0_in_queue_byte(ao_usb_configuration);
609 case AO_USB_REQ_SET_CONFIGURATION:
610 ao_usb_configuration = ao_usb_setup.value;
611 debug ("set configuration %d\n", ao_usb_configuration);
612 ao_usb_set_configuration();
616 case AO_USB_RECIP_INTERFACE:
617 debug ("Interface setup packet\n");
618 switch(ao_usb_setup.request) {
619 case AO_USB_REQ_GET_STATUS:
620 ao_usb_ep0_in_queue_byte(0);
621 ao_usb_ep0_in_queue_byte(0);
623 case AO_USB_REQ_GET_INTERFACE:
624 ao_usb_ep0_in_queue_byte(0);
626 case AO_USB_REQ_SET_INTERFACE:
630 case AO_USB_RECIP_ENDPOINT:
631 debug ("Endpoint setup packet\n");
632 switch(ao_usb_setup.request) {
633 case AO_USB_REQ_GET_STATUS:
634 ao_usb_ep0_in_queue_byte(0);
635 ao_usb_ep0_in_queue_byte(0);
641 case AO_USB_TYPE_CLASS:
642 debug ("Class setup packet\n");
643 switch (ao_usb_setup.request) {
644 case AO_USB_SET_LINE_CODING:
645 debug ("set line coding\n");
646 ao_usb_ep0_out_set((uint8_t *) &ao_usb_line_coding, 7);
648 case AO_USB_GET_LINE_CODING:
649 debug ("get line coding\n");
650 ao_usb_ep0_in_set((const uint8_t *) &ao_usb_line_coding, 7);
652 case AO_USB_SET_CONTROL_LINE_STATE:
658 /* If we're not waiting to receive data from the host,
659 * queue an IN response
661 if (ao_usb_ep0_state == AO_USB_EP0_DATA_IN)
662 ao_usb_ep0_in_start(ao_usb_setup.length);
666 ao_usb_ep0_handle(uint8_t receive)
668 ao_usb_ep0_receive = 0;
669 if (receive & AO_USB_EP0_GOT_RESET) {
674 if (receive & AO_USB_EP0_GOT_SETUP) {
678 if (receive & AO_USB_EP0_GOT_RX_DATA) {
679 debug ("\tgot rx data\n");
680 if (ao_usb_ep0_state == AO_USB_EP0_DATA_OUT) {
682 if (ao_usb_ep0_out_len == 0) {
683 ao_usb_ep0_state = AO_USB_EP0_DATA_IN;
684 ao_usb_ep0_in_start(0);
688 if (receive & AO_USB_EP0_GOT_TX_ACK) {
689 debug ("\tgot tx ack\n");
691 #if HAS_FLIGHT && AO_USB_FORCE_IDLE
692 ao_flight_force_idle = 1;
694 /* Wait until the IN packet is received from addr 0
695 * before assigning our local address
697 if (ao_usb_address_pending)
698 ao_usb_set_address(ao_usb_address);
699 if (ao_usb_ep0_state == AO_USB_EP0_DATA_IN)
707 uint32_t istr = stm_usb.istr;
709 stm_usb.istr = ~istr;
710 if (istr & (1 << STM_USB_ISTR_CTR)) {
711 uint8_t ep = istr & STM_USB_ISTR_EP_ID_MASK;
712 uint16_t epr, epr_write;
714 /* Preserve the SW write bits, don't mess with most HW writable bits,
715 * clear the CTR_RX and CTR_TX bits
717 epr = stm_usb.epr[ep].r;
719 epr_write &= STM_USB_EPR_PRESERVE_MASK;
720 epr_write |= STM_USB_EPR_INVARIANT;
721 epr_write &= ~(1 << STM_USB_EPR_CTR_RX);
722 epr_write &= ~(1 << STM_USB_EPR_CTR_TX);
723 stm_usb.epr[ep].r = epr_write;
728 if (ao_usb_epr_ctr_rx(epr)) {
729 if (ao_usb_epr_setup(epr))
730 ao_usb_ep0_receive |= AO_USB_EP0_GOT_SETUP;
732 ao_usb_ep0_receive |= AO_USB_EP0_GOT_RX_DATA;
734 if (ao_usb_epr_ctr_tx(epr))
735 ao_usb_ep0_receive |= AO_USB_EP0_GOT_TX_ACK;
736 ao_usb_ep0_handle(ao_usb_ep0_receive);
740 if (ao_usb_epr_ctr_rx(epr)) {
741 _rx_dbg1("RX ISR", epr);
742 ao_usb_out_avail = 1;
743 _rx_dbg0("out avail set");
744 ao_wakeup(AO_USB_OUT_SLEEP_ADDR);
745 _rx_dbg0("stdin awoken");
750 _tx_dbg1("TX ISR", epr);
751 if (ao_usb_epr_ctr_tx(epr)) {
752 ao_usb_in_pending = 0;
753 ao_wakeup(&ao_usb_in_pending);
758 if (ao_usb_epr_ctr_tx(epr))
759 _ao_usb_set_stat_tx(AO_USB_INT_EPR, STM_USB_EPR_STAT_TX_NAK);
765 if (istr & (1 << STM_USB_ISTR_RESET)) {
767 ao_usb_ep0_receive |= AO_USB_EP0_GOT_RESET;
768 ao_usb_ep0_handle(ao_usb_ep0_receive);
773 /* Queue the current IN buffer for transmission */
775 _ao_usb_in_send(void)
777 _tx_dbg0("in_send start");
778 debug ("send %d\n", ao_usb_tx_count);
779 while (ao_usb_in_pending)
780 ao_sleep(&ao_usb_in_pending);
781 ao_usb_in_pending = 1;
782 if (ao_usb_tx_count != AO_USB_IN_SIZE)
783 ao_usb_in_flushed = 1;
784 ao_usb_copy_tx(ao_usb_tx_buffer, ao_usb_in_tx_buffer, ao_usb_tx_count);
785 ao_usb_bdt[AO_USB_IN_EPR].single.addr_tx = ao_usb_in_tx_offset;
786 ao_usb_bdt[AO_USB_IN_EPR].single.count_tx = ao_usb_tx_count;
788 _ao_usb_set_stat_tx(AO_USB_IN_EPR, STM_USB_EPR_STAT_TX_VALID);
789 _tx_dbg0("in_send end");
792 /* Wait for a free IN buffer. Interrupts are blocked */
794 _ao_usb_in_wait(void)
797 /* Check if the current buffer is writable */
798 if (ao_usb_tx_count < AO_USB_IN_SIZE)
801 _tx_dbg0("in_wait top");
802 /* Wait for an IN buffer to be ready */
803 while (ao_usb_in_pending)
804 ao_sleep(&ao_usb_in_pending);
805 _tx_dbg0("in_wait bottom");
815 /* Anytime we've sent a character since
816 * the last time we flushed, we'll need
817 * to send a packet -- the only other time
818 * we would send a packet is when that
819 * packet was full, in which case we now
820 * want to send an empty packet
822 ao_arch_block_interrupts();
823 while (!ao_usb_in_flushed) {
824 _tx_dbg0("flush top");
826 _tx_dbg0("flush end");
828 ao_arch_release_interrupts();
832 ao_usb_putchar(char c)
837 ao_arch_block_interrupts();
840 ao_usb_in_flushed = 0;
841 ao_usb_tx_buffer[ao_usb_tx_count++] = (uint8_t) c;
843 /* Send the packet when full */
844 if (ao_usb_tx_count == AO_USB_IN_SIZE) {
845 _tx_dbg0("putchar full");
847 _tx_dbg0("putchar flushed");
849 ao_arch_release_interrupts();
853 _ao_usb_out_recv(void)
855 _rx_dbg0("out_recv top");
856 ao_usb_out_avail = 0;
858 ao_usb_rx_count = ao_usb_bdt[AO_USB_OUT_EPR].single.count_rx & STM_USB_BDT_COUNT_RX_COUNT_RX_MASK;
860 _rx_dbg1("out_recv count", ao_usb_rx_count);
861 debug ("recv %d\n", ao_usb_rx_count);
862 debug_data("Fill OUT len %d:", ao_usb_rx_count);
863 ao_usb_copy_rx(ao_usb_rx_buffer, ao_usb_out_rx_buffer, ao_usb_rx_count);
868 _ao_usb_set_stat_rx(AO_USB_OUT_EPR, STM_USB_EPR_STAT_RX_VALID);
872 _ao_usb_pollchar(void)
877 return AO_READ_AGAIN;
880 if (ao_usb_rx_pos != ao_usb_rx_count)
883 _rx_dbg0("poll check");
884 /* Check to see if a packet has arrived */
885 if (!ao_usb_out_avail) {
886 _rx_dbg0("poll none");
887 return AO_READ_AGAIN;
892 /* Pull a character out of the fifo */
893 c = ao_usb_rx_buffer[ao_usb_rx_pos++];
902 ao_arch_block_interrupts();
903 while ((c = _ao_usb_pollchar()) == AO_READ_AGAIN)
904 ao_sleep(AO_USB_OUT_SLEEP_ADDR);
905 ao_arch_release_interrupts();
917 buffer = ao_usb_packet_buffer_addr(ao_usb_sram_addr);
918 ao_usb_sram_addr += AO_USB_IN_SIZE;
923 ao_usb_free(uint16_t *addr)
925 uint16_t offset = ao_usb_packet_buffer_offset(addr);
926 if (offset < ao_usb_sram_addr)
927 ao_usb_sram_addr = offset;
931 ao_usb_write(uint16_t *buffer, uint16_t len)
933 ao_arch_block_interrupts();
935 /* Flush any pending regular */
939 while (ao_usb_in_pending)
940 ao_sleep(&ao_usb_in_pending);
941 ao_usb_in_pending = 1;
942 ao_usb_in_flushed = (len != AO_USB_IN_SIZE);
943 ao_usb_bdt[AO_USB_IN_EPR].single.addr_tx = ao_usb_packet_buffer_offset(buffer);
944 ao_usb_bdt[AO_USB_IN_EPR].single.count_tx = len;
945 _ao_usb_set_stat_tx(AO_USB_IN_EPR, STM_USB_EPR_STAT_TX_VALID);
946 ao_arch_release_interrupts();
953 ao_arch_block_interrupts();
954 stm_usb.cntr = (1 << STM_USB_CNTR_FRES);
957 /* Disable USB pull-up */
958 stm_usb.bcdr &= ~(1 << STM_USB_BCDR_DPPU);
960 /* Switch off the device */
961 stm_usb.cntr = (1 << STM_USB_CNTR_PDWN) | (1 << STM_USB_CNTR_FRES);
963 /* Disable the interface */
964 stm_rcc.apb1enr &= ~(1 << STM_RCC_APB1ENR_USBEN);
965 ao_arch_release_interrupts();
973 /* Select HSI48 as USB clock source */
974 stm_rcc.cfgr3 &= ~(1 << STM_RCC_CFGR3_USBSW);
976 /* Enable USB device */
977 stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_USBEN);
979 /* Clear reset condition */
980 stm_rcc.apb1rstr &= ~(1 << STM_RCC_APB1RSTR_USBRST);
982 /* Disable USB pull-up */
983 stm_usb.bcdr &= ~(1 << STM_USB_BCDR_DPPU);
985 /* Do not touch the GPIOA configuration; USB takes priority
986 * over GPIO on pins A11 and A12, but if you select alternate
987 * input 10 (the documented correct selection), then USB is
988 * pulled low and doesn't work at all
991 ao_arch_block_interrupts();
993 /* Route interrupts */
994 stm_nvic_set_enable(STM_ISR_USB_POS);
995 stm_nvic_set_priority(STM_ISR_USB_POS, 3);
997 ao_usb_configuration = 0;
999 /* Set up buffer descriptors */
1000 ao_usb_init_btable();
1002 /* Reset the USB controller */
1003 stm_usb.cntr = (1 << STM_USB_CNTR_FRES);
1005 /* Clear the reset bit */
1008 /* Clear any spurious interrupts */
1013 debug ("ao_usb_enable\n");
1015 /* Enable interrupts */
1016 stm_usb.cntr = ((1 << STM_USB_CNTR_CTRM) |
1017 (0 << STM_USB_CNTR_PMAOVRM) |
1018 (0 << STM_USB_CNTR_ERRM) |
1019 (0 << STM_USB_CNTR_WKUPM) |
1020 (0 << STM_USB_CNTR_SUSPM) |
1021 (1 << STM_USB_CNTR_RESETM) |
1022 (0 << STM_USB_CNTR_SOFM) |
1023 (0 << STM_USB_CNTR_ESOFM) |
1024 (0 << STM_USB_CNTR_RESUME) |
1025 (0 << STM_USB_CNTR_FSUSP) |
1026 (0 << STM_USB_CNTR_LP_MODE) |
1027 (0 << STM_USB_CNTR_PDWN) |
1028 (0 << STM_USB_CNTR_FRES));
1030 ao_arch_release_interrupts();
1032 for (t = 0; t < 1000; t++)
1035 /* Enable USB pull-up */
1036 stm_usb.bcdr |= (1 << STM_USB_BCDR_DPPU);
1040 struct ao_task ao_usb_echo_task;
1048 c = ao_usb_getchar();
1059 printf ("control: %d out: %d in: %d int: %d reset: %d\n",
1060 control_count, out_count, in_count, int_count, reset_count);
1063 __code struct ao_cmds ao_usb_cmds[] = {
1064 { ao_usb_irq, "I\0Show USB interrupt counts" },
1074 debug ("ao_usb_init\n");
1075 ao_usb_ep0_state = AO_USB_EP0_IDLE;
1077 ao_add_task(&ao_usb_echo_task, ao_usb_echo, "usb echo");
1080 ao_cmd_register(&ao_usb_cmds[0]);
1084 ao_add_stdio(_ao_usb_pollchar, ao_usb_putchar, ao_usb_flush);
1089 #if TX_DBG || RX_DBG
1099 uint32_t in_pending;
1101 uint32_t in_flushed;
1111 #define NUM_USB_DBG 128
1113 static struct ao_usb_dbg dbg[128];
1116 static void _dbg(int line, char *msg, uint32_t value)
1119 dbg[dbg_i].line = line;
1120 dbg[dbg_i].msg = msg;
1121 dbg[dbg_i].value = value;
1122 asm("mrs %0,primask" : "=&r" (primask));
1123 dbg[dbg_i].primask = primask;
1125 dbg[dbg_i].in_count = in_count;
1126 dbg[dbg_i].in_epr = stm_usb.epr[AO_USB_IN_EPR];
1127 dbg[dbg_i].in_pending = ao_usb_in_pending;
1128 dbg[dbg_i].tx_count = ao_usb_tx_count;
1129 dbg[dbg_i].in_flushed = ao_usb_in_flushed;
1132 dbg[dbg_i].rx_count = ao_usb_rx_count;
1133 dbg[dbg_i].rx_pos = ao_usb_rx_pos;
1134 dbg[dbg_i].out_avail = ao_usb_out_avail;
1135 dbg[dbg_i].out_epr = stm_usb.epr[AO_USB_OUT_EPR];
1137 if (++dbg_i == NUM_USB_DBG)