2 * Copyright © 2023 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation, either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
24 typedef volatile uint32_t vuint32_t;
25 typedef volatile uint16_t vuint16_t;
26 typedef volatile void * vvoid_t;
45 extern struct stm_rcc stm_rcc;
47 //#define stm_rcc (*((struct stm_rcc *) 0x40021000))
49 #define STM_RCC_CR_RTCPRE (29)
50 #define STM_RCC_CR_RTCPRE_HSE_DIV_2 0
51 #define STM_RCC_CR_RTCPRE_HSE_DIV_4 1
52 #define STM_RCC_CR_RTCPRE_HSE_DIV_8 2
53 #define STM_RCC_CR_RTCPRE_HSE_DIV_16 3
54 #define STM_RCC_CR_RTCPRE_HSE_MASK 3UL
56 #define STM_RCC_CR_PLL3RDY (29)
57 #define STM_RCC_CR_PLL3ON (28)
58 #define STM_RCC_CR_PLL2RDY (27)
59 #define STM_RCC_CR_PLL2ON (26)
60 #define STM_RCC_CR_PLLRDY (25)
61 #define STM_RCC_CR_PLLON (24)
62 #define STM_RCC_CR_CSSON (19)
63 #define STM_RCC_CR_HSEBYP (18)
64 #define STM_RCC_CR_HSERDY (17)
65 #define STM_RCC_CR_HSEON (16)
66 #define STM_RCC_CR_HSICAL (8)
67 #define STM_RCC_CR_HSITRIM (3)
68 #define STM_RCC_CR_HSIRDY (1)
69 #define STM_RCC_CR_HSION (0)
71 #define STM_RCC_CFGR_MCOPRE (28)
72 #define STM_RCC_CFGR_MCOPRE_DIV_1 0
73 #define STM_RCC_CFGR_MCOPRE_DIV_2 1
74 #define STM_RCC_CFGR_MCOPRE_DIV_4 2
75 #define STM_RCC_CFGR_MCOPRE_DIV_8 3
76 #define STM_RCC_CFGR_MCOPRE_DIV_16 4
77 #define STM_RCC_CFGR_MCOPRE_MASK 7UL
79 #define STM_RCC_CFGR_MCO (24)
80 #define STM_RCC_CFGR_MCO_DISABLE 0
81 #define STM_RCC_CFGR_MCO_SYSCLK 4
82 #define STM_RCC_CFGR_MCO_HSI 5
83 #define STM_RCC_CFGR_MCO_HSE 6
84 #define STM_RCC_CFGR_MCO_PLL_2 7
85 #define STM_RCC_CFGR_MCO_MASK 7UL
87 #define STM_RCC_CFGR_USBPRE (22)
88 #define STM_RCC_CFGR_USBPRE_1_5 0
89 #define STM_RCC_CFGR_USBPRE_1 1
91 #define STM_RCC_CFGR_PLLMUL (18)
92 #define STM_RCC_CFGR_PLLMUL_2 0
93 #define STM_RCC_CFGR_PLLMUL_3 1
94 #define STM_RCC_CFGR_PLLMUL_4 2
95 #define STM_RCC_CFGR_PLLMUL_5 3
96 #define STM_RCC_CFGR_PLLMUL_6 4
97 #define STM_RCC_CFGR_PLLMUL_7 5
98 #define STM_RCC_CFGR_PLLMUL_8 6
99 #define STM_RCC_CFGR_PLLMUL_9 7
100 #define STM_RCC_CFGR_PLLMUL_10 8
101 #define STM_RCC_CFGR_PLLMUL_11 9
102 #define STM_RCC_CFGR_PLLMUL_12 10
103 #define STM_RCC_CFGR_PLLMUL_13 11
104 #define STM_RCC_CFGR_PLLMUL_14 12
105 #define STM_RCC_CFGR_PLLMUL_15 13
106 #define STM_RCC_CFGR_PLLMUL_16 14
107 #define STM_RCC_CFGR_PLLMUL_MASK 0xfUL
109 #define STM_RCC_CFGR_PLLXTPRE (17)
110 #define STM_RCC_CFGR_PLLXTPRE_1 0
111 #define STM_RCC_CFGR_PLLXTPRE_2 1
113 #define STM_RCC_CFGR_PLLSRC (16)
114 #define STM_RCC_CFGR_PLLSRC_HSI_2 0
115 #define STM_RCC_CFGR_PLLSRC_HSE 1
117 #define STM_RCC_CFGR_ADCPRE (14)
118 #define STM_RCC_CFGR_ADCPRE_2 0
119 #define STM_RCC_CFGR_ADCPRE_4 1
120 #define STM_RCC_CFGR_ADCPRE_6 2
121 #define STM_RCC_CFGR_ADCPRE_8 3
123 #define STM_RCC_CFGR_PPRE2 (11)
124 #define STM_RCC_CFGR_PPRE2_DIV_1 0
125 #define STM_RCC_CFGR_PPRE2_DIV_2 4
126 #define STM_RCC_CFGR_PPRE2_DIV_4 5
127 #define STM_RCC_CFGR_PPRE2_DIV_8 6
128 #define STM_RCC_CFGR_PPRE2_DIV_16 7
129 #define STM_RCC_CFGR_PPRE2_MASK 7UL
131 #define STM_RCC_CFGR_PPRE1 (8)
132 #define STM_RCC_CFGR_PPRE1_DIV_1 0
133 #define STM_RCC_CFGR_PPRE1_DIV_2 4
134 #define STM_RCC_CFGR_PPRE1_DIV_4 5
135 #define STM_RCC_CFGR_PPRE1_DIV_8 6
136 #define STM_RCC_CFGR_PPRE1_DIV_16 7
137 #define STM_RCC_CFGR_PPRE1_MASK 7UL
139 #define STM_RCC_CFGR_HPRE (4)
140 #define STM_RCC_CFGR_HPRE_DIV_1 0
141 #define STM_RCC_CFGR_HPRE_DIV_2 8
142 #define STM_RCC_CFGR_HPRE_DIV_4 9
143 #define STM_RCC_CFGR_HPRE_DIV_8 0xa
144 #define STM_RCC_CFGR_HPRE_DIV_16 0xb
145 #define STM_RCC_CFGR_HPRE_DIV_64 0xc
146 #define STM_RCC_CFGR_HPRE_DIV_128 0xd
147 #define STM_RCC_CFGR_HPRE_DIV_256 0xe
148 #define STM_RCC_CFGR_HPRE_DIV_512 0xf
149 #define STM_RCC_CFGR_HPRE_MASK 0xfUL
151 #define STM_RCC_CFGR_SWS (2)
152 #define STM_RCC_CFGR_SWS_HSI 0
153 #define STM_RCC_CFGR_SWS_HSE 1
154 #define STM_RCC_CFGR_SWS_PLL 2
155 #define STM_RCC_CFGR_SWS_MASK 3UL
157 #define STM_RCC_CFGR_SW (0)
158 #define STM_RCC_CFGR_SW_HSI 0
159 #define STM_RCC_CFGR_SW_HSE 1
160 #define STM_RCC_CFGR_SW_PLL 2
161 #define STM_RCC_CFGR_SW_MASK 3UL
163 #define STM_RCC_AHBENR_CRCEN 6
164 #define STM_RCC_AHBENR_FLITFEN 4
165 #define STM_RCC_AHBENR_SRAMEN 2
166 #define STM_RCC_AHBENR_DMA2EN 1
167 #define STM_RCC_AHBENR_DMA1EN 0
170 #define STM_RCC_APB2ENR_USART1EN 14
171 #define STM_RCC_APB2ENR_SPI1EN 12
172 #define STM_RCC_APB2ENR_TIM1EN 11
173 #define STM_RCC_APB2ENR_ADC2EN 10
174 #define STM_RCC_APB2ENR_ADC1EN 9
175 #define STM_RCC_APB2ENR_IOPEEN 6
176 #define STM_RCC_APB2ENR_IOPDEN 5
177 #define STM_RCC_APB2ENR_IOPCEN 4
178 #define STM_RCC_APB2ENR_IOPBEN 3
179 #define STM_RCC_APB2ENR_IOPAEN 2
180 #define STM_RCC_APB2ENR_AFIOEN 0
182 #define STM_RCC_APB1ENR_DACEN 29
183 #define STM_RCC_APB1ENR_PWREN 28
184 #define STM_RCC_APB1ENR_BKPEN 27
185 #define STM_RCC_APB1ENR_CANEN 26
186 #define STM_RCC_APB1ENR_USBEN 23
187 #define STM_RCC_APB1ENR_I2C2EN 22
188 #define STM_RCC_APB1ENR_I2C1EN 21
189 #define STM_RCC_APB1ENR_UART5EN 20
190 #define STM_RCC_APB1ENR_UART4EN 19
191 #define STM_RCC_APB1ENR_USART3EN 18
192 #define STM_RCC_APB1ENR_USART2EN 17
193 #define STM_RCC_APB1ENR_SPI3EN 15
194 #define STM_RCC_APB1ENR_SPI2EN 14
195 #define STM_RCC_APB1ENR_WWDGEN 11
196 #define STM_RCC_APB1ENR_TIM14EN 8
197 #define STM_RCC_APB1ENR_TIM13EN 7
198 #define STM_RCC_APB1ENR_TIM12EN 6
199 #define STM_RCC_APB1ENR_TIM7EN 5
200 #define STM_RCC_APB1ENR_TIM6EN 4
201 #define STM_RCC_APB1ENR_TIM5EN 3
202 #define STM_RCC_APB1ENR_TIM4EN 2
203 #define STM_RCC_APB1ENR_TIM3EN 1
204 #define STM_RCC_APB1ENR_TIM2EN 0
206 #define STM_RCC_CSR_LPWRRSTF (31)
207 #define STM_RCC_CSR_WWDGRSTF (30)
208 #define STM_RCC_CSR_IWDGRSTF (29)
209 #define STM_RCC_CSR_SFTRSTF (28)
210 #define STM_RCC_CSR_PORRSTF (27)
211 #define STM_RCC_CSR_PINRSTF (26)
212 #define STM_RCC_CSR_RMVF (24)
213 #define STM_RCC_CSR_LSIRDY (1)
214 #define STM_RCC_CSR_LSION (0)
223 extern struct stm_systick stm_systick;
225 //#define stm_systick (*((struct stm_systick *) 0xe000e010))
227 #define STM_SYSTICK_CTRL_ENABLE 0
228 #define STM_SYSTICK_CTRL_TICKINT 1
229 #define STM_SYSTICK_CTRL_CLKSOURCE 2
230 #define STM_SYSTICK_CTRL_CLKSOURCE_HCLK_8 0
231 #define STM_SYSTICK_CTRL_CLKSOURCE_HCLK 1
232 #define STM_SYSTICK_CTRL_COUNTFLAG 16
234 /* The NVIC starts at 0xe000e100, so add that to the offsets to find the absolute address */
237 vuint32_t iser[3]; /* 0x000 0xe000e100 Set Enable Register */
239 uint8_t _unused00c[0x080 - 0x00c];
241 vuint32_t icer[3]; /* 0x080 0xe000e180 Clear Enable Register */
243 uint8_t _unused08c[0x100 - 0x08c];
245 vuint32_t ispr[3]; /* 0x100 0xe000e200 Set Pending Register */
247 uint8_t _unused10c[0x180 - 0x10c];
249 vuint32_t icpr[3]; /* 0x180 0xe000e280 Clear Pending Register */
251 uint8_t _unused18c[0x200 - 0x18c];
253 vuint32_t iabr[3]; /* 0x200 0xe000e300 Active Bit Register */
255 uint8_t _unused20c[0x300 - 0x20c];
257 vuint32_t ipr[31]; /* 0x300 0xe000e400 Priority Register */
259 uint8_t _unused37c[0xe00 - 0x37c]; /* covers SCB */
261 vuint32_t stir; /* 0xe00 0xe000ee00 Software Trigger Interrupt Register */
264 extern struct stm_nvic stm_nvic;
266 //#define stm_nvic (*((struct stm_nvic *) 0xe000e100))
268 #define IRQ_REG(irq) ((irq) >> 5)
269 #define IRQ_BIT(irq) ((irq) & 0x1f)
270 #define IRQ_MASK(irq) (1 << IRQ_BIT(irq))
271 #define IRQ_BOOL(v,irq) (((v) >> IRQ_BIT(irq)) & 1)
274 stm_nvic_set_enable(int irq) {
275 stm_nvic.iser[IRQ_REG(irq)] = IRQ_MASK(irq);
279 stm_nvic_clear_enable(int irq) {
280 stm_nvic.icer[IRQ_REG(irq)] = IRQ_MASK(irq);
284 stm_nvic_enabled(int irq) {
285 return IRQ_BOOL(stm_nvic.iser[IRQ_REG(irq)], irq);
289 stm_nvic_set_pending(int irq) {
290 stm_nvic.ispr[IRQ_REG(irq)] = IRQ_MASK(irq);
294 stm_nvic_clear_pending(int irq) {
295 stm_nvic.icpr[IRQ_REG(irq)] = IRQ_MASK(irq);
299 stm_nvic_pending(int irq) {
300 return IRQ_BOOL(stm_nvic.ispr[IRQ_REG(irq)], irq);
304 stm_nvic_active(int irq) {
305 return IRQ_BOOL(stm_nvic.iabr[IRQ_REG(irq)], irq);
308 #define IRQ_PRIO_REG(irq) ((irq) >> 2)
309 #define IRQ_PRIO_BIT(irq) (((irq) & 3) << 3)
310 #define IRQ_PRIO_MASK(irq) (0xff << IRQ_PRIO_BIT(irq))
313 stm_nvic_set_priority(int irq, uint8_t prio) {
314 int n = IRQ_PRIO_REG(irq);
318 v &= (uint32_t) ~IRQ_PRIO_MASK(irq);
319 v |= (prio) << IRQ_PRIO_BIT(irq);
323 static inline uint8_t
324 stm_nvic_get_priority(int irq) {
325 return (stm_nvic.ipr[IRQ_PRIO_REG(irq)] >> IRQ_PRIO_BIT(irq)) & IRQ_PRIO_MASK(0);
349 extern struct stm_scb stm_scb;
351 #define STM_SCB_AIRCR_VECTKEY 16
352 #define STM_SCB_AIRCR_VECTKEY_KEY 0x05fa
353 #define STM_SCB_AIRCR_PRIGROUP 8
354 #define STM_SCB_AIRCR_SYSRESETREQ 2
355 #define STM_SCB_AIRCR_VECTCLRACTIVE 1
356 #define STM_SCB_AIRCR_VECTRESET 0
372 extern struct stm_flash stm_flash;
374 //#define stm_flash (*((struct stm_flash *) 0x40022000))
376 #define STM_FLASH_ACR_PRFTBS 5
377 #define STM_FLASH_ACR_PRFTBE 4
378 #define STM_FLASH_ACR_HLFCYA 3
379 #define STM_FLASH_ACR_LATENCY 0
380 #define STM_FLASH_ACR_LATENCY_0 0
381 #define STM_FLASH_ACR_LATENCY_1 1
382 #define STM_FLASH_ACR_LATENCY_2 2
384 #define STM_FLASH_SR_EOP 5
385 #define STM_FLASH_SR_WRPRTERR 4
386 #define STM_FLASH_SR_PGERR 2
387 #define STM_FLASH_SR_BSY 0
389 #define STM_FLASH_CR_EOPIE 12
390 #define STM_FLASH_CR_ERRIE 10
391 #define STM_FLASH_CR_OPTWRE 9
392 #define STM_FLASH_CR_LOCK 7
393 #define STM_FLASH_CR_STRT 6
394 #define STM_FLASH_CR_OPTER 5
395 #define STM_FLASH_CR_OPTPG 4
396 #define STM_FLASH_CR_MER 2
397 #define STM_FLASH_CR_PER 1
398 #define STM_FLASH_CR_PG 0
400 #define STM_FLASH_RDPRT_KEY 0x00A5
401 #define STM_FLASH_FPEC_KEY1 0x45670123
402 #define STM_FLASH_FPEC_KEY2 0xCDEF89AB
405 struct stm_flash_data {
409 vuint32_t device_id[3];
412 extern struct stm_flash_data stm_flash_data;
414 static inline uint32_t stm_flash_size(void) { return (uint32_t) stm_flash_data.f_size * 1024; }
416 //#define stm_flash_data (*((struct stm_flash_data *) 0x1ffff7e0))
428 #define STM_GPIO_CR(y) ((uint8_t) (y) >> 3)
429 #define STM_GPIO_CR_CNF(y) ((((uint8_t) (y) & 7) << 2) + 2)
430 #define STM_GPIO_CR_CNF_INPUT_ANALOG 0
431 #define STM_GPIO_CR_CNF_INPUT_FLOATING 1
432 #define STM_GPIO_CR_CNF_INPUT_PULL 2
433 #define STM_GPIO_CR_CNF_OUTPUT_PUSH_PULL 0
434 #define STM_GPIO_CR_CNF_OUTPUT_OPEN_DRAIN 1
435 #define STM_GPIO_CR_CNF_OUTPUT_AF_PUSH_PULL 2
436 #define STM_GPIO_CR_CNF_OUTPUT_AF_OPEN_DRAIN 3
437 #define STM_GPIO_CR_CNF_MASK 3U
438 #define STM_GPIO_CR_MODE(y) ((((y) & 7) << 2))
439 #define STM_GPIO_CR_MODE_INPUT 0
440 #define STM_GPIO_CR_MODE_OUTPUT_10MHZ 1
441 #define STM_GPIO_CR_MODE_OUTPUT_2MHZ 2
442 #define STM_GPIO_CR_MODE_OUTPUT_50MHZ 3
443 #define STM_GPIO_CR_MODE_MASK 3U
446 stm_gpio_conf(struct stm_gpio *gpio, int pin, uint8_t mode, uint8_t cnf)
448 uint8_t cr = STM_GPIO_CR(pin);
449 uint32_t v = gpio->cr[cr];
451 v &= ~((STM_GPIO_CR_CNF_MASK << STM_GPIO_CR_CNF(pin)) |
452 (STM_GPIO_CR_MODE_MASK << STM_GPIO_CR_MODE(pin)));
453 v |= (mode << STM_GPIO_CR_MODE(pin)) | (cnf << STM_GPIO_CR_CNF(pin));
458 stm_gpio_set(struct stm_gpio *gpio, int pin, uint8_t value) {
459 /* Use the bit set/reset register to do this atomically */
460 gpio->bsrr = ((uint32_t) (value ^ 1) << (pin + 16)) | ((uint32_t) value << pin);
464 stm_gpio_set_mask(struct stm_gpio *gpio, uint16_t bits, uint16_t mask) {
465 /* Use the bit set/reset register to do this atomically */
466 gpio->bsrr = ((uint32_t) (~bits & mask) << 16) | ((uint32_t) (bits & mask));
470 stm_gpio_set_bits(struct stm_gpio *gpio, uint16_t bits) {
475 stm_gpio_clr_bits(struct stm_gpio *gpio, uint16_t bits) {
476 gpio->bsrr = ((uint32_t) bits) << 16;
479 static inline uint8_t
480 stm_gpio_get(struct stm_gpio *gpio, int pin) {
481 return (gpio->idr >> pin) & 1;
484 static inline uint16_t
485 stm_gpio_get_all(struct stm_gpio *gpio) {
486 return (uint16_t) gpio->idr;
489 extern struct stm_gpio stm_gpioa;
490 extern struct stm_gpio stm_gpiob;
491 extern struct stm_gpio stm_gpioc;
492 extern struct stm_gpio stm_gpiod;
493 extern struct stm_gpio stm_gpioe;
495 //#define stm_gpioe (*((struct stm_gpio *) 0x40011800))
496 //#define stm_gpiod (*((struct stm_gpio *) 0x40011400))
497 //#define stm_gpioc (*((struct stm_gpio *) 0x40011000))
498 //#define stm_gpiob (*((struct stm_gpio *) 0x40010c00))
499 //#define stm_gpioa (*((struct stm_gpio *) 0x40010800))
508 extern struct stm_afio stm_afio;
510 //#define stm_afio (*((struct stm_afio *) 0x40010000))
512 #define STM_AFIO_MAPR_ADC2_ETRGREG_REMAP 20
513 #define STM_AFIO_MAPR_ADC2_ETRGINJ_REMAP 19
514 #define STM_AFIO_MAPR_ADC1_ETRGREG_REMAP 18
515 #define STM_AFIO_MAPR_ADC1_ETRGINJ_REMAP 17
516 #define STM_AFIO_MAPR_TIM5CH4_IREMAP 16
517 #define STM_AFIO_MAPR_PD01_REMAP 15
518 #define STM_AFIO_MAPR_CAN_REMAP 13
519 #define STM_AFIO_MAPR_CAN_REMAP_PA11_PA12 0
520 #define STM_AFIO_MAPR_CAN_REMAP_PB8_PB9 2
521 #define STM_AFIO_MAPR_CAN_REMAP_PD0_PD1 3
522 #define STM_AFIO_MAPR_CAN_REMAP_MASK 3
523 #define STM_AFIO_MAPR_TIM4_REMAP 12
524 #define STM_AFIO_MAPR_TIM3_REMAP 10
525 #define STM_AFIO_MAPR_TIM3_REMAP_PA6_PA7_PB0_PB1 0
526 #define STM_AFIO_MAPR_TIM3_REMAP_PB4_PB5_PB0_PB1 2
527 #define STM_AFIO_MAPR_TIM3_REMAP_PC6_PC7_PC8_PC9 3
528 #define STM_AFIO_MAPR_TIM3_REMAP_MASK 3
529 #define STM_AFIO_MAPR_TIM2_REMAP 8
530 #define STM_AFIO_MAPR_TIM2_REMAP_PA0_PA1_PA2_PA3 0
531 #define STM_AFIO_MAPR_TIM2_REMAP_PA15_PB3_PA2_PA3 1
532 #define STM_AFIO_MAPR_TIM2_REMAP_PA0_PA1_PB10_PB11 2
533 #define STM_AFIO_MAPR_TIM2_REMAP_PA15_PB3_PB10_PB11 3
534 #define STM_AFIO_MAPR_TIM2_REMAP_MASK 3
535 #define STM_AFIO_MAPR_TIM1_REMAP 6
536 #define STM_AFIO_MAPR_TIM1_REMAP_PA12_PA8_PA9_PA10_PA11_PB12_PB13_PB14_PB15 0
537 #define STM_AFIO_MAPR_TIM1_REMAP_PA12_PA8_PA9_PA10_PA11_PA6_PA7_PB0_PB1 1
538 #define STM_AFIO_MAPR_TIM1_REMAP_PE7_PE9_PE11_PE13_PE14_PE15_PE8_PE10_PE12 3
539 #define STM_AFIO_MAPR_TIM1_REMAP_MASK 3
540 #define STM_AFIO_MAPR_USART3_REMAP 4
541 #define STM_AFIO_MAPR_USART3_REMAP_PB10_PB11_PB12_PB13_PB14 0
542 #define STM_AFIO_MAPR_USART3_REMAP_PC10_PC11_PC12_PB13_PB14 1
543 #define STM_AFIO_MAPR_USART3_REMAP_PD8_PD9_PD10_PD11_PD12 3
544 #define STM_AFIO_MAPR_USART3_REMAP_MASK 3
545 #define STM_AFIO_MAPR_USART2_REMAP 3
546 #define STM_AFIO_MAPR_USART2_REMAP_PA0_PA1_PA2_PA3_PA4 0
547 #define STM_AFIO_MAPR_USART2_REMAP_PD3_PD4_PD5_PD6_PD7 1
548 #define STM_AFIO_MAPR_USART2_REMAP_MASK 1
549 #define STM_AFIO_MAPR_USART1_REMAP 2
550 #define STM_AFIO_MAPR_USART1_REMAP_PA9_PA10 0
551 #define STM_AFIO_MAPR_USART1_REMAP_PB6_PB7 1
552 #define STM_AFIO_MAPR_USART1_REMAP_MASK 1
553 #define STM_AFIO_MAPR_I2C1_REMAP 1
554 #define STM_AFIO_MAPR_I2C1_REMAP_PB6_PB7 0
555 #define STM_AFIO_MAPR_I2C1_REMAP_PB8_PB9 1
556 #define STM_AFIO_MAPR_I2C1_REMAP_MASK 1
557 #define STM_AFIO_MAPR_SPI1_REMAP 0
558 #define STM_AFIO_MAPR_SPI1_REMAP_PA4_PA5_PA6_PA7 0
559 #define STM_AFIO_MAPR_SPI1_REMAP_PA15_PB3_PB4_PB5 1
560 #define STM_AFIO_MAPR_SPI1_REMAP_MASK 1
563 stm_set_afio_mapr(uint8_t bit, uint32_t val, uint32_t mask) {
564 uint32_t mapr = stm_afio.mapr;
566 mapr &= ~(mask << bit);
567 mapr |= (val << bit);
568 stm_afio.mapr = mapr;
572 vuint32_t sr; /* status register */
573 vuint32_t dr; /* data register */
574 vuint32_t brr; /* baud rate register */
575 vuint32_t cr1; /* control register 1 */
577 vuint32_t cr2; /* control register 2 */
578 vuint32_t cr3; /* control register 3 */
579 vuint32_t gtpr; /* guard time and prescaler */
582 extern struct stm_usart stm_usart1;
583 extern struct stm_usart stm_usart2;
584 extern struct stm_usart stm_usart3;
586 //#define stm_usart1 (*((struct stm_usart *) 0x40013800))
587 //#define stm_usart2 (*((struct stm_usart *) 0x40004800))
588 //#define stm_usart3 (*((struct stm_usart *) 0x40004400))
590 #define STM_USART_SR_CTS (9) /* CTS flag */
591 #define STM_USART_SR_LBD (8) /* LIN break detection flag */
592 #define STM_USART_SR_TXE (7) /* Transmit data register empty */
593 #define STM_USART_SR_TC (6) /* Transmission complete */
594 #define STM_USART_SR_RXNE (5) /* Read data register not empty */
595 #define STM_USART_SR_IDLE (4) /* IDLE line detected */
596 #define STM_USART_SR_ORE (3) /* Overrun error */
597 #define STM_USART_SR_NE (2) /* Noise detected flag */
598 #define STM_USART_SR_FE (1) /* Framing error */
599 #define STM_USART_SR_PE (0) /* Parity error */
601 #define STM_USART_BRR_DIV_MANTISSA (4)
602 #define STM_USART_BRR_DIV_FRACTION (0)
604 #define STM_USART_CR1_UE (13) /* USART enable */
605 #define STM_USART_CR1_M (12) /* Word length */
606 #define STM_USART_CR1_WAKE (11) /* Wakeup method */
607 #define STM_USART_CR1_PCE (10) /* Parity control enable */
608 #define STM_USART_CR1_PS (9) /* Parity selection */
609 #define STM_USART_CR1_PEIE (8) /* PE interrupt enable */
610 #define STM_USART_CR1_TXEIE (7) /* TXE interrupt enable */
611 #define STM_USART_CR1_TCIE (6) /* Transmission complete interrupt enable */
612 #define STM_USART_CR1_RXNEIE (5) /* RXNE interrupt enable */
613 #define STM_USART_CR1_IDLEIE (4) /* IDLE interrupt enable */
614 #define STM_USART_CR1_TE (3) /* Transmitter enable */
615 #define STM_USART_CR1_RE (2) /* Receiver enable */
616 #define STM_USART_CR1_RWU (1) /* Receiver wakeup */
617 #define STM_USART_CR1_SBK (0) /* Send break */
619 #define STM_USART_CR2_LINEN (14) /* LIN mode enable */
620 #define STM_USART_CR2_STOP (12) /* STOP bits */
621 #define STM_USART_CR2_STOP_MASK 3UL
622 #define STM_USART_CR2_STOP_1 0
623 #define STM_USART_CR2_STOP_0_5 1
624 #define STM_USART_CR2_STOP_2 2
625 #define STM_USART_CR2_STOP_1_5 3
627 #define STM_USART_CR2_CLKEN (11) /* Clock enable */
628 #define STM_USART_CR2_CPOL (10) /* Clock polarity */
629 #define STM_USART_CR2_CPHA (9) /* Clock phase */
630 #define STM_USART_CR2_LBCL (8) /* Last bit clock pulse */
631 #define STM_USART_CR2_LBDIE (6) /* LIN break detection interrupt enable */
632 #define STM_USART_CR2_LBDL (5) /* lin break detection length */
633 #define STM_USART_CR2_ADD (0)
634 #define STM_USART_CR2_ADD_MASK 0xfUL
636 #define STM_USART_CR3_CTSIE (10) /* CTS interrupt enable */
637 #define STM_USART_CR3_CTSE (9) /* CTS enable */
638 #define STM_USART_CR3_RTSE (8) /* RTS enable */
639 #define STM_USART_CR3_DMAT (7) /* DMA enable transmitter */
640 #define STM_USART_CR3_DMAR (6) /* DMA enable receiver */
641 #define STM_USART_CR3_SCEN (5) /* Smartcard mode enable */
642 #define STM_USART_CR3_NACK (4) /* Smartcard NACK enable */
643 #define STM_USART_CR3_HDSEL (3) /* Half-duplex selection */
644 #define STM_USART_CR3_IRLP (2) /* IrDA low-power */
645 #define STM_USART_CR3_IREN (1) /* IrDA mode enable */
646 #define STM_USART_CR3_EIE (0) /* Error interrupt enable */
650 uint8_t reserved_20[0x40 - 0x20];
662 * Need a pull-up on a separate GPIO
664 #define STM_USB_EPR_CTR_RX 15
665 #define STM_USB_EPR_CTR_RX_WRITE_INVARIANT 1
666 #define STM_USB_EPR_DTOG_RX 14
667 #define STM_USB_EPR_DTOG_RX_WRITE_INVARIANT 0
668 #define STM_USB_EPR_STAT_RX 12
669 #define STM_USB_EPR_STAT_RX_DISABLED 0
670 #define STM_USB_EPR_STAT_RX_STALL 1
671 #define STM_USB_EPR_STAT_RX_NAK 2
672 #define STM_USB_EPR_STAT_RX_VALID 3
673 #define STM_USB_EPR_STAT_RX_MASK 3UL
674 #define STM_USB_EPR_STAT_RX_WRITE_INVARIANT 0
675 #define STM_USB_EPR_SETUP 11
676 #define STM_USB_EPR_EP_TYPE 9
677 #define STM_USB_EPR_EP_TYPE_BULK 0
678 #define STM_USB_EPR_EP_TYPE_CONTROL 1
679 #define STM_USB_EPR_EP_TYPE_ISO 2
680 #define STM_USB_EPR_EP_TYPE_INTERRUPT 3
681 #define STM_USB_EPR_EP_TYPE_MASK 3UL
682 #define STM_USB_EPR_EP_KIND 8
683 #define STM_USB_EPR_EP_KIND_DBL_BUF 1 /* Bulk */
684 #define STM_USB_EPR_EP_KIND_STATUS_OUT 1 /* Control */
685 #define STM_USB_EPR_CTR_TX 7
686 #define STM_USB_CTR_TX_WRITE_INVARIANT 1
687 #define STM_USB_EPR_DTOG_TX 6
688 #define STM_USB_EPR_DTOG_TX_WRITE_INVARIANT 0
689 #define STM_USB_EPR_STAT_TX 4
690 #define STM_USB_EPR_STAT_TX_DISABLED 0
691 #define STM_USB_EPR_STAT_TX_STALL 1
692 #define STM_USB_EPR_STAT_TX_NAK 2
693 #define STM_USB_EPR_STAT_TX_VALID 3
694 #define STM_USB_EPR_STAT_TX_WRITE_INVARIANT 0
695 #define STM_USB_EPR_STAT_TX_MASK 3UL
696 #define STM_USB_EPR_EA 0
697 #define STM_USB_EPR_EA_MASK 0xfUL
699 #define STM_USB_CNTR_CTRM 15
700 #define STM_USB_CNTR_PMAOVRM 14
701 #define STM_USB_CNTR_ERRM 13
702 #define STM_USB_CNTR_WKUPM 12
703 #define STM_USB_CNTR_SUSPM 11
704 #define STM_USB_CNTR_RESETM 10
705 #define STM_USB_CNTR_SOFM 9
706 #define STM_USB_CNTR_ESOFM 8
707 #define STM_USB_CNTR_RESUME 4
708 #define STM_USB_CNTR_FSUSP 3
709 #define STM_USB_CNTR_LP_MODE 2
710 #define STM_USB_CNTR_PDWN 1
711 #define STM_USB_CNTR_FRES 0
713 #define STM_USB_ISTR_CTR 15
714 #define STM_USB_ISTR_PMAOVR 14
715 #define STM_USB_ISTR_ERR 13
716 #define STM_USB_ISTR_WKUP 12
717 #define STM_USB_ISTR_SUSP 11
718 #define STM_USB_ISTR_RESET 10
719 #define STM_USB_ISTR_SOF 9
720 #define STM_USB_ISTR_ESOF 8
721 #define STM_USB_ISTR_DIR 4
722 #define STM_USB_ISTR_EP_ID 0
723 #define STM_USB_ISTR_EP_ID_MASK 0xfUL
725 #define STM_USB_FNR_RXDP 15
726 #define STM_USB_FNR_RXDM 14
727 #define STM_USB_FNR_LCK 13
728 #define STM_USB_FNR_LSOF 11
729 #define STM_USB_FNR_LSOF_MASK 0x3UL
730 #define STM_USB_FNR_FN 0
731 #define STM_USB_FNR_FN_MASK 0x7ffUL
733 #define STM_USB_DADDR_EF 7
734 #define STM_USB_DADDR_ADD 0
735 #define STM_USB_DADDR_ADD_MASK 0x7fUL
737 extern struct stm_usb stm_usb;
740 //#define stm_usb (*((struct stm_usb *) 0x40005c00))
759 #define STM_USB_BDT_COUNT_RX_BL_SIZE 15
760 #define STM_USB_BDT_COUNT_RX_NUM_BLOCK 10
761 #define STM_USB_BDT_COUNT_RX_NUM_BLOCK_MASK 0x1fUL
762 #define STM_USB_BDT_COUNT_RX_COUNT_RX 0
763 #define STM_USB_BDT_COUNT_RX_COUNT_RX_MASK 0x3ffUL
765 #define STM_USB_BDT_SIZE 8
767 extern uint8_t stm_usb_sram[] __attribute__ ((aligned(4)));
769 //#define stm_usb_sram ((uint8_t *)0x40006000);
771 #define isr_decl(name) void stm_ ## name ## _isr(void)
780 isr_decl(usagefault);
787 isr_decl(tamper_stamp);
796 isr_decl(dma1_channel1);
797 isr_decl(dma1_channel2);
798 isr_decl(dma1_channel3);
799 isr_decl(dma1_channel4);
800 isr_decl(dma1_channel5);
801 isr_decl(dma1_channel6);
802 isr_decl(dma1_channel7);
811 isr_decl(tim1_trg_com);
827 isr_decl(usb_wakeup);
830 isr_decl(tim8_trg_com);
841 isr_decl(dma2_channel1);
842 isr_decl(dma2_channel2);
843 isr_decl(dma2_channel3);
844 isr_decl(dma2_channel4_5);
848 #define STM_ISR_WWDG_POS 0
849 #define STM_ISR_PVD_POS 1
850 #define STM_ISR_TAMPER_STAMP_POS 2
851 #define STM_ISR_RTC_WKUP_POS 3
852 #define STM_ISR_FLASH_POS 4
853 #define STM_ISR_RCC_POS 5
854 #define STM_ISR_EXTI0_POS 6
855 #define STM_ISR_EXTI1_POS 7
856 #define STM_ISR_EXTI2_POS 8
857 #define STM_ISR_EXTI3_POS 9
858 #define STM_ISR_EXTI4_POS 10
859 #define STM_ISR_DMA1_CHANNEL1_POS 11
860 #define STM_ISR_DMA1_CHANNEL2_POS 12
861 #define STM_ISR_DMA1_CHANNEL3_POS 13
862 #define STM_ISR_DMA1_CHANNEL4_POS 14
863 #define STM_ISR_DMA1_CHANNEL5_POS 15
864 #define STM_ISR_DMA1_CHANNEL6_POS 16
865 #define STM_ISR_DMA1_CHANNEL7_POS 17
866 #define STM_ISR_ADC1_2_POS 18
867 #define STM_ISR_USB_HP_POS 19
868 #define STM_ISR_USB_LP_POS 20
869 #define STM_ISR_CAN_RX1_POS 21
870 #define STM_ISR_CAN_SCE_POS 22
871 #define STM_ISR_EXTI9_5_POS 23
872 #define STM_ISR_TIM1_BRK_POS 24
873 #define STM_ISR_TIM1_UP_POS 25
874 #define STM_ISR_TIM1_TRG_COM_POS 26
875 #define STM_ISR_TIM1_CC_POS 27
876 #define STM_ISR_TIM2_POS 28
877 #define STM_ISR_TIM3_POS 29
878 #define STM_ISR_TIM4_POS 30
879 #define STM_ISR_I2C1_EV_POS 31
880 #define STM_ISR_I2C1_ER_POS 32
881 #define STM_ISR_I2C2_EV_POS 33
882 #define STM_ISR_I2C2_ER_POS 34
883 #define STM_ISR_SPI1_POS 35
884 #define STM_ISR_SPI2_POS 36
885 #define STM_ISR_USART1_POS 37
886 #define STM_ISR_USART2_POS 38
887 #define STM_ISR_USART3_POS 39
888 #define STM_ISR_EXTI15_10_POS 40
889 #define STM_ISR_RTC_ALARM_POS 41
890 #define STM_ISR_USB_WAKEUP_POS 42
891 #define STM_ISR_TIM8_BRK_POS 43
892 #define STM_ISR_TIM8_UP_POS 44
893 #define STM_ISR_TIM8_TRG_COM_POS 45
894 #define STM_ISR_TIM8_CC_POS 46
895 #define STM_ISR_ADC3_POS 47
896 #define STM_ISR_FSMC_POS 48
897 #define STM_ISR_SDIO_POS 49
898 #define STM_ISR_TIM5_POS 50
899 #define STM_ISR_SPI3_POS 51
900 #define STM_ISR_UART4_POS 52
901 #define STM_ISR_UART5_POS 53
902 #define STM_ISR_TIM6_POS 54
903 #define STM_ISR_TIM7_POS 55
904 #define STM_ISR_DMA2_CHANNEL1_POS 56
905 #define STM_ISR_DMA2_CHANNEL2_POS 57
906 #define STM_ISR_DMA2_CHANNEL3_POS 58
907 #define STM_ISR_DMA3_CHANNEL4_5_POS 59