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   1 /*
   2  * Copyright © 2023 Keith Packard <keithp@keithp.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation, either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful, but
  10  * WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  12  * General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along
  15  * with this program; if not, write to the Free Software Foundation, Inc.,
  16  * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  17  */
  18
  19 #ifndef _STM32F1_H_
  20 #define _STM32F1_H_
  21
  22 #include <stdint.h>
  23
  24 typedef volatile uint32_t       vuint32_t;
  25 typedef volatile uint16_t       vuint16_t;
  26 typedef volatile void *         vvoid_t;
  27
  28 struct stm_rcc {
  29         vuint32_t       cr;
  30         vuint32_t       cfgr;
  31         vuint32_t       cir;
  32         vuint32_t       apb2rstr;
  33
  34         vuint32_t       apb1rstr;
  35         vuint32_t       ahbenr;
  36         vuint32_t       apb2enr;
  37         vuint32_t       apb1enr;
  38
  39         vuint32_t       bdcr;
  40         vuint32_t       csr;
  41         vuint32_t       ahbstr;
  42         vuint32_t       cfgr2;
  43 };
  44
  45 extern struct stm_rcc stm_rcc;
  46
  47 //#define stm_rcc    (*((struct stm_rcc *) 0x40021000))
  48
  49 #define STM_RCC_CR_RTCPRE       (29)
  50 #define  STM_RCC_CR_RTCPRE_HSE_DIV_2    0
  51 #define  STM_RCC_CR_RTCPRE_HSE_DIV_4    1
  52 #define  STM_RCC_CR_RTCPRE_HSE_DIV_8    2
  53 #define  STM_RCC_CR_RTCPRE_HSE_DIV_16   3
  54 #define  STM_RCC_CR_RTCPRE_HSE_MASK     3UL
  55
  56 #define STM_RCC_CR_PLL3RDY      (29)
  57 #define STM_RCC_CR_PLL3ON       (28)
  58 #define STM_RCC_CR_PLL2RDY      (27)
  59 #define STM_RCC_CR_PLL2ON       (26)
  60 #define STM_RCC_CR_PLLRDY       (25)
  61 #define STM_RCC_CR_PLLON        (24)
  62 #define STM_RCC_CR_CSSON        (19)
  63 #define STM_RCC_CR_HSEBYP       (18)
  64 #define STM_RCC_CR_HSERDY       (17)
  65 #define STM_RCC_CR_HSEON        (16)
  66 #define STM_RCC_CR_HSICAL       (8)
  67 #define STM_RCC_CR_HSITRIM      (3)
  68 #define STM_RCC_CR_HSIRDY       (1)
  69 #define STM_RCC_CR_HSION        (0)
  70
  71 #define STM_RCC_CFGR_MCO        (24)
  72 #define  STM_RCC_CFGR_MCO_DISABLE       0
  73 #define  STM_RCC_CFGR_MCO_SYSCLK        4
  74 #define  STM_RCC_CFGR_MCO_HSI   5
  75 #define  STM_RCC_CFGR_MCO_HSE   6
  76 #define  STM_RCC_CFGR_MCO_PLL_2 7
  77 #define  STM_RCC_CFGR_MCO_MASK  7UL
  78
  79 #define STM_RCC_CFGR_USBPRE     (22)
  80 #define  STM_RCC_CFGR_USBPRE_1_5        0
  81 #define  STM_RCC_CFGR_USBPRE_1          1
  82
  83 #define STM_RCC_CFGR_PLLMUL     (18)
  84 #define  STM_RCC_CFGR_PLLMUL_2          0
  85 #define  STM_RCC_CFGR_PLLMUL_3          1
  86 #define  STM_RCC_CFGR_PLLMUL_4          2
  87 #define  STM_RCC_CFGR_PLLMUL_5          3
  88 #define  STM_RCC_CFGR_PLLMUL_6          4
  89 #define  STM_RCC_CFGR_PLLMUL_7          5
  90 #define  STM_RCC_CFGR_PLLMUL_8          6
  91 #define  STM_RCC_CFGR_PLLMUL_9          7
  92 #define  STM_RCC_CFGR_PLLMUL_10         8
  93 #define  STM_RCC_CFGR_PLLMUL_11         9
  94 #define  STM_RCC_CFGR_PLLMUL_12         10
  95 #define  STM_RCC_CFGR_PLLMUL_13         11
  96 #define  STM_RCC_CFGR_PLLMUL_14         12
  97 #define  STM_RCC_CFGR_PLLMUL_15         13
  98 #define  STM_RCC_CFGR_PLLMUL_16         14
  99 #define  STM_RCC_CFGR_PLLMUL_MASK       0xfUL
 100
 101 #define STM_RCC_CFGR_PLLXTPRE   (17)
 102 #define  STM_RCC_CFGR_PLLXTPRE_1        0
 103 #define  STM_RCC_CFGR_PLLXTPRE_2        1
 104 #define  STM_RCC_CFGR_PLLXTPRE_MASK     1UL
 105
 106 #define STM_RCC_CFGR_PLLSRC     (16)
 107 #define  STM_RCC_CFGR_PLLSRC_HSI_2      0
 108 #define  STM_RCC_CFGR_PLLSRC_HSE        1
 109
 110 #define STM_RCC_CFGR_ADCPRE     (14)
 111 #define  STM_RCC_CFGR_ADCPRE_2          0
 112 #define  STM_RCC_CFGR_ADCPRE_4          1
 113 #define  STM_RCC_CFGR_ADCPRE_6          2
 114 #define  STM_RCC_CFGR_ADCPRE_8          3
 115
 116 #define STM_RCC_CFGR_PPRE2      (11)
 117 #define  STM_RCC_CFGR_PPRE2_DIV_1       0
 118 #define  STM_RCC_CFGR_PPRE2_DIV_2       4
 119 #define  STM_RCC_CFGR_PPRE2_DIV_4       5
 120 #define  STM_RCC_CFGR_PPRE2_DIV_8       6
 121 #define  STM_RCC_CFGR_PPRE2_DIV_16      7
 122 #define  STM_RCC_CFGR_PPRE2_MASK        7UL
 123
 124 #define STM_RCC_CFGR_PPRE1      (8)
 125 #define  STM_RCC_CFGR_PPRE1_DIV_1       0
 126 #define  STM_RCC_CFGR_PPRE1_DIV_2       4
 127 #define  STM_RCC_CFGR_PPRE1_DIV_4       5
 128 #define  STM_RCC_CFGR_PPRE1_DIV_8       6
 129 #define  STM_RCC_CFGR_PPRE1_DIV_16      7
 130 #define  STM_RCC_CFGR_PPRE1_MASK        7UL
 131
 132 #define STM_RCC_CFGR_HPRE       (4)
 133 #define  STM_RCC_CFGR_HPRE_DIV_1        0
 134 #define  STM_RCC_CFGR_HPRE_DIV_2        8
 135 #define  STM_RCC_CFGR_HPRE_DIV_4        9
 136 #define  STM_RCC_CFGR_HPRE_DIV_8        0xa
 137 #define  STM_RCC_CFGR_HPRE_DIV_16       0xb
 138 #define  STM_RCC_CFGR_HPRE_DIV_64       0xc
 139 #define  STM_RCC_CFGR_HPRE_DIV_128      0xd
 140 #define  STM_RCC_CFGR_HPRE_DIV_256      0xe
 141 #define  STM_RCC_CFGR_HPRE_DIV_512      0xf
 142 #define  STM_RCC_CFGR_HPRE_MASK         0xfUL
 143
 144 #define STM_RCC_CFGR_SWS        (2)
 145 #define  STM_RCC_CFGR_SWS_HSI           0
 146 #define  STM_RCC_CFGR_SWS_HSE           1
 147 #define  STM_RCC_CFGR_SWS_PLL           2
 148 #define  STM_RCC_CFGR_SWS_MASK          3UL
 149
 150 #define STM_RCC_CFGR_SW         (0)
 151 #define  STM_RCC_CFGR_SW_HSI            0
 152 #define  STM_RCC_CFGR_SW_HSE            1
 153 #define  STM_RCC_CFGR_SW_PLL            2
 154 #define  STM_RCC_CFGR_SW_MASK           3UL
 155
 156 #define STM_RCC_AHBENR_CRCEN    6
 157 #define STM_RCC_AHBENR_FLITFEN  4
 158 #define STM_RCC_AHBENR_SRAMEN   2
 159 #define STM_RCC_AHBENR_DMA2EN   1
 160 #define STM_RCC_AHBENR_DMA1EN   0
 161
 162
 163 #define STM_RCC_APB2ENR_USART1EN        14
 164 #define STM_RCC_APB2ENR_SPI1EN          12
 165 #define STM_RCC_APB2ENR_TIM1EN          11
 166 #define STM_RCC_APB2ENR_ADC2EN          10
 167 #define STM_RCC_APB2ENR_ADC1EN          9
 168 #define STM_RCC_APB2ENR_IOPEEN          6
 169 #define STM_RCC_APB2ENR_IOPDEN          5
 170 #define STM_RCC_APB2ENR_IOPCEN          4
 171 #define STM_RCC_APB2ENR_IOPBEN          3
 172 #define STM_RCC_APB2ENR_IOPAEN          2
 173 #define STM_RCC_APB2ENR_AFIOEN          0
 174
 175 #define STM_RCC_APB1ENR_DACEN           29
 176 #define STM_RCC_APB1ENR_PWREN           28
 177 #define STM_RCC_APB1ENR_BKPEN           27
 178 #define STM_RCC_APB1ENR_CANEN           26
 179 #define STM_RCC_APB1ENR_USBEN           23
 180 #define STM_RCC_APB1ENR_I2C2EN          22
 181 #define STM_RCC_APB1ENR_I2C1EN          21
 182 #define STM_RCC_APB1ENR_UART5EN         20
 183 #define STM_RCC_APB1ENR_UART4EN         19
 184 #define STM_RCC_APB1ENR_USART3EN        18
 185 #define STM_RCC_APB1ENR_USART2EN        17
 186 #define STM_RCC_APB1ENR_SPI3EN          15
 187 #define STM_RCC_APB1ENR_SPI2EN          14
 188 #define STM_RCC_APB1ENR_WWDGEN          11
 189 #define STM_RCC_APB1ENR_TIM14EN         8
 190 #define STM_RCC_APB1ENR_TIM13EN         7
 191 #define STM_RCC_APB1ENR_TIM12EN         6
 192 #define STM_RCC_APB1ENR_TIM7EN          5
 193 #define STM_RCC_APB1ENR_TIM6EN          4
 194 #define STM_RCC_APB1ENR_TIM5EN          3
 195 #define STM_RCC_APB1ENR_TIM4EN          2
 196 #define STM_RCC_APB1ENR_TIM3EN          1
 197 #define STM_RCC_APB1ENR_TIM2EN          0
 198
 199 #define STM_RCC_CSR_LPWRRSTF            (31)
 200 #define STM_RCC_CSR_WWDGRSTF            (30)
 201 #define STM_RCC_CSR_IWDGRSTF            (29)
 202 #define STM_RCC_CSR_SFTRSTF             (28)
 203 #define STM_RCC_CSR_PORRSTF             (27)
 204 #define STM_RCC_CSR_PINRSTF             (26)
 205 #define STM_RCC_CSR_RMVF                (24)
 206 #define STM_RCC_CSR_LSIRDY              (1)
 207 #define STM_RCC_CSR_LSION               (0)
 208
 209 struct stm_systick {
 210         vuint32_t       ctrl;
 211         vuint32_t       load;
 212         vuint32_t       val;
 213         vuint32_t       calib;
 214 };
 215
 216 extern struct stm_systick stm_systick;
 217
 218 //#define stm_systick   (*((struct stm_systick *) 0xe000e010))
 219
 220 #define STM_SYSTICK_CTRL_ENABLE         0
 221 #define STM_SYSTICK_CTRL_TICKINT        1
 222 #define STM_SYSTICK_CTRL_CLKSOURCE      2
 223 #define  STM_SYSTICK_CTRL_CLKSOURCE_HCLK_8              0
 224 #define  STM_SYSTICK_CTRL_CLKSOURCE_HCLK                1
 225 #define STM_SYSTICK_CTRL_COUNTFLAG      16
 226
 227 /* The NVIC starts at 0xe000e100, so add that to the offsets to find the absolute address */
 228
 229 struct stm_nvic {
 230         vuint32_t       iser[3];        /* 0x000 0xe000e100 Set Enable Register */
 231
 232         uint8_t         _unused00c[0x080 - 0x00c];
 233
 234         vuint32_t       icer[3];        /* 0x080 0xe000e180 Clear Enable Register */
 235
 236         uint8_t         _unused08c[0x100 - 0x08c];
 237
 238         vuint32_t       ispr[3];        /* 0x100 0xe000e200 Set Pending Register */
 239
 240         uint8_t         _unused10c[0x180 - 0x10c];
 241
 242         vuint32_t       icpr[3];        /* 0x180 0xe000e280 Clear Pending Register */
 243
 244         uint8_t         _unused18c[0x200 - 0x18c];
 245
 246         vuint32_t       iabr[3];        /* 0x200 0xe000e300 Active Bit Register */
 247
 248         uint8_t         _unused20c[0x300 - 0x20c];
 249
 250         vuint32_t       ipr[31];        /* 0x300 0xe000e400 Priority Register */
 251
 252         uint8_t         _unused37c[0xe00 - 0x37c];      /* covers SCB */
 253
 254         vuint32_t       stir;           /* 0xe00 0xe000ee00 Software Trigger Interrupt Register */
 255 };
 256
 257 extern struct stm_nvic stm_nvic;
 258
 259 //#define stm_nvic (*((struct stm_nvic *) 0xe000e100))
 260
 261 #define IRQ_REG(irq)    ((irq) >> 5)
 262 #define IRQ_BIT(irq)    ((irq) & 0x1f)
 263 #define IRQ_MASK(irq)   (1 << IRQ_BIT(irq))
 264 #define IRQ_BOOL(v,irq) (((v) >> IRQ_BIT(irq)) & 1)
 265
 266 static inline void
 267 stm_nvic_set_enable(int irq) {
 268         stm_nvic.iser[IRQ_REG(irq)] = IRQ_MASK(irq);
 269 }
 270
 271 static inline void
 272 stm_nvic_clear_enable(int irq) {
 273         stm_nvic.icer[IRQ_REG(irq)] = IRQ_MASK(irq);
 274 }
 275
 276 static inline int
 277 stm_nvic_enabled(int irq) {
 278         return IRQ_BOOL(stm_nvic.iser[IRQ_REG(irq)], irq);
 279 }
 280
 281 static inline void
 282 stm_nvic_set_pending(int irq) {
 283         stm_nvic.ispr[IRQ_REG(irq)] = IRQ_MASK(irq);
 284 }
 285
 286 static inline void
 287 stm_nvic_clear_pending(int irq) {
 288         stm_nvic.icpr[IRQ_REG(irq)] = IRQ_MASK(irq);
 289 }
 290
 291 static inline int
 292 stm_nvic_pending(int irq) {
 293         return IRQ_BOOL(stm_nvic.ispr[IRQ_REG(irq)], irq);
 294 }
 295
 296 static inline int
 297 stm_nvic_active(int irq) {
 298         return IRQ_BOOL(stm_nvic.iabr[IRQ_REG(irq)], irq);
 299 }
 300
 301 #define IRQ_PRIO_REG(irq)       ((irq) >> 2)
 302 #define IRQ_PRIO_BIT(irq)       (((irq) & 3) << 3)
 303 #define IRQ_PRIO_MASK(irq)      (0xff << IRQ_PRIO_BIT(irq))
 304
 305 static inline void
 306 stm_nvic_set_priority(int irq, uint8_t prio) {
 307         int             n = IRQ_PRIO_REG(irq);
 308         uint32_t        v;
 309
 310         v = stm_nvic.ipr[n];
 311         v &= (uint32_t) ~IRQ_PRIO_MASK(irq);
 312         v |= (prio) << IRQ_PRIO_BIT(irq);
 313         stm_nvic.ipr[n] = v;
 314 }
 315
 316 static inline uint8_t
 317 stm_nvic_get_priority(int irq) {
 318         return (stm_nvic.ipr[IRQ_PRIO_REG(irq)] >> IRQ_PRIO_BIT(irq)) & IRQ_PRIO_MASK(0);
 319 }
 320
 321 struct stm_scb {
 322         vuint32_t       cpuid;
 323         vuint32_t       icsr;
 324         vuint32_t       vtor;
 325         vuint32_t       aircr;
 326
 327         vuint32_t       scr;
 328         vuint32_t       ccr;
 329         vuint32_t       shpr1;
 330         vuint32_t       shpr2;
 331
 332         vuint32_t       shpr3;
 333         vuint32_t       shcrs;
 334         vuint32_t       cfsr;
 335         vuint32_t       hfsr;
 336
 337         uint32_t        unused_30;
 338         vuint32_t       mmar;
 339         vuint32_t       bfar;
 340 };
 341
 342 extern struct stm_scb stm_scb;
 343
 344 #define STM_SCB_AIRCR_VECTKEY           16
 345 #define  STM_SCB_AIRCR_VECTKEY_KEY              0x05fa
 346 #define STM_SCB_AIRCR_PRIGROUP          8
 347 #define STM_SCB_AIRCR_SYSRESETREQ       2
 348 #define STM_SCB_AIRCR_VECTCLRACTIVE     1
 349 #define STM_SCB_AIRCR_VECTRESET         0
 350
 351 struct stm_dbgmcu {
 352         uint32_t        idcode;
 353 };
 354
 355 extern struct stm_dbgmcu        stm_dbgmcu;
 356
 357 static inline uint16_t
 358 stm_dev_id(void) {
 359         return stm_dbgmcu.idcode & 0xfff;
 360 }
 361
 362 struct stm_flash {
 363         vuint32_t       acr;
 364         vuint32_t       keyr;
 365         vuint32_t       optkeyr;
 366         vuint32_t       sr;
 367
 368         vuint32_t       cr;
 369         vuint32_t       ar;
 370         uint32_t        _unused018;
 371         vuint32_t       obr;
 372
 373         vuint32_t       wrpr;
 374 };
 375
 376 extern struct stm_flash stm_flash;
 377
 378 //#define stm_flash (*((struct stm_flash *) 0x40022000))
 379
 380 #define STM_FLASH_ACR_PRFTBS    5
 381 #define STM_FLASH_ACR_PRFTBE    4
 382 #define STM_FLASH_ACR_HLFCYA    3
 383 #define STM_FLASH_ACR_LATENCY   0
 384 #define  STM_FLASH_ACR_LATENCY_0        0
 385 #define  STM_FLASH_ACR_LATENCY_1        1
 386 #define  STM_FLASH_ACR_LATENCY_2        2
 387
 388 #define STM_FLASH_SR_EOP        5
 389 #define STM_FLASH_SR_WRPRTERR   4
 390 #define STM_FLASH_SR_PGERR      2
 391 #define STM_FLASH_SR_BSY        0
 392
 393 #define STM_FLASH_CR_EOPIE      12
 394 #define STM_FLASH_CR_ERRIE      10
 395 #define STM_FLASH_CR_OPTWRE     9
 396 #define STM_FLASH_CR_LOCK       7
 397 #define STM_FLASH_CR_STRT       6
 398 #define STM_FLASH_CR_OPTER      5
 399 #define STM_FLASH_CR_OPTPG      4
 400 #define STM_FLASH_CR_MER        2
 401 #define STM_FLASH_CR_PER        1
 402 #define STM_FLASH_CR_PG         0
 403
 404 #define STM_FLASH_RDPRT_KEY     0x00A5
 405 #define STM_FLASH_KEYR_KEY1     0x45670123
 406 #define STM_FLASH_KEYR_KEY2     0xCDEF89AB
 407
 408
 409 struct stm_flash_data {
 410         vuint16_t       f_size;
 411         vuint16_t       unused02;
 412         vuint32_t       unused04;
 413         vuint32_t       device_id[3];
 414 };
 415
 416 extern struct stm_flash_data    stm_flash_data;
 417
 418 static inline uint32_t stm_flash_size(void) { return (uint32_t) stm_flash_data.f_size * 1024; }
 419
 420 //#define stm_flash_data        (*((struct stm_flash_data *) 0x1ffff7e0))
 421
 422 struct stm_gpio {
 423         vuint32_t       cr[2];
 424         vuint32_t       idr;
 425         vuint32_t       odr;
 426
 427         vuint32_t       bsrr;
 428         vuint32_t       brr;
 429         vuint32_t       lckr;
 430 };
 431
 432 #define STM_GPIO_CR(y)          ((uint8_t) (y) >> 3)
 433 #define STM_GPIO_CR_CNF(y)      ((((uint8_t) (y) & 7) << 2) + 2)
 434 #define  STM_GPIO_CR_CNF_INPUT_ANALOG           0
 435 #define  STM_GPIO_CR_CNF_INPUT_FLOATING         1
 436 #define  STM_GPIO_CR_CNF_INPUT_PULL             2
 437 #define  STM_GPIO_CR_CNF_OUTPUT_PUSH_PULL       0
 438 #define  STM_GPIO_CR_CNF_OUTPUT_OPEN_DRAIN      1
 439 #define  STM_GPIO_CR_CNF_OUTPUT_AF_PUSH_PULL    2
 440 #define  STM_GPIO_CR_CNF_OUTPUT_AF_OPEN_DRAIN   3
 441 #define  STM_GPIO_CR_CNF_MASK                   3U
 442 #define STM_GPIO_CR_MODE(y)     ((((y) & 7) << 2))
 443 #define  STM_GPIO_CR_MODE_INPUT                 0
 444 #define  STM_GPIO_CR_MODE_OUTPUT_10MHZ          1
 445 #define  STM_GPIO_CR_MODE_OUTPUT_2MHZ           2
 446 #define  STM_GPIO_CR_MODE_OUTPUT_50MHZ          3
 447 #define  STM_GPIO_CR_MODE_MASK                  3U
 448
 449 static inline void
 450 stm_gpio_conf(struct stm_gpio *gpio, int pin, uint8_t mode, uint8_t cnf)
 451 {
 452         uint8_t         cr = STM_GPIO_CR(pin);
 453         uint32_t        v = gpio->cr[cr];
 454
 455         v &= ~((STM_GPIO_CR_CNF_MASK << STM_GPIO_CR_CNF(pin)) |
 456                (STM_GPIO_CR_MODE_MASK << STM_GPIO_CR_MODE(pin)));
 457         v |= (mode << STM_GPIO_CR_MODE(pin)) | (cnf << STM_GPIO_CR_CNF(pin));
 458         gpio->cr[cr] = v;
 459 }
 460
 461 static inline void
 462 stm_gpio_set(struct stm_gpio *gpio, int pin, uint8_t value) {
 463         /* Use the bit set/reset register to do this atomically */
 464         gpio->bsrr = ((uint32_t) (value ^ 1) << (pin + 16)) | ((uint32_t) value << pin);
 465 }
 466
 467 static inline void
 468 stm_gpio_set_mask(struct stm_gpio *gpio, uint16_t bits, uint16_t mask) {
 469         /* Use the bit set/reset register to do this atomically */
 470         gpio->bsrr = ((uint32_t) (~bits & mask) << 16) | ((uint32_t) (bits & mask));
 471 }
 472
 473 static inline void
 474 stm_gpio_set_bits(struct stm_gpio *gpio, uint16_t bits) {
 475         gpio->bsrr = bits;
 476 }
 477
 478 static inline void
 479 stm_gpio_clr_bits(struct stm_gpio *gpio, uint16_t bits) {
 480         gpio->bsrr = ((uint32_t) bits) << 16;
 481 }
 482
 483 static inline uint8_t
 484 stm_gpio_get(struct stm_gpio *gpio, int pin) {
 485         return (gpio->idr >> pin) & 1;
 486 }
 487
 488 static inline uint16_t
 489 stm_gpio_get_all(struct stm_gpio *gpio) {
 490         return (uint16_t) gpio->idr;
 491 }
 492
 493 extern struct stm_gpio stm_gpioa;
 494 extern struct stm_gpio stm_gpiob;
 495 extern struct stm_gpio stm_gpioc;
 496 extern struct stm_gpio stm_gpiod;
 497 extern struct stm_gpio stm_gpioe;
 498
 499 #define stm_gpioe  (*((struct stm_gpio *) 0x40011800))
 500 #define stm_gpiod  (*((struct stm_gpio *) 0x40011400))
 501 #define stm_gpioc  (*((struct stm_gpio *) 0x40011000))
 502 #define stm_gpiob  (*((struct stm_gpio *) 0x40010c00))
 503 #define stm_gpioa  (*((struct stm_gpio *) 0x40010800))
 504
 505 struct stm_afio {
 506         vuint32_t       evcr;
 507         vuint32_t       mapr;
 508         vuint32_t       exticr[4];
 509         vuint32_t       mapr2;
 510 };
 511
 512 extern struct stm_afio stm_afio;
 513
 514 #define stm_afio        (*((struct stm_afio *) 0x40010000))
 515
 516 #define STM_AFIO_MAPR_ADC2_ETRGREG_REMAP        20
 517 #define STM_AFIO_MAPR_ADC2_ETRGINJ_REMAP        19
 518 #define STM_AFIO_MAPR_ADC1_ETRGREG_REMAP        18
 519 #define STM_AFIO_MAPR_ADC1_ETRGINJ_REMAP        17
 520 #define STM_AFIO_MAPR_TIM5CH4_IREMAP            16
 521 #define STM_AFIO_MAPR_PD01_REMAP                15
 522 #define STM_AFIO_MAPR_CAN_REMAP                 13
 523 #define  STM_AFIO_MAPR_CAN_REMAP_PA11_PA12              0
 524 #define  STM_AFIO_MAPR_CAN_REMAP_PB8_PB9                2
 525 #define  STM_AFIO_MAPR_CAN_REMAP_PD0_PD1                3
 526 #define  STM_AFIO_MAPR_CAN_REMAP_MASK                   3
 527 #define STM_AFIO_MAPR_TIM4_REMAP                12
 528 #define STM_AFIO_MAPR_TIM3_REMAP                10
 529 #define  STM_AFIO_MAPR_TIM3_REMAP_PA6_PA7_PB0_PB1       0
 530 #define  STM_AFIO_MAPR_TIM3_REMAP_PB4_PB5_PB0_PB1       2
 531 #define  STM_AFIO_MAPR_TIM3_REMAP_PC6_PC7_PC8_PC9       3
 532 #define  STM_AFIO_MAPR_TIM3_REMAP_MASK                  3
 533 #define STM_AFIO_MAPR_TIM2_REMAP                8
 534 #define  STM_AFIO_MAPR_TIM2_REMAP_PA0_PA1_PA2_PA3       0
 535 #define  STM_AFIO_MAPR_TIM2_REMAP_PA15_PB3_PA2_PA3      1
 536 #define  STM_AFIO_MAPR_TIM2_REMAP_PA0_PA1_PB10_PB11     2
 537 #define  STM_AFIO_MAPR_TIM2_REMAP_PA15_PB3_PB10_PB11    3
 538 #define  STM_AFIO_MAPR_TIM2_REMAP_MASK                  3
 539 #define STM_AFIO_MAPR_TIM1_REMAP                6
 540 #define  STM_AFIO_MAPR_TIM1_REMAP_PA12_PA8_PA9_PA10_PA11_PB12_PB13_PB14_PB15    0
 541 #define  STM_AFIO_MAPR_TIM1_REMAP_PA12_PA8_PA9_PA10_PA11_PA6_PA7_PB0_PB1        1
 542 #define  STM_AFIO_MAPR_TIM1_REMAP_PE7_PE9_PE11_PE13_PE14_PE15_PE8_PE10_PE12     3
 543 #define  STM_AFIO_MAPR_TIM1_REMAP_MASK                                          3
 544 #define STM_AFIO_MAPR_USART3_REMAP              4
 545 #define  STM_AFIO_MAPR_USART3_REMAP_PB10_PB11_PB12_PB13_PB14    0
 546 #define  STM_AFIO_MAPR_USART3_REMAP_PC10_PC11_PC12_PB13_PB14    1
 547 #define  STM_AFIO_MAPR_USART3_REMAP_PD8_PD9_PD10_PD11_PD12      3
 548 #define  STM_AFIO_MAPR_USART3_REMAP_MASK                        3
 549 #define STM_AFIO_MAPR_USART2_REMAP              3
 550 #define  STM_AFIO_MAPR_USART2_REMAP_PA0_PA1_PA2_PA3_PA4 0
 551 #define  STM_AFIO_MAPR_USART2_REMAP_PD3_PD4_PD5_PD6_PD7 1
 552 #define  STM_AFIO_MAPR_USART2_REMAP_MASK                1
 553 #define STM_AFIO_MAPR_USART1_REMAP              2
 554 #define  STM_AFIO_MAPR_USART1_REMAP_PA9_PA10            0
 555 #define  STM_AFIO_MAPR_USART1_REMAP_PB6_PB7             1
 556 #define  STM_AFIO_MAPR_USART1_REMAP_MASK                1
 557 #define STM_AFIO_MAPR_I2C1_REMAP                1
 558 #define  STM_AFIO_MAPR_I2C1_REMAP_PB6_PB7               0
 559 #define  STM_AFIO_MAPR_I2C1_REMAP_PB8_PB9               1
 560 #define  STM_AFIO_MAPR_I2C1_REMAP_MASK                  1
 561 #define STM_AFIO_MAPR_SPI1_REMAP                0
 562 #define  STM_AFIO_MAPR_SPI1_REMAP_PA4_PA5_PA6_PA7       0
 563 #define  STM_AFIO_MAPR_SPI1_REMAP_PA15_PB3_PB4_PB5      1
 564 #define  STM_AFIO_MAPR_SPI1_REMAP_MASK                  1
 565
 566 #define STM_AFIO_EXTICR_PA              0
 567 #define STM_AFIO_EXTICR_PB              1
 568 #define STM_AFIO_EXTICR_PC              2
 569 #define STM_AFIO_EXTICR_PD              3
 570 #define STM_AFIO_EXTICR_PE              4
 571 #define STM_AFIO_EXTICR_PF              5
 572 #define STM_AFIO_EXTICR_PG              6
 573
 574 static inline void
 575 stm_set_afio_mapr(uint8_t bit, uint32_t val, uint32_t mask) {
 576         uint32_t        mapr = stm_afio.mapr;
 577
 578         mapr &= ~(mask << bit);
 579         mapr |= (val << bit);
 580         stm_afio.mapr = mapr;
 581 }
 582
 583 struct stm_usart {
 584         vuint32_t       sr;     /* status register */
 585         vuint32_t       dr;     /* data register */
 586         vuint32_t       brr;    /* baud rate register */
 587         vuint32_t       cr1;    /* control register 1 */
 588
 589         vuint32_t       cr2;    /* control register 2 */
 590         vuint32_t       cr3;    /* control register 3 */
 591         vuint32_t       gtpr;   /* guard time and prescaler */
 592 };
 593
 594 extern struct stm_usart stm_usart1;
 595 extern struct stm_usart stm_usart2;
 596 extern struct stm_usart stm_usart3;
 597
 598 //#define stm_usart1    (*((struct stm_usart *) 0x40013800))
 599 //#define stm_usart2    (*((struct stm_usart *) 0x40004800))
 600 //#define stm_usart3    (*((struct stm_usart *) 0x40004400))
 601
 602 #define STM_USART_SR_CTS        (9)     /* CTS flag */
 603 #define STM_USART_SR_LBD        (8)     /* LIN break detection flag */
 604 #define STM_USART_SR_TXE        (7)     /* Transmit data register empty */
 605 #define STM_USART_SR_TC         (6)     /* Transmission complete */
 606 #define STM_USART_SR_RXNE       (5)     /* Read data register not empty */
 607 #define STM_USART_SR_IDLE       (4)     /* IDLE line detected */
 608 #define STM_USART_SR_ORE        (3)     /* Overrun error */
 609 #define STM_USART_SR_NE         (2)     /* Noise detected flag */
 610 #define STM_USART_SR_FE         (1)     /* Framing error */
 611 #define STM_USART_SR_PE         (0)     /* Parity error */
 612
 613 #define STM_USART_BRR_DIV_MANTISSA      (4)
 614 #define STM_USART_BRR_DIV_FRACTION      (0)
 615
 616 #define STM_USART_CR1_UE        (13)    /* USART enable */
 617 #define STM_USART_CR1_M         (12)    /* Word length */
 618 #define STM_USART_CR1_WAKE      (11)    /* Wakeup method */
 619 #define STM_USART_CR1_PCE       (10)    /* Parity control enable */
 620 #define STM_USART_CR1_PS        (9)     /* Parity selection */
 621 #define STM_USART_CR1_PEIE      (8)     /* PE interrupt enable */
 622 #define STM_USART_CR1_TXEIE     (7)     /* TXE interrupt enable */
 623 #define STM_USART_CR1_TCIE      (6)     /* Transmission complete interrupt enable */
 624 #define STM_USART_CR1_RXNEIE    (5)     /* RXNE interrupt enable */
 625 #define STM_USART_CR1_IDLEIE    (4)     /* IDLE interrupt enable */
 626 #define STM_USART_CR1_TE        (3)     /* Transmitter enable */
 627 #define STM_USART_CR1_RE        (2)     /* Receiver enable */
 628 #define STM_USART_CR1_RWU       (1)     /* Receiver wakeup */
 629 #define STM_USART_CR1_SBK       (0)     /* Send break */
 630
 631 #define STM_USART_CR2_LINEN     (14)    /* LIN mode enable */
 632 #define STM_USART_CR2_STOP      (12)    /* STOP bits */
 633 #define STM_USART_CR2_STOP_MASK 3UL
 634 #define STM_USART_CR2_STOP_1    0
 635 #define STM_USART_CR2_STOP_0_5  1
 636 #define STM_USART_CR2_STOP_2    2
 637 #define STM_USART_CR2_STOP_1_5  3
 638
 639 #define STM_USART_CR2_CLKEN     (11)    /* Clock enable */
 640 #define STM_USART_CR2_CPOL      (10)    /* Clock polarity */
 641 #define STM_USART_CR2_CPHA      (9)     /* Clock phase */
 642 #define STM_USART_CR2_LBCL      (8)     /* Last bit clock pulse */
 643 #define STM_USART_CR2_LBDIE     (6)     /* LIN break detection interrupt enable */
 644 #define STM_USART_CR2_LBDL      (5)     /* lin break detection length */
 645 #define STM_USART_CR2_ADD       (0)
 646 #define STM_USART_CR2_ADD_MASK  0xfUL
 647
 648 #define STM_USART_CR3_CTSIE     (10)    /* CTS interrupt enable */
 649 #define STM_USART_CR3_CTSE      (9)     /* CTS enable */
 650 #define STM_USART_CR3_RTSE      (8)     /* RTS enable */
 651 #define STM_USART_CR3_DMAT      (7)     /* DMA enable transmitter */
 652 #define STM_USART_CR3_DMAR      (6)     /* DMA enable receiver */
 653 #define STM_USART_CR3_SCEN      (5)     /* Smartcard mode enable */
 654 #define STM_USART_CR3_NACK      (4)     /* Smartcard NACK enable */
 655 #define STM_USART_CR3_HDSEL     (3)     /* Half-duplex selection */
 656 #define STM_USART_CR3_IRLP      (2)     /* IrDA low-power */
 657 #define STM_USART_CR3_IREN      (1)     /* IrDA mode enable */
 658 #define STM_USART_CR3_EIE       (0)     /* Error interrupt enable */
 659
 660 struct stm_usb {
 661         vuint32_t       epr[8];
 662         uint8_t         reserved_20[0x40 - 0x20];
 663         vuint32_t       cntr;
 664         vuint32_t       istr;
 665         vuint32_t       fnr;
 666         vuint32_t       daddr;
 667         vuint32_t       btable;
 668 };
 669
 670 /*
 671  * USB DM: PA11
 672  * USB DP: PA12
 673  *
 674  * Need a pull-up on a separate GPIO
 675  */
 676 #define STM_USB_EPR_CTR_RX      15
 677 #define  STM_USB_EPR_CTR_RX_WRITE_INVARIANT             1
 678 #define STM_USB_EPR_DTOG_RX     14
 679 #define STM_USB_EPR_DTOG_RX_WRITE_INVARIANT             0
 680 #define STM_USB_EPR_STAT_RX     12
 681 #define  STM_USB_EPR_STAT_RX_DISABLED                   0
 682 #define  STM_USB_EPR_STAT_RX_STALL                      1
 683 #define  STM_USB_EPR_STAT_RX_NAK                        2
 684 #define  STM_USB_EPR_STAT_RX_VALID                      3
 685 #define  STM_USB_EPR_STAT_RX_MASK                       3UL
 686 #define  STM_USB_EPR_STAT_RX_WRITE_INVARIANT            0
 687 #define STM_USB_EPR_SETUP       11
 688 #define STM_USB_EPR_EP_TYPE     9
 689 #define  STM_USB_EPR_EP_TYPE_BULK                       0
 690 #define  STM_USB_EPR_EP_TYPE_CONTROL                    1
 691 #define  STM_USB_EPR_EP_TYPE_ISO                        2
 692 #define  STM_USB_EPR_EP_TYPE_INTERRUPT                  3
 693 #define  STM_USB_EPR_EP_TYPE_MASK                       3UL
 694 #define STM_USB_EPR_EP_KIND     8
 695 #define  STM_USB_EPR_EP_KIND_DBL_BUF                    1       /* Bulk */
 696 #define  STM_USB_EPR_EP_KIND_STATUS_OUT                 1       /* Control */
 697 #define STM_USB_EPR_CTR_TX      7
 698 #define  STM_USB_CTR_TX_WRITE_INVARIANT                 1
 699 #define STM_USB_EPR_DTOG_TX     6
 700 #define  STM_USB_EPR_DTOG_TX_WRITE_INVARIANT            0
 701 #define STM_USB_EPR_STAT_TX     4
 702 #define  STM_USB_EPR_STAT_TX_DISABLED                   0
 703 #define  STM_USB_EPR_STAT_TX_STALL                      1
 704 #define  STM_USB_EPR_STAT_TX_NAK                        2
 705 #define  STM_USB_EPR_STAT_TX_VALID                      3
 706 #define  STM_USB_EPR_STAT_TX_WRITE_INVARIANT            0
 707 #define  STM_USB_EPR_STAT_TX_MASK                       3UL
 708 #define STM_USB_EPR_EA          0
 709 #define  STM_USB_EPR_EA_MASK                            0xfUL
 710
 711 #define STM_USB_CNTR_CTRM       15
 712 #define STM_USB_CNTR_PMAOVRM    14
 713 #define STM_USB_CNTR_ERRM       13
 714 #define STM_USB_CNTR_WKUPM      12
 715 #define STM_USB_CNTR_SUSPM      11
 716 #define STM_USB_CNTR_RESETM     10
 717 #define STM_USB_CNTR_SOFM       9
 718 #define STM_USB_CNTR_ESOFM      8
 719 #define STM_USB_CNTR_RESUME     4
 720 #define STM_USB_CNTR_FSUSP      3
 721 #define STM_USB_CNTR_LP_MODE    2
 722 #define STM_USB_CNTR_PDWN       1
 723 #define STM_USB_CNTR_FRES       0
 724
 725 #define STM_USB_ISTR_CTR        15
 726 #define STM_USB_ISTR_PMAOVR     14
 727 #define STM_USB_ISTR_ERR        13
 728 #define STM_USB_ISTR_WKUP       12
 729 #define STM_USB_ISTR_SUSP       11
 730 #define STM_USB_ISTR_RESET      10
 731 #define STM_USB_ISTR_SOF        9
 732 #define STM_USB_ISTR_ESOF       8
 733 #define STM_USB_ISTR_DIR        4
 734 #define STM_USB_ISTR_EP_ID      0
 735 #define  STM_USB_ISTR_EP_ID_MASK                0xfUL
 736
 737 #define STM_USB_FNR_RXDP        15
 738 #define STM_USB_FNR_RXDM        14
 739 #define STM_USB_FNR_LCK         13
 740 #define STM_USB_FNR_LSOF        11
 741 #define  STM_USB_FNR_LSOF_MASK                  0x3UL
 742 #define STM_USB_FNR_FN          0
 743 #define  STM_USB_FNR_FN_MASK                    0x7ffUL
 744
 745 #define STM_USB_DADDR_EF        7
 746 #define STM_USB_DADDR_ADD       0
 747 #define  STM_USB_DADDR_ADD_MASK                 0x7fUL
 748
 749 extern struct stm_usb stm_usb;
 750
 751 #define stm_usb (*((struct stm_usb *) 0x40005c00))
 752
 753 union stm_usb_bdt {
 754         struct {
 755                 vuint32_t       addr_tx;
 756                 vuint32_t       count_tx;
 757                 vuint32_t       addr_rx;
 758                 vuint32_t       count_rx;
 759         } single;
 760         struct {
 761                 vuint32_t       addr;
 762                 vuint32_t       count;
 763         } double_tx[2];
 764         struct {
 765                 vuint32_t       addr;
 766                 vuint32_t       count;
 767         } double_rx[2];
 768 };
 769
 770 #define STM_USB_BDT_COUNT_RX_BL_SIZE    15
 771 #define STM_USB_BDT_COUNT_RX_NUM_BLOCK  10
 772 #define  STM_USB_BDT_COUNT_RX_NUM_BLOCK_MASK    0x1fUL
 773 #define STM_USB_BDT_COUNT_RX_COUNT_RX   0
 774 #define  STM_USB_BDT_COUNT_RX_COUNT_RX_MASK     0x3ffUL
 775
 776 #define STM_USB_BDT_SIZE        8
 777
 778 extern uint8_t stm_usb_sram[] __attribute__ ((aligned(4)));
 779
 780 //#define stm_usb_sram ((uint8_t *)0x40006000)
 781
 782 struct stm_dma_channel {
 783         vuint32_t       ccr;
 784         vuint32_t       cndtr;
 785         vvoid_t         cpar;
 786         vvoid_t         cmar;
 787         vuint32_t       reserved;
 788 };
 789
 790 #define STM_NUM_DMA     7
 791
 792 struct stm_dma {
 793         vuint32_t               isr;
 794         vuint32_t               ifcr;
 795         struct stm_dma_channel  channel[STM_NUM_DMA];
 796 };
 797
 798 extern struct stm_dma stm_dma;
 799
 800 #define stm_dma (*((struct stm_dma *) 0x40020000))
 801
 802 /* DMA channels go from 1 to 7, instead of 0 to 6 (sigh)
 803  */
 804
 805 #define STM_DMA_INDEX(channel)          ((channel) - 1)
 806
 807 #define STM_DMA_ISR(index)              ((index) << 2)
 808 #define STM_DMA_ISR_MASK                        0xfUL
 809 #define STM_DMA_ISR_TEIF                        3
 810 #define STM_DMA_ISR_HTIF                        2
 811 #define STM_DMA_ISR_TCIF                        1
 812 #define STM_DMA_ISR_GIF                         0
 813
 814 #define STM_DMA_IFCR(index)             ((index) << 2)
 815 #define STM_DMA_IFCR_MASK                       0xfUL
 816 #define STM_DMA_IFCR_CTEIF                      3
 817 #define STM_DMA_IFCR_CHTIF                      2
 818 #define STM_DMA_IFCR_CTCIF                      1
 819 #define STM_DMA_IFCR_CGIF                       0
 820
 821 #define STM_DMA_CCR_MEM2MEM             (14)
 822
 823 #define STM_DMA_CCR_PL                  (12)
 824 #define  STM_DMA_CCR_PL_LOW                     (0)
 825 #define  STM_DMA_CCR_PL_MEDIUM                  (1)
 826 #define  STM_DMA_CCR_PL_HIGH                    (2)
 827 #define  STM_DMA_CCR_PL_VERY_HIGH               (3)
 828 #define  STM_DMA_CCR_PL_MASK                    (3)
 829
 830 #define STM_DMA_CCR_MSIZE               (10)
 831 #define  STM_DMA_CCR_MSIZE_8                    (0)
 832 #define  STM_DMA_CCR_MSIZE_16                   (1)
 833 #define  STM_DMA_CCR_MSIZE_32                   (2)
 834 #define  STM_DMA_CCR_MSIZE_MASK                 (3)
 835
 836 #define STM_DMA_CCR_PSIZE               (8)
 837 #define  STM_DMA_CCR_PSIZE_8                    (0)
 838 #define  STM_DMA_CCR_PSIZE_16                   (1)
 839 #define  STM_DMA_CCR_PSIZE_32                   (2)
 840 #define  STM_DMA_CCR_PSIZE_MASK                 (3)
 841
 842 #define STM_DMA_CCR_MINC                (7)
 843 #define STM_DMA_CCR_PINC                (6)
 844 #define STM_DMA_CCR_CIRC                (5)
 845 #define STM_DMA_CCR_DIR                 (4)
 846 #define  STM_DMA_CCR_DIR_PER_TO_MEM             0
 847 #define  STM_DMA_CCR_DIR_MEM_TO_PER             1
 848 #define STM_DMA_CCR_TEIE                (3)
 849 #define STM_DMA_CCR_HTIE                (2)
 850 #define STM_DMA_CCR_TCIE                (1)
 851 #define STM_DMA_CCR_EN                  (0)
 852
 853 #define STM_DMA_CHANNEL_ADC1            1
 854 #define STM_DMA_CHANNEL_SPI1_RX         2
 855 #define STM_DMA_CHANNEL_SPI1_TX         3
 856 #define STM_DMA_CHANNEL_SPI2_RX         4
 857 #define STM_DMA_CHANNEL_SPI2_TX         5
 858 #define STM_DMA_CHANNEL_USART3_TX       2
 859 #define STM_DMA_CHANNEL_USART3_RX       3
 860 #define STM_DMA_CHANNEL_USART1_TX       4
 861 #define STM_DMA_CHANNEL_USART1_RX       5
 862 #define STM_DMA_CHANNEL_USART2_RX       6
 863 #define STM_DMA_CHANNEL_USART2_TX       7
 864 #define STM_DMA_CHANNEL_I2C2_TX         4
 865 #define STM_DMA_CHANNEL_I2C2_RX         5
 866 #define STM_DMA_CHANNEL_I2C1_TX         6
 867 #define STM_DMA_CHANNEL_I2C1_RX         7
 868 #define STM_DMA_CHANNEL_TIM1_CH1        2
 869 #define STM_DMA_CHANNEL_TIM1_CH4        4
 870 #define STM_DMA_CHANNEL_TIM1_TRIG       4
 871 #define STM_DMA_CHANNEL_TIM1_COM        4
 872 #define STM_DMA_CHANNEL_TIM1_UP         5
 873 #define STM_DMA_CHANNEL_TIM1_CH3        6
 874 #define STM_DMA_CHANNEL_TIM2_CH3        1
 875 #define STM_DMA_CHANNEL_TIM2_UP         2
 876 #define STM_DMA_CHANNEL_TIM2_CH1        5
 877 #define STM_DMA_CHANNEL_TIM2_CH2        7
 878 #define STM_DMA_CHANNEL_TIM2_CH4        7
 879 #define STM_DMA_CHANNEL_TIM3_CH3        2
 880 #define STM_DMA_CHANNEL_TIM3_CH4        3
 881 #define STM_DMA_CHANNEL_TIM3_UP         3
 882 #define STM_DMA_CHANNEL_TIM3_CH1        6
 883 #define STM_DMA_CHANNEL_TIM3_TRIG       6
 884 #define STM_DMA_CHANNEL_TIM4_CH1        1
 885 #define STM_DMA_CHANNEL_TIM4_CH2        4
 886 #define STM_DMA_CHANNEL_TIM4_CH3        5
 887 #define STM_DMA_CHANNEL_TIM4_UP         7
 888
 889 /* high density, xl-density and connectivity devices also have dma2 */
 890
 891 #define STM_DMA2_CHANNEL_ADC3           5
 892 #define STM_DMA2_CHANNEL_SPI3_RX        1
 893 #define STM_DMA2_CHANNEL_SPI3_TX        2
 894 #define STM_DMA2_CHANNEL_UART4_RX       3
 895 #define STM_DMA2_CHANNEL_UART4_TX       5
 896 #define STM_DMA2_CHANNEL_TIM5_CH4       1
 897 #define STM_DMA2_CHANNEL_TIM5_TRIG      1
 898 #define STM_DMA2_CHANNEL_TIM5_CH3       2
 899 #define STM_DMA2_CHANNEL_TIM5_UP        2
 900 #define STM_DMA2_CHANNEL_TIM5_CH2       4
 901 #define STM_DMA2_CHANNEL_TIM5_CH1       5
 902 #define STM_DMA2_CHANNEL_TIM6_UP        3
 903 #define STM_DMA2_CHANNEL_DAC_CHANNEL1   3
 904 #define STM_DMA2_CHANNEL_TIM7_UP        4
 905 #define STM_DMA2_CHANNEL_DAC_CHANNEL2   4
 906 #define STM_DMA2_CHANNEL_TIM8_CH3       1
 907 #define STM_DMA2_CHANNEL_TIM8_UP        1
 908 #define STM_DMA2_CHANNEL_TIM8_CH4       2
 909 #define STM_DMA2_CHANNEL_TIM8_TRIG      2
 910 #define STM_DMA2_CHANNEL_TIM8_COM       2
 911 #define STM_DMA2_CHANNEL_TIM8_CH1       3
 912 #define STM_DMA2_CHANNEL_TIM8_CH2       5
 913
 914 struct stm_spi {
 915         vuint32_t       cr1;
 916         vuint32_t       cr2;
 917         vuint32_t       sr;
 918         vuint32_t       dr;
 919
 920         vuint32_t       crcpr;
 921         vuint32_t       rxcrcr;
 922         vuint32_t       txcrcr;
 923         vuint32_t       i2scfgr;
 924
 925         vuint32_t       i2spr;
 926 };
 927
 928 extern struct stm_spi stm_spi1, stm_spi2;
 929
 930 #define stm_spi1 (*((struct stm_spi *) 0x40013000))
 931 #define stm_spi2 (*((struct stm_spi *) 0x40003800))
 932
 933 /* SPI channels go from 1 to 2, instead of 0 to 1 (sigh)
 934  */
 935
 936 #define STM_NUM_SPI     2
 937
 938 #define STM_SPI_INDEX(channel)          ((channel) - 1)
 939
 940 #define STM_SPI_CR1_BIDIMODE            15
 941 #define STM_SPI_CR1_BIDIOE              14
 942 #define STM_SPI_CR1_CRCEN               13
 943 #define STM_SPI_CR1_CRCNEXT             12
 944 #define STM_SPI_CR1_DFF                 11
 945 #define STM_SPI_CR1_RXONLY              10
 946 #define STM_SPI_CR1_SSM                 9
 947 #define STM_SPI_CR1_SSI                 8
 948 #define STM_SPI_CR1_LSBFIRST            7
 949 #define STM_SPI_CR1_SPE                 6
 950 #define STM_SPI_CR1_BR                  3
 951 #define  STM_SPI_CR1_BR_PCLK_2                  0
 952 #define  STM_SPI_CR1_BR_PCLK_4                  1
 953 #define  STM_SPI_CR1_BR_PCLK_8                  2
 954 #define  STM_SPI_CR1_BR_PCLK_16                 3
 955 #define  STM_SPI_CR1_BR_PCLK_32                 4
 956 #define  STM_SPI_CR1_BR_PCLK_64                 5
 957 #define  STM_SPI_CR1_BR_PCLK_128                6
 958 #define  STM_SPI_CR1_BR_PCLK_256                7
 959 #define  STM_SPI_CR1_BR_MASK                    7UL
 960
 961 #define STM_SPI_CR1_MSTR                2
 962 #define STM_SPI_CR1_CPOL                1
 963 #define STM_SPI_CR1_CPHA                0
 964
 965 #define STM_SPI_CR2_TXEIE       7
 966 #define STM_SPI_CR2_RXNEIE      6
 967 #define STM_SPI_CR2_ERRIE       5
 968 #define STM_SPI_CR2_SSOE        2
 969 #define STM_SPI_CR2_TXDMAEN     1
 970 #define STM_SPI_CR2_RXDMAEN     0
 971
 972 #define STM_SPI_SR_FRE          8
 973 #define STM_SPI_SR_BSY          7
 974 #define STM_SPI_SR_OVR          6
 975 #define STM_SPI_SR_MODF         5
 976 #define STM_SPI_SR_CRCERR       4
 977 #define STM_SPI_SR_UDR          3
 978 #define STM_SPI_SR_CHSIDE       2
 979 #define STM_SPI_SR_TXE          1
 980 #define STM_SPI_SR_RXNE         0
 981
 982 #define STM_NUM_I2C     2
 983
 984 #define STM_I2C_INDEX(channel)  ((channel) - 1)
 985
 986 struct stm_i2c {
 987         vuint32_t       cr1;
 988         vuint32_t       cr2;
 989         vuint32_t       oar1;
 990         vuint32_t       oar2;
 991         vuint32_t       dr;
 992         vuint32_t       sr1;
 993         vuint32_t       sr2;
 994         vuint32_t       ccr;
 995         vuint32_t       trise;
 996 };
 997
 998 extern struct stm_i2c stm_i2c1, stm_i2c2;
 999
1000 #define stm_i2c1        (*((struct stm_i2c *) 0x40005400))
1001 #define stm_i2c2        (*((struct stm_i2c *) 0x40005800))
1002
1003 #define STM_I2C_CR1_SWRST       15
1004 #define STM_I2C_CR1_ALERT       13
1005 #define STM_I2C_CR1_PEC         12
1006 #define STM_I2C_CR1_POS         11
1007 #define STM_I2C_CR1_ACK         10
1008 #define STM_I2C_CR1_STOP        9
1009 #define STM_I2C_CR1_START       8
1010 #define STM_I2C_CR1_NOSTRETCH   7
1011 #define STM_I2C_CR1_ENGC        6
1012 #define STM_I2C_CR1_ENPEC       5
1013 #define STM_I2C_CR1_ENARP       4
1014 #define STM_I2C_CR1_SMBTYPE     3
1015 #define STM_I2C_CR1_SMBUS       1
1016 #define STM_I2C_CR1_PE          0
1017
1018 #define STM_I2C_CR2_LAST        12
1019 #define STM_I2C_CR2_DMAEN       11
1020 #define STM_I2C_CR2_ITBUFEN     10
1021 #define STM_I2C_CR2_ITEVTEN     9
1022 #define STM_I2C_CR2_ITERREN     8
1023 #define STM_I2C_CR2_FREQ        0
1024 #define  STM_I2C_CR2_FREQ_MASK          0x3fUL
1025
1026 #define STM_I2C_SR1_SMBALERT    15
1027 #define STM_I2C_SR1_TIMEOUT     14
1028 #define STM_I2C_SR1_PECERR      12
1029 #define STM_I2C_SR1_OVR         11
1030 #define STM_I2C_SR1_AF          10
1031 #define STM_I2C_SR1_ARLO        9
1032 #define STM_I2C_SR1_BERR        8
1033 #define STM_I2C_SR1_TXE         7
1034 #define STM_I2C_SR1_RXNE        6
1035 #define STM_I2C_SR1_STOPF       4
1036 #define STM_I2C_SR1_ADD10       3
1037 #define STM_I2C_SR1_BTF         2
1038 #define STM_I2C_SR1_ADDR        1
1039 #define STM_I2C_SR1_SB          0
1040
1041 #define STM_I2C_SR2_PEC         8
1042 #define  STM_I2C_SR2_PEC_MASK   0xff00UL
1043 #define STM_I2C_SR2_DUALF       7
1044 #define STM_I2C_SR2_SMBHOST     6
1045 #define STM_I2C_SR2_SMBDEFAULT  5
1046 #define STM_I2C_SR2_GENCALL     4
1047 #define STM_I2C_SR2_TRA         2
1048 #define STM_I2C_SR2_BUSY        1
1049 #define STM_I2C_SR2_MSL         0
1050
1051 #define STM_I2C_CCR_FS          15
1052 #define STM_I2C_CCR_DUTY        14
1053 #define STM_I2C_CCR_CCR         0
1054 #define  STM_I2C_CCR_MASK       0x7ffUL
1055
1056 struct stm_adc {
1057         vuint32_t       sr;
1058         vuint32_t       cr1;
1059         vuint32_t       cr2;
1060         vuint32_t       smpr1;
1061
1062         vuint32_t       smpr2;
1063         vuint32_t       jofr1;
1064         vuint32_t       jofr2;
1065         vuint32_t       jofr3;
1066
1067         vuint32_t       jofr4;
1068         vuint32_t       htr;
1069         vuint32_t       ltr;
1070         vuint32_t       sqr1;
1071
1072         vuint32_t       sqr2;
1073         vuint32_t       sqr3;
1074         vuint32_t       jsqr;
1075         vuint32_t       jdr1;
1076
1077         vuint32_t       jdr2;
1078         vuint32_t       jdr3;
1079         vuint32_t       jdr4;
1080         vuint32_t       dr;
1081 };
1082
1083 extern struct stm_adc stm_adc;
1084
1085 #define stm_adc (*((struct stm_adc *) 0x40012400))
1086
1087 #define STM_ADC_SQ_TEMP         16
1088 #define STM_ADC_SQ_V_REF        17
1089
1090 #define STM_ADC_SR_STRT         4
1091 #define STM_ADC_SR_JSTRT        3
1092 #define STM_ADC_SR_JEOC         2
1093 #define STM_ADC_SR_EOC          1
1094 #define STM_ADC_SR_AWD          0
1095
1096 #define STM_ADC_CR1_AWDEN       23
1097 #define STM_ADC_CR1_JAWDEN      22
1098 #define STM_ADC_CR1_DUALMOD     16
1099 # define STM_ADC_CR1_DUALMOD_INDEPENDENT                0
1100 # define STM_ADC_CR1_DUALMOD_COMB_REG_SIM_INJ_SIM       1
1101 # define STM_ADC_CR1_DUALMOD_COMB_REG_SIM_ALT_TRIG      2
1102 # define STM_ADC_CR1_DUALMOD_COMB_INJ_SIM_FAST_INT      3
1103 # define STM_ADC_CR1_DUALMOD_COMB_INJ_SIM_SLOW_INT      4
1104 # define STM_ADC_CR1_DUALMOD_INJ_SIM                    5
1105 # define STM_ADC_CR1_DUALMOD_REG_SIM                    6
1106 # define STM_ADC_CR1_DUALMOD_FAST_INT                   7
1107 # define STM_ADC_CR1_DUALMOD_SLOW_INT                   8
1108 # define STM_ADC_CR1_DUALMOD_ALT_TRIG                   9
1109
1110 #define STM_ADC_CR1_DISCNUM     13
1111 #define  STM_ADC_CR1_DISCNUM_1          0
1112 #define  STM_ADC_CR1_DISCNUM_2          1
1113 #define  STM_ADC_CR1_DISCNUM_3          2
1114 #define  STM_ADC_CR1_DISCNUM_4          3
1115 #define  STM_ADC_CR1_DISCNUM_5          4
1116 #define  STM_ADC_CR1_DISCNUM_6          5
1117 #define  STM_ADC_CR1_DISCNUM_7          6
1118 #define  STM_ADC_CR1_DISCNUM_8          7
1119 #define  STM_ADC_CR1_DISCNUM_MASK       7UL
1120 #define STM_ADC_CR1_JDISCEN     12
1121 #define STM_ADC_CR1_DISCEN      11
1122 #define STM_ADC_CR1_JAUTO       10
1123 #define STM_ADC_CR1_AWDSGL      9
1124 #define STM_ADC_CR1_SCAN        8
1125 #define STM_ADC_CR1_JEOCIE      7
1126 #define STM_ADC_CR1_AWDIE       6
1127 #define STM_ADC_CR1_EOCIE       5
1128 #define STM_ADC_CR1_AWDCH       0
1129 #define  STM_ADC_CR1_AWDCH_MASK         0x1fUL
1130
1131 #define STM_ADC_CR2_TSVREF      23
1132 #define STM_ADC_CR2_SWSTART     21
1133 #define STM_ADC_CR2_JWSTART     21
1134 #define STM_ADC_CR2_EXTTRIG     20
1135 #define STM_ADC_CR2_EXTSEL      17
1136 #define  STM_ADC_CR2_EXTSEL_TIM1_CC1    0
1137 #define  STM_ADC_CR2_EXTSEL_TIM1_CC2    1
1138 #define  STM_ADC_CR2_EXTSEL_TIM1_CC3    2
1139 #define  STM_ADC_CR2_EXTSEL_TIM2_CC2    3
1140 #define  STM_ADC_CR2_EXTSEL_TIM3_TRGO   4
1141 #define  STM_ADC_CR2_EXTSEL_TIM4_CC4    5
1142 #define  STM_ADC_CR2_EXTSEL_EXTI        6
1143 #define  STM_ADC_CR2_EXTSEL_SWSTART     7
1144 #define  STM_ADC_CR2_EXTSEL_MASK        7UL
1145 #define STM_ADC_CR2_JEXTTRIG    15
1146 #define STM_ADC_CR2_JEXTSEL     12
1147 #define  STM_ADC_CR2_JEXTSEL_TIM1_TRGO  0
1148 #define  STM_ADC_CR2_JEXTSEL_TIM1_CC4   1
1149 #define  STM_ADC_CR2_JEXTSEL_TIM2_TRGO  2
1150 #define  STM_ADC_CR2_JEXTSEL_TIM2_CC1   3
1151 #define  STM_ADC_CR2_JEXTSEL_TIM3_CC4   4
1152 #define  STM_ADC_CR2_JEXTSEL_TIM4_TRGO  5
1153 #define  STM_ADC_CR2_JEXTSEL_EXTI_15    6
1154 #define  STM_ADC_CR2_JEXTSEL_JSWSTART   7
1155 #define  STM_ADC_CR2_JEXTSEL_MASK       7UL
1156 #define STM_ADC_CR2_ALIGN       11
1157 #define STM_ADC_CR2_DMA         8
1158 #define STM_ADC_CR2_RSTCAL      3
1159 #define STM_ADC_CR2_CAL         2
1160 #define STM_ADC_CR2_CONT        1
1161 #define STM_ADC_CR2_ADON        0
1162
1163 struct stm_exti {
1164         vuint32_t       imr;
1165         vuint32_t       emr;
1166         vuint32_t       rtsr;
1167         vuint32_t       ftsr;
1168
1169         vuint32_t       swier;
1170         vuint32_t       pr;
1171 };
1172
1173 extern struct stm_exti stm_exti;
1174
1175 #define stm_exti        (*((struct stm_exti *) 0x40010400))
1176
1177 static inline void
1178 stm_exticr_set(struct stm_gpio *gpio, int pin) {
1179         uint8_t reg = (uint8_t) (pin >> 2);
1180         uint8_t shift = (pin & 3) << 2;
1181         uint8_t val = 0;
1182
1183         /* Enable AFIO */
1184         stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_AFIOEN);
1185
1186         if (gpio == &stm_gpioa)
1187                 val = STM_AFIO_EXTICR_PA;
1188         else if (gpio == &stm_gpiob)
1189                 val = STM_AFIO_EXTICR_PB;
1190         else if (gpio == &stm_gpioc)
1191                 val = STM_AFIO_EXTICR_PC;
1192         else if (gpio == &stm_gpiod)
1193                 val = STM_AFIO_EXTICR_PD;
1194         else if (gpio == &stm_gpioe)
1195                 val = STM_AFIO_EXTICR_PE;
1196
1197         stm_afio.exticr[reg] = (stm_afio.exticr[reg] & (uint32_t) ~(0xf << shift)) | val << shift;
1198 }
1199
1200 struct stm_tim18 {
1201         vuint32_t       cr1;
1202         vuint32_t       cr2;
1203         vuint32_t       smcr;
1204         vuint32_t       dier;
1205
1206         vuint32_t       sr;
1207         vuint32_t       egr;
1208         vuint32_t       ccmr1;
1209         vuint32_t       ccmr2;
1210
1211         vuint32_t       ccer;
1212         vuint32_t       cnt;
1213         vuint32_t       psc;
1214         vuint32_t       arr;
1215
1216         vuint32_t       rcr;
1217         vuint32_t       ccr1;
1218         vuint32_t       ccr2;
1219         vuint32_t       ccr3;
1220
1221         vuint32_t       ccr4;
1222         uint32_t        bdtr;
1223         vuint32_t       dcr;
1224         vuint32_t       dmar;
1225 };
1226
1227 extern struct stm_tim18 stm_tim1, stm_tim8;
1228
1229 #define stm_tim1        (*((struct stm_tim18 *) 0x40012c00))
1230 #define stm_tim8        (*((struct stm_tim18 *) 0x40013400))
1231
1232 #define STM_TIM18_CR1_CKD       8
1233 #define  STM_TIM18_CR1_CKD_1            0
1234 #define  STM_TIM18_CR1_CKD_2            1
1235 #define  STM_TIM18_CR1_CKD_4            2
1236 #define  STM_TIM18_CR1_CKD_MASK 3UL
1237 #define STM_TIM18_CR1_ARPE      7
1238 #define STM_TIM18_CR1_CMS       5
1239 #define  STM_TIM18_CR1_CMS_EDGE 0
1240 #define  STM_TIM18_CR1_CMS_CENTER_1     1
1241 #define  STM_TIM18_CR1_CMS_CENTER_2     2
1242 #define  STM_TIM18_CR1_CMS_CENTER_3     3
1243 #define  STM_TIM18_CR1_CMS_MASK 3UL
1244 #define STM_TIM18_CR1_DIR       4
1245 #define  STM_TIM18_CR1_DIR_UP           0
1246 #define  STM_TIM18_CR1_DIR_DOWN 1
1247 #define STM_TIM18_CR1_OPM       3
1248 #define STM_TIM18_CR1_URS       2
1249 #define STM_TIM18_CR1_UDIS      1
1250 #define STM_TIM18_CR1_CEN       0
1251
1252 #define STM_TIM18_CR2_TI1S      7
1253 #define STM_TIM18_CR2_MMS       4
1254 #define  STM_TIM18_CR2_MMS_RESET                0
1255 #define  STM_TIM18_CR2_MMS_ENABLE               1
1256 #define  STM_TIM18_CR2_MMS_UPDATE               2
1257 #define  STM_TIM18_CR2_MMS_COMPARE_PULSE        3
1258 #define  STM_TIM18_CR2_MMS_COMPARE_OC1REF       4
1259 #define  STM_TIM18_CR2_MMS_COMPARE_OC2REF       5
1260 #define  STM_TIM18_CR2_MMS_COMPARE_OC3REF       6
1261 #define  STM_TIM18_CR2_MMS_COMPARE_OC4REF       7
1262 #define  STM_TIM18_CR2_MMS_MASK         7UL
1263 #define STM_TIM18_CR2_CCDS      3
1264
1265 #define STM_TIM18_SMCR_ETP      15
1266 #define STM_TIM18_SMCR_ECE      14
1267 #define STM_TIM18_SMCR_ETPS     12
1268 #define  STM_TIM18_SMCR_ETPS_OFF                0
1269 #define  STM_TIM18_SMCR_ETPS_DIV_2              1
1270 #define  STM_TIM18_SMCR_ETPS_DIV_4              2
1271 #define  STM_TIM18_SMCR_ETPS_DIV_8              3
1272 #define  STM_TIM18_SMCR_ETPS_MASK               3UL
1273 #define STM_TIM18_SMCR_ETF      8
1274 #define  STM_TIM18_SMCR_ETF_NONE                0
1275 #define  STM_TIM18_SMCR_ETF_INT_N_2             1
1276 #define  STM_TIM18_SMCR_ETF_INT_N_4             2
1277 #define  STM_TIM18_SMCR_ETF_INT_N_8             3
1278 #define  STM_TIM18_SMCR_ETF_DTS_2_N_6           4
1279 #define  STM_TIM18_SMCR_ETF_DTS_2_N_8           5
1280 #define  STM_TIM18_SMCR_ETF_DTS_4_N_6           6
1281 #define  STM_TIM18_SMCR_ETF_DTS_4_N_8           7
1282 #define  STM_TIM18_SMCR_ETF_DTS_8_N_6           8
1283 #define  STM_TIM18_SMCR_ETF_DTS_8_N_8           9
1284 #define  STM_TIM18_SMCR_ETF_DTS_16_N_5          10
1285 #define  STM_TIM18_SMCR_ETF_DTS_16_N_6          11
1286 #define  STM_TIM18_SMCR_ETF_DTS_16_N_8          12
1287 #define  STM_TIM18_SMCR_ETF_DTS_32_N_5          13
1288 #define  STM_TIM18_SMCR_ETF_DTS_32_N_6          14
1289 #define  STM_TIM18_SMCR_ETF_DTS_32_N_8          15
1290 #define  STM_TIM18_SMCR_ETF_MASK                15UL
1291 #define STM_TIM18_SMCR_MSM      7
1292 #define STM_TIM18_SMCR_TS       4
1293 #define  STM_TIM18_SMCR_TS_ITR0         0
1294 #define  STM_TIM18_SMCR_TS_ITR1         1
1295 #define  STM_TIM18_SMCR_TS_ITR2         2
1296 #define  STM_TIM18_SMCR_TS_ITR3         3
1297 #define  STM_TIM18_SMCR_TS_TI1F_ED              4
1298 #define  STM_TIM18_SMCR_TS_TI1FP1               5
1299 #define  STM_TIM18_SMCR_TS_TI2FP2               6
1300 #define  STM_TIM18_SMCR_TS_ETRF         7
1301 #define  STM_TIM18_SMCR_TS_MASK         7UL
1302 #define STM_TIM18_SMCR_SMS      0
1303 #define  STM_TIM18_SMCR_SMS_DISABLE             0
1304 #define  STM_TIM18_SMCR_SMS_ENCODER_MODE_1      1
1305 #define  STM_TIM18_SMCR_SMS_ENCODER_MODE_2      2
1306 #define  STM_TIM18_SMCR_SMS_ENCODER_MODE_3      3
1307 #define  STM_TIM18_SMCR_SMS_RESET_MODE          4
1308 #define  STM_TIM18_SMCR_SMS_GATED_MODE          5
1309 #define  STM_TIM18_SMCR_SMS_TRIGGER_MODE        6
1310 #define  STM_TIM18_SMCR_SMS_EXTERNAL_CLOCK      7
1311 #define  STM_TIM18_SMCR_SMS_MASK                7UL
1312
1313 #define STM_TIM18_DIER_TDE              14
1314 #define STM_TIM18_DIER_CC4DE            12
1315 #define STM_TIM18_DIER_CC3DE            11
1316 #define STM_TIM18_DIER_CC2DE            10
1317 #define STM_TIM18_DIER_CC1DE            9
1318 #define STM_TIM18_DIER_UDE              8
1319
1320 #define STM_TIM18_DIER_TIE              6
1321 #define STM_TIM18_DIER_CC4IE            4
1322 #define STM_TIM18_DIER_CC3IE            3
1323 #define STM_TIM18_DIER_CC2IE            2
1324 #define STM_TIM18_DIER_CC1IE            1
1325 #define STM_TIM18_DIER_UIE              0
1326
1327 #define STM_TIM18_SR_CC4OF      12
1328 #define STM_TIM18_SR_CC3OF      11
1329 #define STM_TIM18_SR_CC2OF      10
1330 #define STM_TIM18_SR_CC1OF      9
1331 #define STM_TIM18_SR_TIF        6
1332 #define STM_TIM18_SR_CC4IF      4
1333 #define STM_TIM18_SR_CC3IF      3
1334 #define STM_TIM18_SR_CC2IF      2
1335 #define STM_TIM18_SR_CC1IF      1
1336 #define STM_TIM18_SR_UIF        0
1337
1338 #define STM_TIM18_EGR_TG        6
1339 #define STM_TIM18_EGR_CC4G      4
1340 #define STM_TIM18_EGR_CC3G      3
1341 #define STM_TIM18_EGR_CC2G      2
1342 #define STM_TIM18_EGR_CC1G      1
1343 #define STM_TIM18_EGR_UG        0
1344
1345 #define STM_TIM18_CCMR1_OC2CE   15
1346 #define STM_TIM18_CCMR1_OC2M    12
1347 #define  STM_TIM18_CCMR1_OC2M_FROZEN                    0
1348 #define  STM_TIM18_CCMR1_OC2M_SET_HIGH_ON_MATCH 1
1349 #define  STM_TIM18_CCMR1_OC2M_SET_LOW_ON_MATCH          2
1350 #define  STM_TIM18_CCMR1_OC2M_TOGGLE                    3
1351 #define  STM_TIM18_CCMR1_OC2M_FORCE_LOW         4
1352 #define  STM_TIM18_CCMR1_OC2M_FORCE_HIGH                5
1353 #define  STM_TIM18_CCMR1_OC2M_PWM_MODE_1                6
1354 #define  STM_TIM18_CCMR1_OC2M_PWM_MODE_2                7
1355 #define  STM_TIM18_CCMR1_OC2M_MASK                      7UL
1356 #define STM_TIM18_CCMR1_OC2PE   11
1357 #define STM_TIM18_CCMR1_OC2FE   10
1358 #define STM_TIM18_CCMR1_CC2S    8
1359 #define  STM_TIM18_CCMR1_CC2S_OUTPUT                    0
1360 #define  STM_TIM18_CCMR1_CC2S_INPUT_TI2         1
1361 #define  STM_TIM18_CCMR1_CC2S_INPUT_TI1         2
1362 #define  STM_TIM18_CCMR1_CC2S_INPUT_TRC         3
1363 #define  STM_TIM18_CCMR1_CC2S_MASK                      3UL
1364
1365 #define STM_TIM18_CCMR1_OC1CE   7
1366 #define STM_TIM18_CCMR1_OC1M    4
1367 #define  STM_TIM18_CCMR1_OC1M_FROZEN                    0
1368 #define  STM_TIM18_CCMR1_OC1M_SET_HIGH_ON_MATCH 1
1369 #define  STM_TIM18_CCMR1_OC1M_SET_LOW_ON_MATCH          2
1370 #define  STM_TIM18_CCMR1_OC1M_TOGGLE                    3
1371 #define  STM_TIM18_CCMR1_OC1M_FORCE_LOW         4
1372 #define  STM_TIM18_CCMR1_OC1M_FORCE_HIGH                5
1373 #define  STM_TIM18_CCMR1_OC1M_PWM_MODE_1                6
1374 #define  STM_TIM18_CCMR1_OC1M_PWM_MODE_2                7
1375 #define  STM_TIM18_CCMR1_OC1M_MASK                      7UL
1376 #define STM_TIM18_CCMR1_OC1PE   3
1377 #define STM_TIM18_CCMR1_OC1FE   2
1378 #define STM_TIM18_CCMR1_CC1S    0
1379 #define  STM_TIM18_CCMR1_CC1S_OUTPUT                    0
1380 #define  STM_TIM18_CCMR1_CC1S_INPUT_TI1         1
1381 #define  STM_TIM18_CCMR1_CC1S_INPUT_TI2         2
1382 #define  STM_TIM18_CCMR1_CC1S_INPUT_TRC         3
1383 #define  STM_TIM18_CCMR1_CC1S_MASK                      3UL
1384
1385 #define STM_TIM18_CCMR1_IC2F    12
1386 #define  STM_TIM18_CCMR1_IC2F_NONE                      0
1387 #define  STM_TIM18_CCMR1_IC2F_CK_INT_N_2                1
1388 #define  STM_TIM18_CCMR1_IC2F_CK_INT_N_4                2
1389 #define  STM_TIM18_CCMR1_IC2F_CK_INT_N_8                3
1390 #define  STM_TIM18_CCMR1_IC2F_DTS_2_N_6         4
1391 #define  STM_TIM18_CCMR1_IC2F_DTS_2_N_8         5
1392 #define  STM_TIM18_CCMR1_IC2F_DTS_4_N_6         6
1393 #define  STM_TIM18_CCMR1_IC2F_DTS_4_N_8         7
1394 #define  STM_TIM18_CCMR1_IC2F_DTS_8_N_6         8
1395 #define  STM_TIM18_CCMR1_IC2F_DTS_8_N_8         9
1396 #define  STM_TIM18_CCMR1_IC2F_DTS_16_N_5                10
1397 #define  STM_TIM18_CCMR1_IC2F_DTS_16_N_6                11
1398 #define  STM_TIM18_CCMR1_IC2F_DTS_16_N_8                12
1399 #define  STM_TIM18_CCMR1_IC2F_DTS_32_N_5                13
1400 #define  STM_TIM18_CCMR1_IC2F_DTS_32_N_6                14
1401 #define  STM_TIM18_CCMR1_IC2F_DTS_32_N_8                15
1402 #define STM_TIM18_CCMR1_IC2PSC  10
1403 #define  STM_TIM18_CCMR1_IC2PSC_NONE                    0
1404 #define  STM_TIM18_CCMR1_IC2PSC_2                       1
1405 #define  STM_TIM18_CCMR1_IC2PSC_4                       2
1406 #define  STM_TIM18_CCMR1_IC2PSC_8                       3
1407 #define STM_TIM18_CCMR1_IC1F    4
1408 #define  STM_TIM18_CCMR1_IC1F_NONE                      0
1409 #define  STM_TIM18_CCMR1_IC1F_CK_INT_N_2                1
1410 #define  STM_TIM18_CCMR1_IC1F_CK_INT_N_4                2
1411 #define  STM_TIM18_CCMR1_IC1F_CK_INT_N_8                3
1412 #define  STM_TIM18_CCMR1_IC1F_DTS_2_N_6         4
1413 #define  STM_TIM18_CCMR1_IC1F_DTS_2_N_8         5
1414 #define  STM_TIM18_CCMR1_IC1F_DTS_4_N_6         6
1415 #define  STM_TIM18_CCMR1_IC1F_DTS_4_N_8         7
1416 #define  STM_TIM18_CCMR1_IC1F_DTS_8_N_6         8
1417 #define  STM_TIM18_CCMR1_IC1F_DTS_8_N_8         9
1418 #define  STM_TIM18_CCMR1_IC1F_DTS_16_N_5                10
1419 #define  STM_TIM18_CCMR1_IC1F_DTS_16_N_6                11
1420 #define  STM_TIM18_CCMR1_IC1F_DTS_16_N_8                12
1421 #define  STM_TIM18_CCMR1_IC1F_DTS_32_N_5                13
1422 #define  STM_TIM18_CCMR1_IC1F_DTS_32_N_6                14
1423 #define  STM_TIM18_CCMR1_IC1F_DTS_32_N_8                15
1424 #define STM_TIM18_CCMR1_IC1PSC  2
1425 #define  STM_TIM18_CCMR1_IC1PSC_NONE                    0
1426 #define  STM_TIM18_CCMR1_IC1PSC_2                       1
1427 #define  STM_TIM18_CCMR1_IC1PSC_4                       2
1428 #define  STM_TIM18_CCMR1_IC1PSC_8                       3
1429
1430 #define STM_TIM18_CCMR2_OC4CE   15
1431 #define STM_TIM18_CCMR2_OC4M    12
1432 #define  STM_TIM18_CCMR2_OC4M_FROZEN                    0
1433 #define  STM_TIM18_CCMR2_OC4M_SET_HIGH_ON_MATCH 1
1434 #define  STM_TIM18_CCMR2_OC4M_SET_LOW_ON_MATCH          2
1435 #define  STM_TIM18_CCMR2_OC4M_TOGGLE                    3
1436 #define  STM_TIM18_CCMR2_OC4M_FORCE_LOW         4
1437 #define  STM_TIM18_CCMR2_OC4M_FORCE_HIGH                5
1438 #define  STM_TIM18_CCMR2_OC4M_PWM_MODE_1                6
1439 #define  STM_TIM18_CCMR2_OC4M_PWM_MODE_2                7
1440 #define  STM_TIM18_CCMR2_OC4M_MASK                      7UL
1441 #define STM_TIM18_CCMR2_OC4PE   11
1442 #define STM_TIM18_CCMR2_OC4FE   10
1443 #define STM_TIM18_CCMR2_CC4S    8
1444 #define  STM_TIM18_CCMR2_CC4S_OUTPUT                    0
1445 #define  STM_TIM18_CCMR2_CC4S_INPUT_TI4         1
1446 #define  STM_TIM18_CCMR2_CC4S_INPUT_TI3         2
1447 #define  STM_TIM18_CCMR2_CC4S_INPUT_TRC         3
1448 #define  STM_TIM18_CCMR2_CC4S_MASK                      3UL
1449
1450 #define STM_TIM18_CCMR2_OC3CE   7
1451 #define STM_TIM18_CCMR2_OC3M    4
1452 #define  STM_TIM18_CCMR2_OC3M_FROZEN                    0
1453 #define  STM_TIM18_CCMR2_OC3M_SET_HIGH_ON_MATCH 1
1454 #define  STM_TIM18_CCMR2_OC3M_SET_LOW_ON_MATCH          2
1455 #define  STM_TIM18_CCMR2_OC3M_TOGGLE                    3
1456 #define  STM_TIM18_CCMR2_OC3M_FORCE_LOW         4
1457 #define  STM_TIM18_CCMR2_OC3M_FORCE_HIGH                5
1458 #define  STM_TIM18_CCMR2_OC3M_PWM_MODE_1                6
1459 #define  STM_TIM18_CCMR2_OC3M_PWM_MODE_2                7
1460 #define  STM_TIM18_CCMR2_OC3M_MASK                      7UL
1461 #define STM_TIM18_CCMR2_OC3PE   3
1462 #define STM_TIM18_CCMR2_OC3FE   2
1463 #define STM_TIM18_CCMR2_CC3S    0
1464 #define  STM_TIM18_CCMR2_CC3S_OUTPUT                    0
1465 #define  STM_TIM18_CCMR2_CC3S_INPUT_TI3         1
1466 #define  STM_TIM18_CCMR2_CC3S_INPUT_TI4         2
1467 #define  STM_TIM18_CCMR2_CC3S_INPUT_TRC         3
1468 #define  STM_TIM18_CCMR2_CC3S_MASK                      3UL
1469
1470 #define STM_TIM18_CCER_CC4NP    15
1471 #define STM_TIM18_CCER_CC4P     13
1472 #define  STM_TIM18_CCER_CC4P_ACTIVE_HIGH        0
1473 #define  STM_TIM18_CCER_CC4P_ACTIVE_LOW 1
1474 #define STM_TIM18_CCER_CC4E     12
1475 #define STM_TIM18_CCER_CC3NP    11
1476 #define STM_TIM18_CCER_CC3P     9
1477 #define  STM_TIM18_CCER_CC3P_ACTIVE_HIGH        0
1478 #define  STM_TIM18_CCER_CC3P_ACTIVE_LOW 1
1479 #define STM_TIM18_CCER_CC3E     8
1480 #define STM_TIM18_CCER_CC2NP    7
1481 #define STM_TIM18_CCER_CC2P     5
1482 #define  STM_TIM18_CCER_CC2P_ACTIVE_HIGH        0
1483 #define  STM_TIM18_CCER_CC2P_ACTIVE_LOW 1
1484 #define STM_TIM18_CCER_CC2E     4
1485 #define STM_TIM18_CCER_CC1NP    3
1486 #define STM_TIM18_CCER_CC1P     1
1487 #define  STM_TIM18_CCER_CC1P_ACTIVE_HIGH        0
1488 #define  STM_TIM18_CCER_CC1P_ACTIVE_LOW 1
1489 #define STM_TIM18_CCER_CC1E     0
1490
1491 struct stm_tim234 {
1492         vuint32_t       cr1;
1493         vuint32_t       cr2;
1494         vuint32_t       smcr;
1495         vuint32_t       dier;
1496
1497         vuint32_t       sr;
1498         vuint32_t       egr;
1499         vuint32_t       ccmr1;
1500         vuint32_t       ccmr2;
1501
1502         vuint32_t       ccer;
1503         vuint32_t       cnt;
1504         vuint32_t       psc;
1505         vuint32_t       arr;
1506
1507         uint32_t        reserved_30;
1508         vuint32_t       ccr1;
1509         vuint32_t       ccr2;
1510         vuint32_t       ccr3;
1511
1512         vuint32_t       ccr4;
1513         uint32_t        reserved_44;
1514         vuint32_t       dcr;
1515         vuint32_t       dmar;
1516 };
1517
1518 extern struct stm_tim234 stm_tim2, stm_tim3, stm_tim4;
1519
1520 #define stm_tim2        (*((struct stm_tim234 *) 0x40000000))
1521 #define stm_tim3        (*((struct stm_tim234 *) 0x40000400))
1522 #define stm_tim4        (*((struct stm_tim234 *) 0x40000800))
1523
1524 #define STM_TIM234_CR1_CKD      8
1525 #define  STM_TIM234_CR1_CKD_1           0
1526 #define  STM_TIM234_CR1_CKD_2           1
1527 #define  STM_TIM234_CR1_CKD_4           2
1528 #define  STM_TIM234_CR1_CKD_MASK        3UL
1529 #define STM_TIM234_CR1_ARPE     7
1530 #define STM_TIM234_CR1_CMS      5
1531 #define  STM_TIM234_CR1_CMS_EDGE        0
1532 #define  STM_TIM234_CR1_CMS_CENTER_1    1
1533 #define  STM_TIM234_CR1_CMS_CENTER_2    2
1534 #define  STM_TIM234_CR1_CMS_CENTER_3    3
1535 #define  STM_TIM234_CR1_CMS_MASK        3UL
1536 #define STM_TIM234_CR1_DIR      4
1537 #define  STM_TIM234_CR1_DIR_UP          0
1538 #define  STM_TIM234_CR1_DIR_DOWN        1
1539 #define STM_TIM234_CR1_OPM      3
1540 #define STM_TIM234_CR1_URS      2
1541 #define STM_TIM234_CR1_UDIS     1
1542 #define STM_TIM234_CR1_CEN      0
1543
1544 #define STM_TIM234_CR2_TI1S     7
1545 #define STM_TIM234_CR2_MMS      4
1546 #define  STM_TIM234_CR2_MMS_RESET               0
1547 #define  STM_TIM234_CR2_MMS_ENABLE              1
1548 #define  STM_TIM234_CR2_MMS_UPDATE              2
1549 #define  STM_TIM234_CR2_MMS_COMPARE_PULSE       3
1550 #define  STM_TIM234_CR2_MMS_COMPARE_OC1REF      4
1551 #define  STM_TIM234_CR2_MMS_COMPARE_OC2REF      5
1552 #define  STM_TIM234_CR2_MMS_COMPARE_OC3REF      6
1553 #define  STM_TIM234_CR2_MMS_COMPARE_OC4REF      7
1554 #define  STM_TIM234_CR2_MMS_MASK                7UL
1555 #define STM_TIM234_CR2_CCDS     3
1556
1557 #define STM_TIM234_SMCR_ETP     15
1558 #define STM_TIM234_SMCR_ECE     14
1559 #define STM_TIM234_SMCR_ETPS    12
1560 #define  STM_TIM234_SMCR_ETPS_OFF               0
1561 #define  STM_TIM234_SMCR_ETPS_DIV_2             1
1562 #define  STM_TIM234_SMCR_ETPS_DIV_4             2
1563 #define  STM_TIM234_SMCR_ETPS_DIV_8             3
1564 #define  STM_TIM234_SMCR_ETPS_MASK              3UL
1565 #define STM_TIM234_SMCR_ETF     8
1566 #define  STM_TIM234_SMCR_ETF_NONE               0
1567 #define  STM_TIM234_SMCR_ETF_INT_N_2            1
1568 #define  STM_TIM234_SMCR_ETF_INT_N_4            2
1569 #define  STM_TIM234_SMCR_ETF_INT_N_8            3
1570 #define  STM_TIM234_SMCR_ETF_DTS_2_N_6          4
1571 #define  STM_TIM234_SMCR_ETF_DTS_2_N_8          5
1572 #define  STM_TIM234_SMCR_ETF_DTS_4_N_6          6
1573 #define  STM_TIM234_SMCR_ETF_DTS_4_N_8          7
1574 #define  STM_TIM234_SMCR_ETF_DTS_8_N_6          8
1575 #define  STM_TIM234_SMCR_ETF_DTS_8_N_8          9
1576 #define  STM_TIM234_SMCR_ETF_DTS_16_N_5         10
1577 #define  STM_TIM234_SMCR_ETF_DTS_16_N_6         11
1578 #define  STM_TIM234_SMCR_ETF_DTS_16_N_8         12
1579 #define  STM_TIM234_SMCR_ETF_DTS_32_N_5         13
1580 #define  STM_TIM234_SMCR_ETF_DTS_32_N_6         14
1581 #define  STM_TIM234_SMCR_ETF_DTS_32_N_8         15
1582 #define  STM_TIM234_SMCR_ETF_MASK               15UL
1583 #define STM_TIM234_SMCR_MSM     7
1584 #define STM_TIM234_SMCR_TS      4
1585 #define  STM_TIM234_SMCR_TS_ITR0                0
1586 #define  STM_TIM234_SMCR_TS_ITR1                1
1587 #define  STM_TIM234_SMCR_TS_ITR2                2
1588 #define  STM_TIM234_SMCR_TS_ITR3                3
1589 #define  STM_TIM234_SMCR_TS_TI1F_ED             4
1590 #define  STM_TIM234_SMCR_TS_TI1FP1              5
1591 #define  STM_TIM234_SMCR_TS_TI2FP2              6
1592 #define  STM_TIM234_SMCR_TS_ETRF                7
1593 #define  STM_TIM234_SMCR_TS_MASK                7UL
1594 #define STM_TIM234_SMCR_SMS     0
1595 #define  STM_TIM234_SMCR_SMS_DISABLE            0
1596 #define  STM_TIM234_SMCR_SMS_ENCODER_MODE_1     1
1597 #define  STM_TIM234_SMCR_SMS_ENCODER_MODE_2     2
1598 #define  STM_TIM234_SMCR_SMS_ENCODER_MODE_3     3
1599 #define  STM_TIM234_SMCR_SMS_RESET_MODE         4
1600 #define  STM_TIM234_SMCR_SMS_GATED_MODE         5
1601 #define  STM_TIM234_SMCR_SMS_TRIGGER_MODE       6
1602 #define  STM_TIM234_SMCR_SMS_EXTERNAL_CLOCK     7
1603 #define  STM_TIM234_SMCR_SMS_MASK               7UL
1604
1605 #define STM_TIM234_DIER_TDE             14
1606 #define STM_TIM234_DIER_CC4DE           12
1607 #define STM_TIM234_DIER_CC3DE           11
1608 #define STM_TIM234_DIER_CC2DE           10
1609 #define STM_TIM234_DIER_CC1DE           9
1610 #define STM_TIM234_DIER_UDE             8
1611
1612 #define STM_TIM234_DIER_TIE             6
1613 #define STM_TIM234_DIER_CC4IE           4
1614 #define STM_TIM234_DIER_CC3IE           3
1615 #define STM_TIM234_DIER_CC2IE           2
1616 #define STM_TIM234_DIER_CC1IE           1
1617 #define STM_TIM234_DIER_UIE             0
1618
1619 #define STM_TIM234_SR_CC4OF     12
1620 #define STM_TIM234_SR_CC3OF     11
1621 #define STM_TIM234_SR_CC2OF     10
1622 #define STM_TIM234_SR_CC1OF     9
1623 #define STM_TIM234_SR_TIF       6
1624 #define STM_TIM234_SR_CC4IF     4
1625 #define STM_TIM234_SR_CC3IF     3
1626 #define STM_TIM234_SR_CC2IF     2
1627 #define STM_TIM234_SR_CC1IF     1
1628 #define STM_TIM234_SR_UIF       0
1629
1630 #define STM_TIM234_EGR_TG       6
1631 #define STM_TIM234_EGR_CC4G     4
1632 #define STM_TIM234_EGR_CC3G     3
1633 #define STM_TIM234_EGR_CC2G     2
1634 #define STM_TIM234_EGR_CC1G     1
1635 #define STM_TIM234_EGR_UG       0
1636
1637 #define STM_TIM234_CCMR1_OC2CE  15
1638 #define STM_TIM234_CCMR1_OC2M   12
1639 #define  STM_TIM234_CCMR1_OC2M_FROZEN                   0
1640 #define  STM_TIM234_CCMR1_OC2M_SET_HIGH_ON_MATCH        1
1641 #define  STM_TIM234_CCMR1_OC2M_SET_LOW_ON_MATCH         2
1642 #define  STM_TIM234_CCMR1_OC2M_TOGGLE                   3
1643 #define  STM_TIM234_CCMR1_OC2M_FORCE_LOW                4
1644 #define  STM_TIM234_CCMR1_OC2M_FORCE_HIGH               5
1645 #define  STM_TIM234_CCMR1_OC2M_PWM_MODE_1               6
1646 #define  STM_TIM234_CCMR1_OC2M_PWM_MODE_2               7
1647 #define  STM_TIM234_CCMR1_OC2M_MASK                     7UL
1648 #define STM_TIM234_CCMR1_OC2PE  11
1649 #define STM_TIM234_CCMR1_OC2FE  10
1650 #define STM_TIM234_CCMR1_CC2S   8
1651 #define  STM_TIM234_CCMR1_CC2S_OUTPUT                   0
1652 #define  STM_TIM234_CCMR1_CC2S_INPUT_TI2                1
1653 #define  STM_TIM234_CCMR1_CC2S_INPUT_TI1                2
1654 #define  STM_TIM234_CCMR1_CC2S_INPUT_TRC                3
1655 #define  STM_TIM234_CCMR1_CC2S_MASK                     3UL
1656
1657 #define STM_TIM234_CCMR1_OC1CE  7
1658 #define STM_TIM234_CCMR1_OC1M   4
1659 #define  STM_TIM234_CCMR1_OC1M_FROZEN                   0
1660 #define  STM_TIM234_CCMR1_OC1M_SET_HIGH_ON_MATCH        1
1661 #define  STM_TIM234_CCMR1_OC1M_SET_LOW_ON_MATCH         2
1662 #define  STM_TIM234_CCMR1_OC1M_TOGGLE                   3
1663 #define  STM_TIM234_CCMR1_OC1M_FORCE_LOW                4
1664 #define  STM_TIM234_CCMR1_OC1M_FORCE_HIGH               5
1665 #define  STM_TIM234_CCMR1_OC1M_PWM_MODE_1               6
1666 #define  STM_TIM234_CCMR1_OC1M_PWM_MODE_2               7
1667 #define  STM_TIM234_CCMR1_OC1M_MASK                     7UL
1668 #define STM_TIM234_CCMR1_OC1PE  3
1669 #define STM_TIM234_CCMR1_OC1FE  2
1670 #define STM_TIM234_CCMR1_CC1S   0
1671 #define  STM_TIM234_CCMR1_CC1S_OUTPUT                   0
1672 #define  STM_TIM234_CCMR1_CC1S_INPUT_TI1                1
1673 #define  STM_TIM234_CCMR1_CC1S_INPUT_TI2                2
1674 #define  STM_TIM234_CCMR1_CC1S_INPUT_TRC                3
1675 #define  STM_TIM234_CCMR1_CC1S_MASK                     3UL
1676
1677 #define STM_TIM234_CCMR1_IC2F   12
1678 #define  STM_TIM234_CCMR1_IC2F_NONE                     0
1679 #define  STM_TIM234_CCMR1_IC2F_CK_INT_N_2               1
1680 #define  STM_TIM234_CCMR1_IC2F_CK_INT_N_4               2
1681 #define  STM_TIM234_CCMR1_IC2F_CK_INT_N_8               3
1682 #define  STM_TIM234_CCMR1_IC2F_DTS_2_N_6                4
1683 #define  STM_TIM234_CCMR1_IC2F_DTS_2_N_8                5
1684 #define  STM_TIM234_CCMR1_IC2F_DTS_4_N_6                6
1685 #define  STM_TIM234_CCMR1_IC2F_DTS_4_N_8                7
1686 #define  STM_TIM234_CCMR1_IC2F_DTS_8_N_6                8
1687 #define  STM_TIM234_CCMR1_IC2F_DTS_8_N_8                9
1688 #define  STM_TIM234_CCMR1_IC2F_DTS_16_N_5               10
1689 #define  STM_TIM234_CCMR1_IC2F_DTS_16_N_6               11
1690 #define  STM_TIM234_CCMR1_IC2F_DTS_16_N_8               12
1691 #define  STM_TIM234_CCMR1_IC2F_DTS_32_N_5               13
1692 #define  STM_TIM234_CCMR1_IC2F_DTS_32_N_6               14
1693 #define  STM_TIM234_CCMR1_IC2F_DTS_32_N_8               15
1694 #define STM_TIM234_CCMR1_IC2PSC 10
1695 #define  STM_TIM234_CCMR1_IC2PSC_NONE                   0
1696 #define  STM_TIM234_CCMR1_IC2PSC_2                      1
1697 #define  STM_TIM234_CCMR1_IC2PSC_4                      2
1698 #define  STM_TIM234_CCMR1_IC2PSC_8                      3
1699 #define STM_TIM234_CCMR1_IC1F   4
1700 #define  STM_TIM234_CCMR1_IC1F_NONE                     0
1701 #define  STM_TIM234_CCMR1_IC1F_CK_INT_N_2               1
1702 #define  STM_TIM234_CCMR1_IC1F_CK_INT_N_4               2
1703 #define  STM_TIM234_CCMR1_IC1F_CK_INT_N_8               3
1704 #define  STM_TIM234_CCMR1_IC1F_DTS_2_N_6                4
1705 #define  STM_TIM234_CCMR1_IC1F_DTS_2_N_8                5
1706 #define  STM_TIM234_CCMR1_IC1F_DTS_4_N_6                6
1707 #define  STM_TIM234_CCMR1_IC1F_DTS_4_N_8                7
1708 #define  STM_TIM234_CCMR1_IC1F_DTS_8_N_6                8
1709 #define  STM_TIM234_CCMR1_IC1F_DTS_8_N_8                9
1710 #define  STM_TIM234_CCMR1_IC1F_DTS_16_N_5               10
1711 #define  STM_TIM234_CCMR1_IC1F_DTS_16_N_6               11
1712 #define  STM_TIM234_CCMR1_IC1F_DTS_16_N_8               12
1713 #define  STM_TIM234_CCMR1_IC1F_DTS_32_N_5               13
1714 #define  STM_TIM234_CCMR1_IC1F_DTS_32_N_6               14
1715 #define  STM_TIM234_CCMR1_IC1F_DTS_32_N_8               15
1716 #define STM_TIM234_CCMR1_IC1PSC 2
1717 #define  STM_TIM234_CCMR1_IC1PSC_NONE                   0
1718 #define  STM_TIM234_CCMR1_IC1PSC_2                      1
1719 #define  STM_TIM234_CCMR1_IC1PSC_4                      2
1720 #define  STM_TIM234_CCMR1_IC1PSC_8                      3
1721
1722 #define STM_TIM234_CCMR2_OC4CE  15
1723 #define STM_TIM234_CCMR2_OC4M   12
1724 #define  STM_TIM234_CCMR2_OC4M_FROZEN                   0
1725 #define  STM_TIM234_CCMR2_OC4M_SET_HIGH_ON_MATCH        1
1726 #define  STM_TIM234_CCMR2_OC4M_SET_LOW_ON_MATCH         2
1727 #define  STM_TIM234_CCMR2_OC4M_TOGGLE                   3
1728 #define  STM_TIM234_CCMR2_OC4M_FORCE_LOW                4
1729 #define  STM_TIM234_CCMR2_OC4M_FORCE_HIGH               5
1730 #define  STM_TIM234_CCMR2_OC4M_PWM_MODE_1               6
1731 #define  STM_TIM234_CCMR2_OC4M_PWM_MODE_2               7
1732 #define  STM_TIM234_CCMR2_OC4M_MASK                     7UL
1733 #define STM_TIM234_CCMR2_OC4PE  11
1734 #define STM_TIM234_CCMR2_OC4FE  10
1735 #define STM_TIM234_CCMR2_CC4S   8
1736 #define  STM_TIM234_CCMR2_CC4S_OUTPUT                   0
1737 #define  STM_TIM234_CCMR2_CC4S_INPUT_TI4                1
1738 #define  STM_TIM234_CCMR2_CC4S_INPUT_TI3                2
1739 #define  STM_TIM234_CCMR2_CC4S_INPUT_TRC                3
1740 #define  STM_TIM234_CCMR2_CC4S_MASK                     3UL
1741
1742 #define STM_TIM234_CCMR2_OC3CE  7
1743 #define STM_TIM234_CCMR2_OC3M   4
1744 #define  STM_TIM234_CCMR2_OC3M_FROZEN                   0
1745 #define  STM_TIM234_CCMR2_OC3M_SET_HIGH_ON_MATCH        1
1746 #define  STM_TIM234_CCMR2_OC3M_SET_LOW_ON_MATCH         2
1747 #define  STM_TIM234_CCMR2_OC3M_TOGGLE                   3
1748 #define  STM_TIM234_CCMR2_OC3M_FORCE_LOW                4
1749 #define  STM_TIM234_CCMR2_OC3M_FORCE_HIGH               5
1750 #define  STM_TIM234_CCMR2_OC3M_PWM_MODE_1               6
1751 #define  STM_TIM234_CCMR2_OC3M_PWM_MODE_2               7
1752 #define  STM_TIM234_CCMR2_OC3M_MASK                     7UL
1753 #define STM_TIM234_CCMR2_OC3PE  3
1754 #define STM_TIM234_CCMR2_OC3FE  2
1755 #define STM_TIM234_CCMR2_CC3S   0
1756 #define  STM_TIM234_CCMR2_CC3S_OUTPUT                   0
1757 #define  STM_TIM234_CCMR2_CC3S_INPUT_TI3                1
1758 #define  STM_TIM234_CCMR2_CC3S_INPUT_TI4                2
1759 #define  STM_TIM234_CCMR2_CC3S_INPUT_TRC                3
1760 #define  STM_TIM234_CCMR2_CC3S_MASK                     3UL
1761
1762 #define STM_TIM234_CCER_CC4NP   15
1763 #define STM_TIM234_CCER_CC4P    13
1764 #define  STM_TIM234_CCER_CC4P_ACTIVE_HIGH       0
1765 #define  STM_TIM234_CCER_CC4P_ACTIVE_LOW        1
1766 #define STM_TIM234_CCER_CC4E    12
1767 #define STM_TIM234_CCER_CC3NP   11
1768 #define STM_TIM234_CCER_CC3P    9
1769 #define  STM_TIM234_CCER_CC3P_ACTIVE_HIGH       0
1770 #define  STM_TIM234_CCER_CC3P_ACTIVE_LOW        1
1771 #define STM_TIM234_CCER_CC3E    8
1772 #define STM_TIM234_CCER_CC2NP   7
1773 #define STM_TIM234_CCER_CC2P    5
1774 #define  STM_TIM234_CCER_CC2P_ACTIVE_HIGH       0
1775 #define  STM_TIM234_CCER_CC2P_ACTIVE_LOW        1
1776 #define STM_TIM234_CCER_CC2E    4
1777 #define STM_TIM234_CCER_CC1NP   3
1778 #define STM_TIM234_CCER_CC1P    1
1779 #define  STM_TIM234_CCER_CC1P_ACTIVE_HIGH       0
1780 #define  STM_TIM234_CCER_CC1P_ACTIVE_LOW        1
1781 #define STM_TIM234_CCER_CC1E    0
1782
1783 struct stm_tim67 {
1784         vuint32_t       cr1;
1785         vuint32_t       cr2;
1786         uint32_t        _unused_08;
1787         vuint32_t       dier;
1788
1789         vuint32_t       sr;
1790         vuint32_t       egr;
1791         uint32_t        _unused_18;
1792         uint32_t        _unused_1c;
1793
1794         uint32_t        _unused_20;
1795         vuint32_t       cnt;
1796         vuint32_t       psc;
1797         vuint32_t       arr;
1798 };
1799
1800 extern struct stm_tim67 stm_tim6;
1801
1802 #define STM_TIM67_CR1_ARPE      (7)
1803 #define STM_TIM67_CR1_OPM       (3)
1804 #define STM_TIM67_CR1_URS       (2)
1805 #define STM_TIM67_CR1_UDIS      (1)
1806 #define STM_TIM67_CR1_CEN       (0)
1807
1808 #define STM_TIM67_CR2_MMS       (4)
1809 #define  STM_TIM67_CR2_MMS_RESET        0
1810 #define  STM_TIM67_CR2_MMS_ENABLE       1
1811 #define  STM_TIM67_CR2_MMS_UPDATE       2
1812 #define  STM_TIM67_CR2_MMS_MASK         7UL
1813
1814 #define STM_TIM67_DIER_UDE      (8)
1815 #define STM_TIM67_DIER_UIE      (0)
1816
1817 #define STM_TIM67_SR_UIF        (0)
1818
1819 #define STM_TIM67_EGR_UG        (0)
1820
1821 #define isr_decl(name) void stm_ ## name ## _isr(void)
1822
1823 isr_decl(halt);
1824 isr_decl(ignore);
1825
1826 isr_decl(nmi);
1827 isr_decl(hardfault);
1828 isr_decl(memmanage);
1829 isr_decl(busfault);
1830 isr_decl(usagefault);
1831 isr_decl(svc);
1832 isr_decl(debugmon);
1833 isr_decl(pendsv);
1834 isr_decl(systick);
1835 isr_decl(wwdg);
1836 isr_decl(pvd);
1837 isr_decl(tamper_stamp);
1838 isr_decl(rtc_wkup);
1839 isr_decl(flash);
1840 isr_decl(rcc);
1841 isr_decl(exti0);
1842 isr_decl(exti1);
1843 isr_decl(exti2);
1844 isr_decl(exti3);
1845 isr_decl(exti4);
1846 isr_decl(dma1_channel1);
1847 isr_decl(dma1_channel2);
1848 isr_decl(dma1_channel3);
1849 isr_decl(dma1_channel4);
1850 isr_decl(dma1_channel5);
1851 isr_decl(dma1_channel6);
1852 isr_decl(dma1_channel7);
1853 isr_decl(adc1_2);
1854 isr_decl(usb_hp);
1855 isr_decl(usb_lp);
1856 isr_decl(can_rx1);
1857 isr_decl(can_sce);
1858 isr_decl(exti9_5);
1859 isr_decl(tim1_brk);
1860 isr_decl(tim1_up);
1861 isr_decl(tim1_trg_com);
1862 isr_decl(tim1_cc);
1863 isr_decl(tim2);
1864 isr_decl(tim3);
1865 isr_decl(tim4);
1866 isr_decl(i2c1_ev);
1867 isr_decl(i2c1_er);
1868 isr_decl(i2c2_ev);
1869 isr_decl(i2c2_er);
1870 isr_decl(spi1);
1871 isr_decl(spi2);
1872 isr_decl(usart1);
1873 isr_decl(usart2);
1874 isr_decl(usart3);
1875 isr_decl(exti15_10);
1876 isr_decl(rtc_alarm);
1877 isr_decl(usb_wakeup);
1878 isr_decl(tim8_brk);
1879 isr_decl(tim8_up);
1880 isr_decl(tim8_trg_com);
1881 isr_decl(tim8_cc);
1882 isr_decl(adc3);
1883 isr_decl(fsmc);
1884 isr_decl(sdio);
1885 isr_decl(tim5);
1886 isr_decl(spi3);
1887 isr_decl(uart4);
1888 isr_decl(uart5);
1889 isr_decl(tim6);
1890 isr_decl(tim7);
1891 isr_decl(dma2_channel1);
1892 isr_decl(dma2_channel2);
1893 isr_decl(dma2_channel3);
1894 isr_decl(dma2_channel4_5);
1895
1896 #undef isr_decl
1897
1898 #define STM_ISR_WWDG_POS                0
1899 #define STM_ISR_PVD_POS                 1
1900 #define STM_ISR_TAMPER_STAMP_POS        2
1901 #define STM_ISR_RTC_WKUP_POS            3
1902 #define STM_ISR_FLASH_POS               4
1903 #define STM_ISR_RCC_POS                 5
1904 #define STM_ISR_EXTI0_POS               6
1905 #define STM_ISR_EXTI1_POS               7
1906 #define STM_ISR_EXTI2_POS               8
1907 #define STM_ISR_EXTI3_POS               9
1908 #define STM_ISR_EXTI4_POS               10
1909 #define STM_ISR_DMA1_CHANNEL1_POS       11
1910 #define STM_ISR_DMA1_CHANNEL2_POS       12
1911 #define STM_ISR_DMA1_CHANNEL3_POS       13
1912 #define STM_ISR_DMA1_CHANNEL4_POS       14
1913 #define STM_ISR_DMA1_CHANNEL5_POS       15
1914 #define STM_ISR_DMA1_CHANNEL6_POS       16
1915 #define STM_ISR_DMA1_CHANNEL7_POS       17
1916 #define STM_ISR_ADC1_2_POS              18
1917 #define STM_ISR_USB_HP_POS              19
1918 #define STM_ISR_USB_LP_POS              20
1919 #define STM_ISR_CAN_RX1_POS             21
1920 #define STM_ISR_CAN_SCE_POS             22
1921 #define STM_ISR_EXTI9_5_POS             23
1922 #define STM_ISR_TIM1_BRK_POS            24
1923 #define STM_ISR_TIM1_UP_POS             25
1924 #define STM_ISR_TIM1_TRG_COM_POS        26
1925 #define STM_ISR_TIM1_CC_POS             27
1926 #define STM_ISR_TIM2_POS                28
1927 #define STM_ISR_TIM3_POS                29
1928 #define STM_ISR_TIM4_POS                30
1929 #define STM_ISR_I2C1_EV_POS             31
1930 #define STM_ISR_I2C1_ER_POS             32
1931 #define STM_ISR_I2C2_EV_POS             33
1932 #define STM_ISR_I2C2_ER_POS             34
1933 #define STM_ISR_SPI1_POS                35
1934 #define STM_ISR_SPI2_POS                36
1935 #define STM_ISR_USART1_POS              37
1936 #define STM_ISR_USART2_POS              38
1937 #define STM_ISR_USART3_POS              39
1938 #define STM_ISR_EXTI15_10_POS           40
1939 #define STM_ISR_RTC_ALARM_POS           41
1940 #define STM_ISR_USB_WAKEUP_POS          42
1941 #define STM_ISR_TIM8_BRK_POS            43
1942 #define STM_ISR_TIM8_UP_POS             44
1943 #define STM_ISR_TIM8_TRG_COM_POS        45
1944 #define STM_ISR_TIM8_CC_POS             46
1945 #define STM_ISR_ADC3_POS                47
1946 #define STM_ISR_FSMC_POS                48
1947 #define STM_ISR_SDIO_POS                49
1948 #define STM_ISR_TIM5_POS                50
1949 #define STM_ISR_SPI3_POS                51
1950 #define STM_ISR_UART4_POS               52
1951 #define STM_ISR_UART5_POS               53
1952 #define STM_ISR_TIM6_POS                54
1953 #define STM_ISR_TIM7_POS                55
1954 #define STM_ISR_DMA2_CHANNEL1_POS       56
1955 #define STM_ISR_DMA2_CHANNEL2_POS       57
1956 #define STM_ISR_DMA2_CHANNEL3_POS       58
1957 #define STM_ISR_DMA3_CHANNEL4_5_POS     59
1958
1959 #endif