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   1 /*
   2  * Copyright © 2012 Keith Packard <keithp@keithp.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful, but
  10  * WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  12  * General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along
  15  * with this program; if not, write to the Free Software Foundation, Inc.,
  16  * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  17  */
  18
  19 #include <ao.h>
  20
  21 struct ao_i2c_stm_info {
  22         uint8_t tx_dma_index;
  23         uint8_t rx_dma_index;
  24         struct stm_i2c  *stm_i2c;
  25 };
  26
  27 #define I2C_FAST        1
  28
  29 #define I2C_TIMEOUT     100
  30
  31 #define I2C_IDLE        0
  32 #define I2C_RUNNING     1
  33 #define I2C_ERROR       2
  34
  35 static uint8_t  ao_i2c_state[STM_NUM_I2C];
  36 static uint16_t ao_i2c_addr[STM_NUM_I2C];
  37 uint8_t         ao_i2c_mutex[STM_NUM_I2C];
  38
  39 # define I2C_HIGH_SLOW  5000    /* ns, 100kHz clock */
  40 #ifdef TELEMEGA
  41 # define I2C_HIGH_FAST  2000    /* ns, 167kHz clock */
  42 #else
  43 # define I2C_HIGH_FAST  1000    /* ns, 333kHz clock */
  44 #endif
  45
  46 # define I2C_RISE_SLOW  500     /* ns */
  47 # define I2C_RISE_FAST  100     /* ns */
  48
  49 /* Clock period in ns */
  50 #define CYCLES(period)  (((period) * (AO_PCLK1 / 1000)) / 1000000)
  51
  52 #define max(a,b)        ((a) > (b) ? (a) : (b))
  53 #define I2C_CCR_HIGH_SLOW       max(4,CYCLES(I2C_HIGH_SLOW))
  54 #define I2C_CCR_HIGH_FAST       max(4,CYCLES(I2C_HIGH_FAST))
  55 #define I2C_TRISE_SLOW          (CYCLES(I2C_RISE_SLOW) + 1)
  56 #define I2C_TRISE_FAST          (CYCLES(I2C_RISE_FAST) + 1)
  57
  58 #if I2C_FAST
  59 #define I2C_TRISE       I2C_TRISE_FAST
  60 #define I2C_CCR_HIGH    I2C_CCR_HIGH_FAST
  61 #else
  62 #define I2C_TRISE       I2C_TRISE_SLOW
  63 #define I2C_CCR_HIGH    I2C_CCR_HIGH_SLOW
  64 #endif
  65
  66 #define AO_STM_I2C_CR2_FREQ     (AO_APB1CLK / 1000000)
  67
  68 #define AO_STM_I2C_CR1 ((0 << STM_I2C_CR1_SWRST) |      \
  69                         (0 << STM_I2C_CR1_ALERT) |      \
  70                         (0 << STM_I2C_CR1_PEC) |        \
  71                         (0 << STM_I2C_CR1_POS) |        \
  72                         (0 << STM_I2C_CR1_ACK) |        \
  73                         (0 << STM_I2C_CR1_STOP) |       \
  74                         (0 << STM_I2C_CR1_START) |      \
  75                         (0 << STM_I2C_CR1_NOSTRETCH) |  \
  76                         (0 << STM_I2C_CR1_ENGC) |       \
  77                         (0 << STM_I2C_CR1_ENPEC) |      \
  78                         (0 << STM_I2C_CR1_ENARP) |      \
  79                         (0 << STM_I2C_CR1_SMBTYPE) |    \
  80                         (0 << STM_I2C_CR1_SMBUS) |      \
  81                         (1 << STM_I2C_CR1_PE))
  82
  83 #define AO_STM_I2C_CR2  ((0 << STM_I2C_CR2_LAST) |                      \
  84                          (0 << STM_I2C_CR2_DMAEN) |                     \
  85                          (0 << STM_I2C_CR2_ITBUFEN) |                   \
  86                          (0 << STM_I2C_CR2_ITEVTEN) |                   \
  87                          (0 << STM_I2C_CR2_ITERREN) |                   \
  88                          (AO_STM_I2C_CR2_FREQ << STM_I2C_CR2_FREQ))
  89
  90 static const struct ao_i2c_stm_info     ao_i2c_stm_info[STM_NUM_I2C] = {
  91         {
  92                 .tx_dma_index = STM_DMA_INDEX(STM_DMA_CHANNEL_I2C1_TX),
  93                 .rx_dma_index = STM_DMA_INDEX(STM_DMA_CHANNEL_I2C1_RX),
  94                 .stm_i2c = &stm_i2c1
  95         },
  96         {
  97                 .tx_dma_index = STM_DMA_INDEX(STM_DMA_CHANNEL_I2C2_TX),
  98                 .rx_dma_index = STM_DMA_INDEX(STM_DMA_CHANNEL_I2C2_RX),
  99                 .stm_i2c = &stm_i2c2
 100         },
 101 };
 102
 103 static uint8_t  *ao_i2c_recv_data[STM_NUM_I2C];
 104 static uint16_t ao_i2c_recv_len[STM_NUM_I2C];
 105 static uint16_t ev_count;
 106
 107 static void
 108 ao_i2c_ev_isr(uint8_t index)
 109 {
 110         struct stm_i2c  *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
 111         uint32_t        sr1;
 112
 113         ++ev_count;
 114         sr1 = stm_i2c->sr1;
 115         if (sr1 & (1 << STM_I2C_SR1_SB))
 116                 stm_i2c->dr = ao_i2c_addr[index];
 117         if (sr1 & (1 << STM_I2C_SR1_ADDR)) {
 118                 stm_i2c->cr2 &= ~(1UL << STM_I2C_CR2_ITEVTEN);
 119                 ao_i2c_state[index] = I2C_RUNNING;
 120                 ao_wakeup(&ao_i2c_state[index]);
 121         }
 122         if (sr1 & (1 << STM_I2C_SR1_BTF)) {
 123                 stm_i2c->cr2 &= ~(1UL << STM_I2C_CR2_ITEVTEN);
 124                 ao_wakeup(&ao_i2c_state[index]);
 125         }
 126         if (sr1 & (1 << STM_I2C_SR1_RXNE)) {
 127                 if (ao_i2c_recv_len[index]) {
 128                         *(ao_i2c_recv_data[index]++) = (uint8_t) stm_i2c->dr;
 129                         if (!--ao_i2c_recv_len[index])
 130                                 ao_wakeup(&ao_i2c_recv_len[index]);
 131                 }
 132         }
 133 }
 134
 135 void stm_i2c1_ev_isr(void) { ao_i2c_ev_isr(0); }
 136 void stm_i2c2_ev_isr(void) { ao_i2c_ev_isr(1); }
 137
 138 static void
 139 ao_i2c_er_isr(uint8_t index)
 140 {
 141         struct stm_i2c  *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
 142         uint32_t        sr1;
 143
 144         sr1 = stm_i2c->sr1;
 145         if (sr1 & (1 << STM_I2C_SR1_AF)) {
 146                 ao_i2c_state[index] = I2C_ERROR;
 147                 stm_i2c->sr1 = sr1 & ~(1UL << STM_I2C_SR1_AF);
 148                 ao_wakeup(&ao_i2c_state[index]);
 149         }
 150 }
 151
 152 void stm_i2c1_er_isr(void) { ao_i2c_er_isr(0); }
 153 void stm_i2c2_er_isr(void) { ao_i2c_er_isr(1); }
 154
 155 void
 156 ao_i2c_get(uint8_t index)
 157 {
 158         struct stm_i2c  *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
 159         ao_mutex_get(&ao_i2c_mutex[index]);
 160
 161         stm_i2c->sr1 = 0;
 162         stm_i2c->sr2 = 0;
 163 }
 164
 165 void
 166 ao_i2c_put(uint8_t index)
 167 {
 168         ao_mutex_put(&ao_i2c_mutex[index]);
 169 }
 170
 171 uint8_t
 172 ao_i2c_start(uint8_t index, uint16_t addr)
 173 {
 174         struct stm_i2c  *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
 175         int             t;
 176
 177         ao_i2c_state[index] = I2C_IDLE;
 178         ao_i2c_addr[index] = addr;
 179         stm_i2c->cr2 = AO_STM_I2C_CR2;
 180         stm_i2c->cr1 = AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_START);
 181         for (t = 0; t < I2C_TIMEOUT; t++) {
 182                 if (!(stm_i2c->cr1 & (1 << STM_I2C_CR1_START)))
 183                         break;
 184         }
 185         ao_arch_block_interrupts();
 186         stm_i2c->cr2 = AO_STM_I2C_CR2 | (1 << STM_I2C_CR2_ITEVTEN) | (1 << STM_I2C_CR2_ITERREN);
 187         ao_i2c_ev_isr(index);
 188         while (ao_i2c_state[index] == I2C_IDLE)
 189                 if (ao_sleep_for(&ao_i2c_state[index], AO_MS_TO_TICKS(250)))
 190                         break;
 191         ao_arch_release_interrupts();
 192         return ao_i2c_state[index] == I2C_RUNNING;
 193 }
 194
 195 static void
 196 ao_i2c_wait_stop(uint8_t index)
 197 {
 198         struct stm_i2c  *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
 199         int     t;
 200
 201         for (t = 0; t < I2C_TIMEOUT; t++) {
 202                 if (!(stm_i2c->cr1 & (1 << STM_I2C_CR1_STOP)))
 203                         break;
 204                 ao_yield();
 205         }
 206         ao_i2c_state[index] = I2C_IDLE;
 207 }
 208
 209 static void
 210 ao_i2c_wait_addr(uint8_t index)
 211 {
 212         struct stm_i2c  *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
 213         int     t;
 214
 215         for (t = 0; t < I2C_TIMEOUT; t++)
 216                 if (!(stm_i2c->sr1 & (1 << STM_I2C_SR1_ADDR)))
 217                         break;
 218         if (t)
 219                 printf ("wait_addr %d\n", t);
 220 }
 221
 222 uint8_t
 223 ao_i2c_send(void *block, uint16_t len, uint8_t index, uint8_t stop)
 224 {
 225         struct stm_i2c  *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
 226         uint8_t         tx_dma_index = ao_i2c_stm_info[index].tx_dma_index;
 227
 228         /* Clear any pending ADDR bit */
 229         (void) stm_i2c->sr2;
 230         ao_i2c_wait_addr(index);
 231         stm_i2c->cr2 = AO_STM_I2C_CR2 | (1 << STM_I2C_CR2_DMAEN);
 232         ao_dma_set_transfer(tx_dma_index,
 233                             &stm_i2c->dr,
 234                             block,
 235                             len,
 236                             (0 << STM_DMA_CCR_MEM2MEM) |
 237                             (STM_DMA_CCR_PL_MEDIUM << STM_DMA_CCR_PL) |
 238                             (STM_DMA_CCR_MSIZE_8 << STM_DMA_CCR_MSIZE) |
 239                             (STM_DMA_CCR_PSIZE_8 << STM_DMA_CCR_PSIZE) |
 240                             (1 << STM_DMA_CCR_MINC) |
 241                             (0 << STM_DMA_CCR_PINC) |
 242                             (0 << STM_DMA_CCR_CIRC) |
 243                             (STM_DMA_CCR_DIR_MEM_TO_PER << STM_DMA_CCR_DIR));
 244
 245         ao_dma_start(tx_dma_index);
 246         ao_arch_block_interrupts();
 247         while (!ao_dma_done[tx_dma_index])
 248                 if (ao_sleep_for(&ao_dma_done[tx_dma_index], 1 + len))
 249                         break;
 250         ao_dma_done_transfer(tx_dma_index);
 251         stm_i2c->cr2 = AO_STM_I2C_CR2 | (1 << STM_I2C_CR2_ITEVTEN) | (1 << STM_I2C_CR2_ITERREN);
 252         while ((stm_i2c->sr1 & (1 << STM_I2C_SR1_BTF)) == 0)
 253                 if (ao_sleep_for(&ao_i2c_state[index], 1 + len))
 254                         break;
 255         stm_i2c->cr2 = AO_STM_I2C_CR2;
 256         ao_arch_release_interrupts();
 257         if (stop) {
 258                 stm_i2c->cr1 = AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_STOP);
 259                 ao_i2c_wait_stop(index);
 260         }
 261         return true;
 262 }
 263
 264 static void
 265 ao_i2c_recv_dma_isr(int index)
 266 {
 267         int             i;
 268         struct stm_i2c  *stm_i2c = NULL;
 269
 270         for (i = 0; i < STM_NUM_I2C; i++)
 271                 if (index == ao_i2c_stm_info[i].rx_dma_index) {
 272                         stm_i2c = ao_i2c_stm_info[i].stm_i2c;
 273                         break;
 274                 }
 275         if (!stm_i2c)
 276                 return;
 277         stm_i2c->cr2 = AO_STM_I2C_CR2 | (1 << STM_I2C_CR2_LAST);
 278         ao_dma_done[index] = 1;
 279         ao_wakeup(&ao_dma_done[index]);
 280 }
 281
 282 uint8_t
 283 ao_i2c_recv(void *block, uint16_t len, uint8_t index, uint8_t stop)
 284 {
 285         struct stm_i2c  *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
 286         uint8_t         ret = true;
 287
 288         if (len == 0)
 289                 return true;
 290         if (len == 1) {
 291                 ao_i2c_recv_data[index] = block;
 292                 ao_i2c_recv_len[index] = 1;
 293                 stm_i2c->cr1 = AO_STM_I2C_CR1;
 294
 295                 /* Clear any pending ADDR bit */
 296                 stm_i2c->sr2;
 297                 ao_i2c_wait_addr(index);
 298
 299                 /* Enable interrupts to transfer the byte */
 300                 stm_i2c->cr2 = (AO_STM_I2C_CR2 |
 301                                 (1 << STM_I2C_CR2_ITEVTEN) |
 302                                 (1 << STM_I2C_CR2_ITERREN) |
 303                                 (1 << STM_I2C_CR2_ITBUFEN));
 304                 if (stop)
 305                         stm_i2c->cr1 = AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_STOP);
 306
 307                 ao_arch_block_interrupts();
 308                 while (ao_i2c_recv_len[index])
 309                         if (ao_sleep_for(&ao_i2c_recv_len[index], 1))
 310                                 break;
 311                 ao_arch_release_interrupts();
 312                 ret = ao_i2c_recv_len[index] == 0;
 313         } else {
 314                 uint8_t         rx_dma_index = ao_i2c_stm_info[index].rx_dma_index;
 315                 ao_dma_set_transfer(rx_dma_index,
 316                                     &stm_i2c->dr,
 317                                     block,
 318                                     len,
 319                                     (0 << STM_DMA_CCR_MEM2MEM) |
 320                                     (STM_DMA_CCR_PL_HIGH << STM_DMA_CCR_PL) |
 321                                     (STM_DMA_CCR_MSIZE_8 << STM_DMA_CCR_MSIZE) |
 322                                     (STM_DMA_CCR_PSIZE_8 << STM_DMA_CCR_PSIZE) |
 323                                     (1 << STM_DMA_CCR_MINC) |
 324                                     (0 << STM_DMA_CCR_PINC) |
 325                                     (0 << STM_DMA_CCR_CIRC) |
 326                                     (STM_DMA_CCR_DIR_PER_TO_MEM << STM_DMA_CCR_DIR));
 327
 328                 /* XXX ao_i2c_recv_dma_isr hasn't ever been used, so it
 329                  * doesn't appear to be necessary. Testing with a device
 330                  * that uses i2c would really be useful here to discover
 331                  * whether this function is necessary or not.
 332                  */
 333 #if 0
 334                 ao_dma_set_isr(rx_dma_index, ao_i2c_recv_dma_isr);
 335 #else
 336                 (void) ao_i2c_recv_dma_isr;
 337 #endif
 338                 stm_i2c->cr1 = AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_ACK);
 339                 stm_i2c->cr2 = AO_STM_I2C_CR2 |
 340                         (1 << STM_I2C_CR2_DMAEN) | (1 << STM_I2C_CR2_LAST);
 341                 /* Clear any pending ADDR bit */
 342                 (void) stm_i2c->sr2;
 343                 ao_i2c_wait_addr(index);
 344
 345                 ao_dma_start(rx_dma_index);
 346                 ao_arch_block_interrupts();
 347                 while (!ao_dma_done[rx_dma_index])
 348                         if (ao_sleep_for(&ao_dma_done[rx_dma_index], len))
 349                                 break;
 350                 ao_arch_release_interrupts();
 351                 ret = ao_dma_done[rx_dma_index];
 352                 ao_dma_done_transfer(rx_dma_index);
 353                 stm_i2c->cr1 = AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_STOP);
 354         }
 355         if (stop)
 356                 ao_i2c_wait_stop(index);
 357         return ret;
 358 }
 359
 360 static void
 361 ao_i2c_channel_init(uint8_t index)
 362 {
 363         struct stm_i2c  *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
 364         int i;
 365
 366         /* Turn I2C off while configuring */
 367         stm_i2c->cr1 = (1 << STM_I2C_CR1_SWRST);
 368         for (i = 0; i < 100; i++)
 369                 asm("nop");
 370         stm_i2c->cr1 = 0;
 371         stm_i2c->cr2 = AO_STM_I2C_CR2;
 372
 373         (void) stm_i2c->sr1;
 374         (void) stm_i2c->sr2;
 375         (void) stm_i2c->dr;
 376
 377         stm_i2c->sr1 = 0;
 378         stm_i2c->sr2 = 0;
 379
 380         stm_i2c->ccr = ((I2C_FAST << STM_I2C_CCR_FS) |
 381                         (0 << STM_I2C_CCR_DUTY) |
 382                         (I2C_CCR_HIGH << STM_I2C_CCR_CCR));
 383
 384         stm_i2c->trise = I2C_TRISE;
 385
 386         stm_i2c->cr1 = AO_STM_I2C_CR1;
 387 }
 388
 389 static inline void
 390 i2c_pin_set(struct stm_gpio *gpio, int pin)
 391 {
 392         ao_enable_port(gpio);
 393         stm_gpio_conf(gpio, pin,
 394                       STM_GPIO_CR_MODE_OUTPUT_2MHZ,
 395                       STM_GPIO_CR_CNF_OUTPUT_AF_OPEN_DRAIN);
 396 }
 397
 398 void
 399 ao_i2c_init(void)
 400 {
 401 #if HAS_I2C_1
 402 # if I2C_1_PB6_PB7
 403         stm_set_afio_mapr(STM_AFIO_MAPR_I2C1_REMAP,
 404                           STM_AFIO_MAPR_I2C1_REMAP_PB6_PB7,
 405                           STM_AFIO_MAPR_I2C1_REMAP_MASK);
 406         i2c_pin_set(&stm_gpiob, 6);
 407         i2c_pin_set(&stm_gpiob, 7);
 408 # else
 409 #  if I2C_1_PB8_PB9
 410         stm_set_afio_mapr(STM_AFIO_MAPR_I2C1_REMAP,
 411                           STM_AFIO_MAPR_I2C1_REMAP_PB8_PB9,
 412                           STM_AFIO_MAPR_I2C1_REMAP_MASK);
 413         i2c_pin_set(&stm_gpiob, 8);
 414         i2c_pin_set(&stm_gpiob, 9);
 415 #  else
 416 #   error "No I2C_1 port configuration specified"
 417 #  endif
 418 # endif
 419
 420         stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_I2C1EN);
 421         ao_i2c_channel_init(0);
 422
 423         stm_nvic_set_enable(STM_ISR_I2C1_EV_POS);
 424         stm_nvic_set_priority(STM_ISR_I2C1_EV_POS, AO_STM_NVIC_MED_PRIORITY);
 425         stm_nvic_set_enable(STM_ISR_I2C1_ER_POS);
 426         stm_nvic_set_priority(STM_ISR_I2C1_ER_POS, AO_STM_NVIC_MED_PRIORITY);
 427 #endif
 428
 429 #if HAS_I2C_2
 430 # if I2C_2_PB10_PB11
 431         i2c_pin_set(&stm_gpiob, 10);
 432         i2c_pin_set(&stm_gpiob, 11);
 433 # else
 434 #  error "No I2C_2 port configuration specified"
 435 # endif
 436         stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_I2C2EN);
 437         ao_i2c_channel_init(1);
 438
 439         stm_nvic_set_enable(STM_ISR_I2C2_EV_POS);
 440         stm_nvic_set_priority(STM_ISR_I2C2_EV_POS, AO_STM_NVIC_MED_PRIORITY);
 441         stm_nvic_set_enable(STM_ISR_I2C2_ER_POS);
 442         stm_nvic_set_priority(STM_ISR_I2C2_ER_POS, AO_STM_NVIC_MED_PRIORITY);
 443 #endif
 444 }