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   1 /*
   2  * Copyright © 2024 Keith Packard <keithp@keithp.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful, but
  10  * WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  12  * General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along
  15  * with this program; if not, write to the Free Software Foundation, Inc.,
  16  * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  17  */
  18
  19 #include <ao.h>
  20 #include <ao_data.h>
  21 #include <ao_adc_single.h>
  22
  23 static uint8_t                  ao_adc_ready;
  24
  25 #define AO_ADC_CR2_VAL(start)   ((HAS_ADC_TEMP << STM_ADC_CR2_TSVREF) | \
  26                                  ((start) << STM_ADC_CR2_SWSTART) |     \
  27                                  (0 << STM_ADC_CR2_JWSTART) |           \
  28                                  (0 << STM_ADC_CR2_EXTTRIG) |           \
  29                                  (STM_ADC_CR2_EXTSEL_SWSTART << STM_ADC_CR2_EXTSEL) | \
  30                                  (0 << STM_ADC_CR2_JEXTTRIG) |          \
  31                                  (0 << STM_ADC_CR2_JEXTSEL) |           \
  32                                  (0 << STM_ADC_CR2_ALIGN) |             \
  33                                  (1 << STM_ADC_CR2_DMA) |               \
  34                                  (0 << STM_ADC_CR2_CONT) |              \
  35                                  (1 << STM_ADC_CR2_ADON))
  36
  37 /*
  38  * Callback from DMA ISR
  39  *
  40  * Shut down DMA engine, signal anyone waiting
  41  */
  42 static void ao_adc_done(int index)
  43 {
  44         (void) index;
  45         ao_dma_done_transfer(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1));
  46         ao_adc_ready = 1;
  47         /* Turn the ADC back off */
  48         stm_adc1.cr2 = 0;
  49         ao_wakeup((void *) &ao_adc_ready);
  50 }
  51
  52 /*
  53  * Start the ADC sequence using the DMA engine
  54  */
  55 static void
  56 ao_adc_poll(struct ao_adc *packet)
  57 {
  58         ao_adc_ready = 0;
  59         stm_adc1.sr = 0;
  60         ao_dma_set_transfer(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1),
  61                             &stm_adc1.dr,
  62                             (void *) packet,
  63                             AO_NUM_ADC,
  64                             (0 << STM_DMA_CCR_MEM2MEM) |
  65                             (STM_DMA_CCR_PL_HIGH << STM_DMA_CCR_PL) |
  66                             (STM_DMA_CCR_MSIZE_16 << STM_DMA_CCR_MSIZE) |
  67                             (STM_DMA_CCR_PSIZE_16 << STM_DMA_CCR_PSIZE) |
  68                             (1 << STM_DMA_CCR_MINC) |
  69                             (0 << STM_DMA_CCR_PINC) |
  70                             (0 << STM_DMA_CCR_CIRC) |
  71                             (STM_DMA_CCR_DIR_PER_TO_MEM << STM_DMA_CCR_DIR));
  72         ao_dma_set_isr(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1), ao_adc_done);
  73         ao_dma_start(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1));
  74
  75         stm_adc1.cr2 = AO_ADC_CR2_VAL(0);
  76         ao_delay(AO_MS_TO_TICKS(10));
  77         stm_adc1.cr2 = AO_ADC_CR2_VAL(0);
  78         ao_delay(AO_MS_TO_TICKS(10));
  79         stm_adc1.cr2 = AO_ADC_CR2_VAL(1);
  80 }
  81
  82 /*
  83  * Fetch a copy of the most recent ADC data
  84  */
  85 void
  86 ao_adc_single_get(struct ao_adc *packet)
  87 {
  88         ao_adc_poll(packet);
  89         ao_arch_block_interrupts();
  90         while (!ao_adc_ready)
  91                 ao_sleep(&ao_adc_ready);
  92         ao_arch_release_interrupts();
  93 }
  94
  95 static void
  96 ao_adc_dump(void)
  97 {
  98         struct ao_adc   packet;
  99         ao_adc_single_get(&packet);
 100         AO_ADC_DUMP(&packet);
 101 }
 102
 103 const struct ao_cmds ao_adc_cmds[] = {
 104         { ao_adc_dump,  "a\0Display current ADC values" },
 105         { 0, NULL },
 106 };
 107
 108 static inline void
 109 adc_pin_set(struct stm_gpio *gpio, int pin)
 110 {
 111         ao_enable_port(gpio);
 112         stm_gpio_conf(gpio, pin,
 113                       STM_GPIO_CR_MODE_INPUT,
 114                       STM_GPIO_CR_CNF_INPUT_ANALOG);
 115 }
 116
 117 void
 118 ao_adc_single_init(void)
 119 {
 120 #ifdef AO_ADC_PIN0_PORT
 121         adc_pin_set(AO_ADC_PIN0_PORT, AO_ADC_PIN0_PIN);
 122 #endif
 123 #ifdef AO_ADC_PIN1_PORT
 124         adc_pin_set(AO_ADC_PIN1_PORT, AO_ADC_PIN1_PIN);
 125 #endif
 126 #ifdef AO_ADC_PIN2_PORT
 127         adc_pin_set(AO_ADC_PIN2_PORT, AO_ADC_PIN2_PIN);
 128 #endif
 129 #ifdef AO_ADC_PIN3_PORT
 130         adc_pin_set(AO_ADC_PIN3_PORT, AO_ADC_PIN3_PIN);
 131 #endif
 132 #ifdef AO_ADC_PIN4_PORT
 133         adc_pin_set(AO_ADC_PIN4_PORT, AO_ADC_PIN4_PIN);
 134 #endif
 135 #ifdef AO_ADC_PIN5_PORT
 136         adc_pin_set(AO_ADC_PIN5_PORT, AO_ADC_PIN5_PIN);
 137 #endif
 138 #ifdef AO_ADC_PIN6_PORT
 139         adc_pin_set(AO_ADC_PIN6_PORT, AO_ADC_PIN6_PIN);
 140 #endif
 141 #ifdef AO_ADC_PIN7_PORT
 142         adc_pin_set(AO_ADC_PIN7_PORT, AO_ADC_PIN7_PIN);
 143 #endif
 144 #ifdef AO_ADC_PIN8_PORT
 145         adc_pin_set(AO_ADC_PIN8_PORT, AO_ADC_PIN8_PIN);
 146 #endif
 147 #ifdef AO_ADC_PIN9_PORT
 148         adc_pin_set(AO_ADC_PIN9_PORT, AO_ADC_PIN9_PIN);
 149 #endif
 150 #ifdef AO_ADC_PIN10_PORT
 151         adc_pin_set(AO_ADC_PIN10_PORT, AO_ADC_PIN10_PIN);
 152 #endif
 153 #ifdef AO_ADC_PIN11_PORT
 154         adc_pin_set(AO_ADC_PIN11_PORT, AO_ADC_PIN11_PIN);
 155 #endif
 156 #ifdef AO_ADC_PIN12_PORT
 157         adc_pin_set(AO_ADC_PIN12_PORT, AO_ADC_PIN12_PIN);
 158 #endif
 159 #ifdef AO_ADC_PIN13_PORT
 160         adc_pin_set(AO_ADC_PIN13_PORT, AO_ADC_PIN13_PIN);
 161 #endif
 162 #ifdef AO_ADC_PIN14_PORT
 163         adc_pin_set(AO_ADC_PIN14_PORT, AO_ADC_PIN14_PIN);
 164 #endif
 165 #ifdef AO_ADC_PIN15_PORT
 166         adc_pin_set(AO_ADC_PIN15_PORT, AO_ADC_PIN15_PIN);
 167 #endif
 168 #ifdef AO_ADC_PIN16_PORT
 169         adc_pin_set(AO_ADC_PIN16_PORT, AO_ADC_PIN16_PIN);
 170 #endif
 171 #ifdef AO_ADC_PIN17_PORT
 172         adc_pin_set(AO_ADC_PIN17_PORT, AO_ADC_PIN17_PIN);
 173 #endif
 174 #ifdef AO_ADC_PIN18_PORT
 175         adc_pin_set(AO_ADC_PIN18_PORT, AO_ADC_PIN18_PIN);
 176 #endif
 177 #ifdef AO_ADC_PIN19_PORT
 178         adc_pin_set(AO_ADC_PIN19_PORT, AO_ADC_PIN19_PIN);
 179 #endif
 180 #ifdef AO_ADC_PIN20_PORT
 181         adc_pin_set(AO_ADC_PIN20_PORT, AO_ADC_PIN20_PIN);
 182 #endif
 183 #ifdef AO_ADC_PIN21_PORT
 184         adc_pin_set(AO_ADC_PIN21_PORT, AO_ADC_PIN21_PIN);
 185 #endif
 186 #ifdef AO_ADC_PIN22_PORT
 187         adc_pin_set(AO_ADC_PIN22_PORT, AO_ADC_PIN22_PIN);
 188 #endif
 189 #ifdef AO_ADC_PIN23_PORT
 190         adc_pin_set(AO_ADC_PIN23_PORT, AO_ADC_PIN23_PIN);
 191 #endif
 192 #ifdef AO_ADC_PIN24_PORT
 193         #error "Too many ADC ports"
 194 #endif
 195
 196         stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_ADC1EN);
 197
 198         /* Turn off ADC during configuration */
 199         stm_adc1.cr2 = 0;
 200
 201         stm_adc1.cr1 = ((0 << STM_ADC_CR1_AWDEN ) |
 202                        (0 << STM_ADC_CR1_JAWDEN ) |
 203                        (STM_ADC_CR1_DUALMOD_INDEPENDENT << STM_ADC_CR1_DUALMOD ) |
 204                        (0 << STM_ADC_CR1_DISCNUM ) |
 205                        (0 << STM_ADC_CR1_JDISCEN ) |
 206                        (0 << STM_ADC_CR1_DISCEN ) |
 207                        (0 << STM_ADC_CR1_JAUTO ) |
 208                        (0 << STM_ADC_CR1_AWDSGL ) |
 209                        (1 << STM_ADC_CR1_SCAN ) |
 210                        (0 << STM_ADC_CR1_JEOCIE ) |
 211                        (0 << STM_ADC_CR1_AWDIE ) |
 212                        (0 << STM_ADC_CR1_EOCIE ) |
 213                        (0 << STM_ADC_CR1_AWDCH ));
 214
 215         /* 384 cycle sample time for everyone */
 216         stm_adc1.smpr1 = 0x00ffffff;
 217         stm_adc1.smpr2 = 0x3fffffff;
 218
 219         stm_adc1.sqr1 = ((AO_NUM_ADC - 1) << 20);
 220 #if AO_NUM_ADC > 0
 221         stm_adc1.sqr3 |= (AO_ADC_SQ1 << 0);
 222 #endif
 223 #if AO_NUM_ADC > 1
 224         stm_adc1.sqr3 |= (AO_ADC_SQ2 << 5);
 225 #endif
 226 #if AO_NUM_ADC > 2
 227         stm_adc1.sqr3 |= (AO_ADC_SQ3 << 10);
 228 #endif
 229 #if AO_NUM_ADC > 3
 230         stm_adc1.sqr3 |= (AO_ADC_SQ4 << 15);
 231 #endif
 232 #if AO_NUM_ADC > 4
 233         stm_adc1.sqr3 |= (AO_ADC_SQ5 << 20);
 234 #endif
 235 #if AO_NUM_ADC > 5
 236         stm_adc1.sqr3 |= (AO_ADC_SQ6 << 25);
 237 #endif
 238 #if AO_NUM_ADC > 6
 239         stm_adc1.sqr2 |= (AO_ADC_SQ7 << 0);
 240 #endif
 241 #if AO_NUM_ADC > 7
 242         stm_adc1.sqr2 |= (AO_ADC_SQ8 << 5);
 243 #endif
 244 #if AO_NUM_ADC > 8
 245         stm_adc1.sqr2 |= (AO_ADC_SQ9 << 10);
 246 #endif
 247 #if AO_NUM_ADC > 9
 248         stm_adc1.sqr2 |= (AO_ADC_SQ10 << 15);
 249 #endif
 250 #if AO_NUM_ADC > 10
 251         stm_adc1.sqr2 |= (AO_ADC_SQ11 << 20);
 252 #endif
 253 #if AO_NUM_ADC > 11
 254         stm_adc1.sqr2 |= (AO_ADC_SQ12 << 25);
 255 #endif
 256 #if AO_NUM_ADC > 12
 257         stm_adc1.sqr1 |= (AO_ADC_SQ13 << 0);
 258 #endif
 259 #if AO_NUM_ADC > 13
 260         stm_adc1.sqr1 |= (AO_ADC_SQ14 << 5);
 261 #endif
 262 #if AO_NUM_ADC > 14
 263         stm_adc1.sqr1 |= (AO_ADC_SQ15 << 10);
 264 #endif
 265 #if AO_NUM_ADC > 15
 266         stm_adc1.sqr1 |= (AO_ADC_SQ16 << 15);
 267 #endif
 268 #if AO_NUM_ADC > 15
 269 #error "too many ADC channels"
 270 #endif
 271
 272         /* Clear any stale status bits */
 273         stm_adc1.sr = 0;
 274
 275         ao_dma_alloc(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1));
 276
 277         ao_cmd_register(&ao_adc_cmds[0]);
 278 }