2 * Copyright © 2012 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
20 struct ao_spi_stm_info {
21 uint8_t miso_dma_index;
22 uint8_t mosi_dma_index;
23 struct stm_spi *stm_spi;
26 static uint8_t ao_spi_mutex[STM_NUM_SPI];
27 static uint8_t ao_spi_index[STM_NUM_SPI];
29 static const struct ao_spi_stm_info ao_spi_stm_info[STM_NUM_SPI] = {
31 .miso_dma_index = STM_DMA_INDEX(STM_DMA_CHANNEL_SPI1_RX),
32 .mosi_dma_index = STM_DMA_INDEX(STM_DMA_CHANNEL_SPI1_TX),
36 .miso_dma_index = STM_DMA_INDEX(STM_DMA_CHANNEL_SPI2_RX),
37 .mosi_dma_index = STM_DMA_INDEX(STM_DMA_CHANNEL_SPI2_TX),
42 static uint8_t spi_dev_null;
51 static uint8_t spi_task_index;
54 validate_spi(struct stm_spi *stm_spi, int which, uint16_t len)
56 uint32_t sr = stm_spi->sr;
58 if (stm_spi != &stm_spi2)
60 spi_tasks[spi_task_index].task = ao_cur_task ? ao_cur_task->task_id : 0;
61 spi_tasks[spi_task_index].which = which;
62 spi_tasks[spi_task_index].tick = ao_time();
63 spi_tasks[spi_task_index].len = len;
64 spi_task_index = (spi_task_index + 1) & (63);
65 if (sr & (1 << STM_SPI_SR_FRE))
67 if (sr & (1 << STM_SPI_SR_BSY))
69 if (sr & (1 << STM_SPI_SR_OVR))
71 if (sr & (1 << STM_SPI_SR_MODF))
73 if (sr & (1 << STM_SPI_SR_UDR))
75 if ((sr & (1 << STM_SPI_SR_TXE)) == 0)
77 if (sr & (1 << STM_SPI_SR_RXNE))
79 if (which != 5 && which != 6 && which != 13)
80 if (ao_cur_task->task_id != ao_spi_mutex[1])
84 #define validate_spi(stm_spi, which, len) do { (void) (which); (void) (len); } while (0)
88 ao_spi_run(uint8_t id, uint8_t which, uint16_t len)
90 struct stm_spi *stm_spi = ao_spi_stm_info[id].stm_spi;
91 uint8_t mosi_dma_index = ao_spi_stm_info[id].mosi_dma_index;
92 uint8_t miso_dma_index = ao_spi_stm_info[id].miso_dma_index;
94 validate_spi(stm_spi, which, len);
96 stm_spi->cr2 = ((0 << STM_SPI_CR2_TXEIE) |
97 (0 << STM_SPI_CR2_RXNEIE) |
98 (0 << STM_SPI_CR2_ERRIE) |
99 (0 << STM_SPI_CR2_SSOE) |
100 (1 << STM_SPI_CR2_TXDMAEN) |
101 (1 << STM_SPI_CR2_RXDMAEN));
103 ao_dma_start(miso_dma_index);
104 ao_dma_start(mosi_dma_index);
107 while (!ao_dma_done[miso_dma_index])
108 ao_sleep(&ao_dma_done[miso_dma_index]);
111 while ((stm_spi->sr & (1 << STM_SPI_SR_TXE)) == 0);
112 while (stm_spi->sr & (1 << STM_SPI_SR_BSY));
114 validate_spi(stm_spi, which+1, len);
118 ao_dma_done_transfer(mosi_dma_index);
119 ao_dma_done_transfer(miso_dma_index);
123 ao_spi_send(const void *block, uint16_t len, uint8_t spi_index)
125 uint8_t id = AO_SPI_INDEX(spi_index);
126 struct stm_spi *stm_spi = ao_spi_stm_info[id].stm_spi;
127 uint8_t mosi_dma_index = ao_spi_stm_info[id].mosi_dma_index;
128 uint8_t miso_dma_index = ao_spi_stm_info[id].miso_dma_index;
130 /* Set up the transmit DMA to deliver data */
131 ao_dma_set_transfer(mosi_dma_index,
135 (0 << STM_DMA_CCR_MEM2MEM) |
136 (STM_DMA_CCR_PL_MEDIUM << STM_DMA_CCR_PL) |
137 (STM_DMA_CCR_MSIZE_8 << STM_DMA_CCR_MSIZE) |
138 (STM_DMA_CCR_PSIZE_8 << STM_DMA_CCR_PSIZE) |
139 (1 << STM_DMA_CCR_MINC) |
140 (0 << STM_DMA_CCR_PINC) |
141 (0 << STM_DMA_CCR_CIRC) |
142 (STM_DMA_CCR_DIR_MEM_TO_PER << STM_DMA_CCR_DIR));
144 /* Set up the receive DMA -- when this is done, we know the SPI unit
145 * is idle. Without this, we'd have to poll waiting for the BSY bit to
148 ao_dma_set_transfer(miso_dma_index,
152 (0 << STM_DMA_CCR_MEM2MEM) |
153 (STM_DMA_CCR_PL_MEDIUM << STM_DMA_CCR_PL) |
154 (STM_DMA_CCR_MSIZE_8 << STM_DMA_CCR_MSIZE) |
155 (STM_DMA_CCR_PSIZE_8 << STM_DMA_CCR_PSIZE) |
156 (0 << STM_DMA_CCR_MINC) |
157 (0 << STM_DMA_CCR_PINC) |
158 (0 << STM_DMA_CCR_CIRC) |
159 (STM_DMA_CCR_DIR_PER_TO_MEM << STM_DMA_CCR_DIR));
161 ao_spi_run(id, 1, len);
165 ao_spi_send_fixed(uint8_t value, uint16_t len, uint8_t spi_index)
167 uint8_t id = AO_SPI_INDEX(spi_index);
168 struct stm_spi *stm_spi = ao_spi_stm_info[id].stm_spi;
169 uint8_t mosi_dma_index = ao_spi_stm_info[id].mosi_dma_index;
170 uint8_t miso_dma_index = ao_spi_stm_info[id].miso_dma_index;
172 /* Set up the transmit DMA to deliver data */
173 ao_dma_set_transfer(mosi_dma_index,
177 (0 << STM_DMA_CCR_MEM2MEM) |
178 (STM_DMA_CCR_PL_MEDIUM << STM_DMA_CCR_PL) |
179 (STM_DMA_CCR_MSIZE_8 << STM_DMA_CCR_MSIZE) |
180 (STM_DMA_CCR_PSIZE_8 << STM_DMA_CCR_PSIZE) |
181 (0 << STM_DMA_CCR_MINC) |
182 (0 << STM_DMA_CCR_PINC) |
183 (0 << STM_DMA_CCR_CIRC) |
184 (STM_DMA_CCR_DIR_MEM_TO_PER << STM_DMA_CCR_DIR));
186 /* Set up the receive DMA -- when this is done, we know the SPI unit
187 * is idle. Without this, we'd have to poll waiting for the BSY bit to
190 ao_dma_set_transfer(miso_dma_index,
194 (0 << STM_DMA_CCR_MEM2MEM) |
195 (STM_DMA_CCR_PL_MEDIUM << STM_DMA_CCR_PL) |
196 (STM_DMA_CCR_MSIZE_8 << STM_DMA_CCR_MSIZE) |
197 (STM_DMA_CCR_PSIZE_8 << STM_DMA_CCR_PSIZE) |
198 (0 << STM_DMA_CCR_MINC) |
199 (0 << STM_DMA_CCR_PINC) |
200 (0 << STM_DMA_CCR_CIRC) |
201 (STM_DMA_CCR_DIR_PER_TO_MEM << STM_DMA_CCR_DIR));
203 ao_spi_run(id, 3, len);
207 ao_spi_send_sync(const void *block, uint16_t len, uint8_t spi_index)
209 uint8_t id = AO_SPI_INDEX(spi_index);
210 const uint8_t *b = block;
211 struct stm_spi *stm_spi = ao_spi_stm_info[id].stm_spi;
213 stm_spi->cr2 = ((0 << STM_SPI_CR2_TXEIE) |
214 (0 << STM_SPI_CR2_RXNEIE) |
215 (0 << STM_SPI_CR2_ERRIE) |
216 (0 << STM_SPI_CR2_SSOE) |
217 (0 << STM_SPI_CR2_TXDMAEN) |
218 (0 << STM_SPI_CR2_RXDMAEN));
219 validate_spi(stm_spi, 7, len);
221 while (!(stm_spi->sr & (1 << STM_SPI_SR_TXE)));
224 while ((stm_spi->sr & (1 << STM_SPI_SR_TXE)) == 0)
226 while (stm_spi->sr & (1 << STM_SPI_SR_BSY))
228 /* Clear the OVR flag */
231 validate_spi(stm_spi, 8, len);
235 ao_spi_recv(void *block, uint16_t len, uint8_t spi_index)
237 uint8_t id = AO_SPI_INDEX(spi_index);
238 struct stm_spi *stm_spi = ao_spi_stm_info[id].stm_spi;
239 uint8_t mosi_dma_index = ao_spi_stm_info[id].mosi_dma_index;
240 uint8_t miso_dma_index = ao_spi_stm_info[id].miso_dma_index;
244 /* Set up transmit DMA to make the SPI hardware actually run */
245 ao_dma_set_transfer(mosi_dma_index,
249 (0 << STM_DMA_CCR_MEM2MEM) |
250 (STM_DMA_CCR_PL_MEDIUM << STM_DMA_CCR_PL) |
251 (STM_DMA_CCR_MSIZE_8 << STM_DMA_CCR_MSIZE) |
252 (STM_DMA_CCR_PSIZE_8 << STM_DMA_CCR_PSIZE) |
253 (0 << STM_DMA_CCR_MINC) |
254 (0 << STM_DMA_CCR_PINC) |
255 (0 << STM_DMA_CCR_CIRC) |
256 (STM_DMA_CCR_DIR_MEM_TO_PER << STM_DMA_CCR_DIR));
258 /* Set up the receive DMA to capture data */
259 ao_dma_set_transfer(miso_dma_index,
263 (0 << STM_DMA_CCR_MEM2MEM) |
264 (STM_DMA_CCR_PL_MEDIUM << STM_DMA_CCR_PL) |
265 (STM_DMA_CCR_MSIZE_8 << STM_DMA_CCR_MSIZE) |
266 (STM_DMA_CCR_PSIZE_8 << STM_DMA_CCR_PSIZE) |
267 (1 << STM_DMA_CCR_MINC) |
268 (0 << STM_DMA_CCR_PINC) |
269 (0 << STM_DMA_CCR_CIRC) |
270 (STM_DMA_CCR_DIR_PER_TO_MEM << STM_DMA_CCR_DIR));
272 ao_spi_run(id, 9, len);
276 ao_spi_duplex(void *out, void *in, uint16_t len, uint8_t spi_index)
278 uint8_t id = AO_SPI_INDEX(spi_index);
279 struct stm_spi *stm_spi = ao_spi_stm_info[id].stm_spi;
280 uint8_t mosi_dma_index = ao_spi_stm_info[id].mosi_dma_index;
281 uint8_t miso_dma_index = ao_spi_stm_info[id].miso_dma_index;
283 /* Set up transmit DMA to send data */
284 ao_dma_set_transfer(mosi_dma_index,
288 (0 << STM_DMA_CCR_MEM2MEM) |
289 (STM_DMA_CCR_PL_MEDIUM << STM_DMA_CCR_PL) |
290 (STM_DMA_CCR_MSIZE_8 << STM_DMA_CCR_MSIZE) |
291 (STM_DMA_CCR_PSIZE_8 << STM_DMA_CCR_PSIZE) |
292 (1 << STM_DMA_CCR_MINC) |
293 (0 << STM_DMA_CCR_PINC) |
294 (0 << STM_DMA_CCR_CIRC) |
295 (STM_DMA_CCR_DIR_MEM_TO_PER << STM_DMA_CCR_DIR));
297 /* Set up the receive DMA to capture data */
298 ao_dma_set_transfer(miso_dma_index,
302 (0 << STM_DMA_CCR_MEM2MEM) |
303 (STM_DMA_CCR_PL_MEDIUM << STM_DMA_CCR_PL) |
304 (STM_DMA_CCR_MSIZE_8 << STM_DMA_CCR_MSIZE) |
305 (STM_DMA_CCR_PSIZE_8 << STM_DMA_CCR_PSIZE) |
306 (1 << STM_DMA_CCR_MINC) |
307 (0 << STM_DMA_CCR_PINC) |
308 (0 << STM_DMA_CCR_CIRC) |
309 (STM_DMA_CCR_DIR_PER_TO_MEM << STM_DMA_CCR_DIR));
310 ao_spi_run(id, 11, len);
314 ao_spi_disable_index(uint8_t spi_index)
316 /* Disable current config
318 switch (AO_SPI_INDEX(spi_index)) {
319 case STM_SPI_INDEX(1):
321 case AO_SPI_1_PA5_PA6_PA7:
322 stm_gpio_set(&stm_gpioa, 5, 1);
323 stm_moder_set(&stm_gpioa, 5, STM_MODER_OUTPUT);
324 stm_moder_set(&stm_gpioa, 6, STM_MODER_INPUT);
325 stm_moder_set(&stm_gpioa, 7, STM_MODER_OUTPUT);
327 case AO_SPI_1_PB3_PB4_PB5:
328 stm_gpio_set(&stm_gpiob, 3, 1);
329 stm_moder_set(&stm_gpiob, 3, STM_MODER_OUTPUT);
330 stm_moder_set(&stm_gpiob, 4, STM_MODER_INPUT);
331 stm_moder_set(&stm_gpiob, 5, STM_MODER_OUTPUT);
333 case AO_SPI_1_PE13_PE14_PE15:
334 stm_gpio_set(&stm_gpioe, 13, 1);
335 stm_moder_set(&stm_gpioe, 13, STM_MODER_OUTPUT);
336 stm_moder_set(&stm_gpioe, 14, STM_MODER_INPUT);
337 stm_moder_set(&stm_gpioe, 15, STM_MODER_OUTPUT);
341 case STM_SPI_INDEX(2):
343 case AO_SPI_2_PB13_PB14_PB15:
344 stm_gpio_set(&stm_gpiob, 13, 1);
345 stm_moder_set(&stm_gpiob, 13, STM_MODER_OUTPUT);
346 stm_moder_set(&stm_gpiob, 14, STM_MODER_INPUT);
347 stm_moder_set(&stm_gpiob, 15, STM_MODER_OUTPUT);
349 case AO_SPI_2_PD1_PD3_PD4:
350 stm_gpio_set(&stm_gpiod, 1, 1);
351 stm_moder_set(&stm_gpiod, 1, STM_MODER_OUTPUT);
352 stm_moder_set(&stm_gpiod, 3, STM_MODER_INPUT);
353 stm_moder_set(&stm_gpiod, 4, STM_MODER_OUTPUT);
361 ao_spi_enable_index(uint8_t spi_index)
363 switch (AO_SPI_INDEX(spi_index)) {
364 case STM_SPI_INDEX(1):
366 case AO_SPI_1_PA5_PA6_PA7:
367 stm_afr_set(&stm_gpioa, 5, STM_AFR_AF5);
368 stm_afr_set(&stm_gpioa, 6, STM_AFR_AF5);
369 stm_afr_set(&stm_gpioa, 7, STM_AFR_AF5);
371 case AO_SPI_1_PB3_PB4_PB5:
372 stm_afr_set(&stm_gpiob, 3, STM_AFR_AF5);
373 stm_afr_set(&stm_gpiob, 4, STM_AFR_AF5);
374 stm_afr_set(&stm_gpiob, 5, STM_AFR_AF5);
376 case AO_SPI_1_PE13_PE14_PE15:
377 stm_afr_set(&stm_gpioe, 13, STM_AFR_AF5);
378 stm_afr_set(&stm_gpioe, 14, STM_AFR_AF5);
379 stm_afr_set(&stm_gpioe, 15, STM_AFR_AF5);
383 case STM_SPI_INDEX(2):
385 case AO_SPI_2_PB13_PB14_PB15:
386 stm_afr_set(&stm_gpiob, 13, STM_AFR_AF5);
387 stm_afr_set(&stm_gpiob, 14, STM_AFR_AF5);
388 stm_afr_set(&stm_gpiob, 15, STM_AFR_AF5);
390 case AO_SPI_2_PD1_PD3_PD4:
391 stm_afr_set(&stm_gpiod, 1, STM_AFR_AF5);
392 stm_afr_set(&stm_gpiod, 3, STM_AFR_AF5);
393 stm_afr_set(&stm_gpiod, 4, STM_AFR_AF5);
401 ao_spi_config(uint8_t spi_index, uint32_t speed)
403 uint8_t id = AO_SPI_INDEX(spi_index);
404 struct stm_spi *stm_spi = ao_spi_stm_info[id].stm_spi;
406 if (spi_index != ao_spi_index[id]) {
408 /* Disable old config
410 ao_spi_disable_index(ao_spi_index[id]);
414 ao_spi_enable_index(spi_index);
416 /* Remember current config
418 ao_spi_index[id] = spi_index;
420 stm_spi->cr1 = ((0 << STM_SPI_CR1_BIDIMODE) | /* Three wire mode */
421 (0 << STM_SPI_CR1_BIDIOE) |
422 (0 << STM_SPI_CR1_CRCEN) | /* CRC disabled */
423 (0 << STM_SPI_CR1_CRCNEXT) |
424 (0 << STM_SPI_CR1_DFF) |
425 (0 << STM_SPI_CR1_RXONLY) |
426 (1 << STM_SPI_CR1_SSM) | /* Software SS handling */
427 (1 << STM_SPI_CR1_SSI) | /* ... */
428 (0 << STM_SPI_CR1_LSBFIRST) | /* Big endian */
429 (1 << STM_SPI_CR1_SPE) | /* Enable SPI unit */
430 (speed << STM_SPI_CR1_BR) | /* baud rate to pclk/4 */
431 (1 << STM_SPI_CR1_MSTR) |
432 (0 << STM_SPI_CR1_CPOL) | /* Format 0 */
433 (0 << STM_SPI_CR1_CPHA));
434 validate_spi(stm_spi, 13, 0);
438 ao_spi_try_get(uint8_t spi_index, uint32_t speed, uint8_t task_id)
440 uint8_t id = AO_SPI_INDEX(spi_index);
442 if (!ao_mutex_try(&ao_spi_mutex[id], task_id))
444 ao_spi_config(spi_index, speed);
449 ao_spi_get(uint8_t spi_index, uint32_t speed)
451 uint8_t id = AO_SPI_INDEX(spi_index);
453 ao_mutex_get(&ao_spi_mutex[id]);
454 ao_spi_config(spi_index, speed);
458 ao_spi_put(uint8_t spi_index)
460 uint8_t id = AO_SPI_INDEX(spi_index);
461 struct stm_spi *stm_spi = ao_spi_stm_info[id].stm_spi;
464 ao_mutex_put(&ao_spi_mutex[id]);
468 ao_spi_channel_init(uint8_t spi_index)
470 uint8_t id = AO_SPI_INDEX(spi_index);
471 struct stm_spi *stm_spi = ao_spi_stm_info[id].stm_spi;
473 ao_spi_disable_index(spi_index);
476 stm_spi->cr2 = ((0 << STM_SPI_CR2_TXEIE) |
477 (0 << STM_SPI_CR2_RXNEIE) |
478 (0 << STM_SPI_CR2_ERRIE) |
479 (0 << STM_SPI_CR2_SSOE) |
480 (0 << STM_SPI_CR2_TXDMAEN) |
481 (0 << STM_SPI_CR2_RXDMAEN));
483 /* Clear any pending data and error flags */
490 ao_spi_dump_cmd(void)
494 for (s = 0; s < 64; s++) {
495 int i = (spi_task_index + s) & 63;
496 if (spi_tasks[i].which) {
498 const char *name = "(none)";
499 for (t = 0; t < ao_num_tasks; t++)
500 if (ao_tasks[t]->task_id == spi_tasks[i].task) {
501 name = ao_tasks[t]->name;
504 printf("%2d: %5d task %2d which %2d len %5d %s\n",
513 for (s = 0; s < STM_NUM_SPI; s++) {
514 struct stm_spi *spi = ao_spi_stm_info[s].stm_spi;
516 printf("%1d: mutex %2d index %3d miso dma %3d mosi dma %3d",
517 s, ao_spi_mutex[s], ao_spi_index[s],
518 ao_spi_stm_info[s].miso_dma_index,
519 ao_spi_stm_info[s].mosi_dma_index);
520 printf(" cr1 %04x cr2 %02x sr %03x\n",
521 spi->cr1, spi->cr2, spi->sr);
526 static const struct ao_cmds ao_spi_cmds[] = {
527 { ao_spi_dump_cmd, "S\0Dump SPI status" },
536 # if SPI_1_PA5_PA6_PA7
537 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOAEN);
538 stm_ospeedr_set(&stm_gpioa, 5, SPI_1_OSPEEDR);
539 stm_ospeedr_set(&stm_gpioa, 6, SPI_1_OSPEEDR);
540 stm_ospeedr_set(&stm_gpioa, 7, SPI_1_OSPEEDR);
542 # if SPI_1_PB3_PB4_PB5
543 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOBEN);
544 stm_ospeedr_set(&stm_gpiob, 3, SPI_1_OSPEEDR);
545 stm_ospeedr_set(&stm_gpiob, 4, SPI_1_OSPEEDR);
546 stm_ospeedr_set(&stm_gpiob, 5, SPI_1_OSPEEDR);
548 # if SPI_1_PE13_PE14_PE15
549 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOEEN);
550 stm_ospeedr_set(&stm_gpioe, 13, SPI_1_OSPEEDR);
551 stm_ospeedr_set(&stm_gpioe, 14, SPI_1_OSPEEDR);
552 stm_ospeedr_set(&stm_gpioe, 15, SPI_1_OSPEEDR);
554 stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_SPI1EN);
555 ao_spi_index[0] = AO_SPI_CONFIG_NONE;
556 ao_spi_channel_init(0);
560 # if SPI_2_PB13_PB14_PB15
561 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOBEN);
562 stm_ospeedr_set(&stm_gpiob, 13, SPI_2_OSPEEDR);
563 stm_ospeedr_set(&stm_gpiob, 14, SPI_2_OSPEEDR);
564 stm_ospeedr_set(&stm_gpiob, 15, SPI_2_OSPEEDR);
566 # if SPI_2_PD1_PD3_PD4
567 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIODEN);
568 stm_ospeedr_set(&stm_gpiod, 1, SPI_2_OSPEEDR);
569 stm_ospeedr_set(&stm_gpiod, 3, SPI_2_OSPEEDR);
570 stm_ospeedr_set(&stm_gpiod, 4, SPI_2_OSPEEDR);
572 stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_SPI2EN);
573 ao_spi_index[1] = AO_SPI_CONFIG_NONE;
574 ao_spi_channel_init(1);
577 ao_cmd_register(&ao_spi_cmds[0]);