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   1 /*
   2  * Copyright © 2012 Keith Packard <keithp@keithp.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; version 2 of the License.
   7  *
   8  * This program is distributed in the hope that it will be useful, but
   9  * WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  11  * General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along
  14  * with this program; if not, write to the Free Software Foundation, Inc.,
  15  * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  16  */
  17
  18 #include "ao.h"
  19
  20 #define NUM_DMA 7
  21
  22 struct ao_dma_config {
  23         void            (*isr)(int arg);
  24         int             arg;
  25 };
  26
  27 uint8_t ao_dma_done[NUM_DMA];
  28
  29 static struct ao_dma_config ao_dma_config[NUM_DMA];
  30 static uint8_t ao_dma_allocated[NUM_DMA];
  31 static uint8_t ao_dma_mutex[NUM_DMA];
  32 static uint8_t ao_dma_active;
  33
  34 static void
  35 ao_dma_isr(uint8_t index) {
  36         /* Get channel interrupt bits */
  37         uint32_t        isr = stm_dma.isr & (STM_DMA_ISR_MASK <<
  38                                              STM_DMA_ISR(index));
  39
  40         /* Ack them */
  41         stm_dma.ifcr = isr;
  42         if (ao_dma_config[index].isr)
  43                 (*ao_dma_config[index].isr)(ao_dma_config[index].arg);
  44         else {
  45                 ao_dma_done[index] = 1;
  46                 ao_wakeup(&ao_dma_done[index]);
  47         }
  48 }
  49
  50 void stm_dma1_channel1_isr(void) { ao_dma_isr(STM_DMA_INDEX(1)); }
  51 void stm_dma1_channel2_isr(void) { ao_dma_isr(STM_DMA_INDEX(2)); }
  52 void stm_dma1_channel3_isr(void) { ao_dma_isr(STM_DMA_INDEX(3)); }
  53 void stm_dma1_channel4_isr(void) { ao_dma_isr(STM_DMA_INDEX(4)); }
  54 void stm_dma1_channel5_isr(void) { ao_dma_isr(STM_DMA_INDEX(5)); }
  55 void stm_dma1_channel6_isr(void) { ao_dma_isr(STM_DMA_INDEX(6)); }
  56 void stm_dma1_channel7_isr(void) { ao_dma_isr(STM_DMA_INDEX(7)); }
  57
  58 void
  59 ao_dma_set_transfer(uint8_t             index,
  60                     volatile void       *peripheral,
  61                     void                *memory,
  62                     uint16_t            count,
  63                     uint32_t            ccr)
  64 {
  65         if (ao_dma_allocated[index]) {
  66                 if (ao_dma_mutex[index])
  67                         ao_panic(AO_PANIC_DMA);
  68                 ao_dma_mutex[index] = 1;
  69         } else
  70                 ao_mutex_get(&ao_dma_mutex[index]);
  71         ao_arch_critical(
  72                 if (ao_dma_active++ == 0)
  73                         stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_DMA1EN);
  74                 );
  75         stm_dma.channel[index].ccr = ccr | (1 << STM_DMA_CCR_TCIE);
  76         stm_dma.channel[index].cndtr = count;
  77         stm_dma.channel[index].cpar = peripheral;
  78         stm_dma.channel[index].cmar = memory;
  79         ao_dma_config[index].isr = NULL;
  80 }
  81
  82 void
  83 ao_dma_set_isr(uint8_t index, void (*isr)(int), int arg)
  84 {
  85         ao_dma_config[index].arg = arg;
  86         ao_dma_config[index].isr = isr;
  87 }
  88
  89 void
  90 ao_dma_start(uint8_t index)
  91 {
  92         ao_dma_done[index] = 0;
  93         stm_dma.channel[index].ccr |= (1 << STM_DMA_CCR_EN);
  94 }
  95
  96 void
  97 ao_dma_done_transfer(uint8_t index)
  98 {
  99         stm_dma.channel[index].ccr &= ~(1 << STM_DMA_CCR_EN);
 100         ao_arch_critical(
 101                 if (--ao_dma_active == 0)
 102                         stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_DMA1EN);
 103                 );
 104         if (ao_dma_allocated[index])
 105                 ao_dma_mutex[index] = 0;
 106         else
 107                 ao_mutex_put(&ao_dma_mutex[index]);
 108 }
 109
 110 void
 111 ao_dma_abort(uint8_t index)
 112 {
 113         stm_dma.channel[index].ccr &= ~(1 << STM_DMA_CCR_EN);
 114         ao_wakeup(&ao_dma_done[index]);
 115 }
 116
 117 void
 118 ao_dma_alloc(uint8_t index)
 119 {
 120         if (ao_dma_allocated[index])
 121                 ao_panic(AO_PANIC_DMA);
 122         ao_dma_allocated[index] = 1;
 123 }
 124
 125 void
 126 ao_dma_init(void)
 127 {
 128         int     index;
 129
 130         for (index = 0; index < STM_NUM_DMA; index++) {
 131                 stm_nvic_set_enable(STM_ISR_DMA1_CHANNEL1_POS + index);
 132                 stm_nvic_set_priority(STM_ISR_DMA1_CHANNEL1_POS + index, 4);
 133                 ao_dma_allocated[index] = 0;
 134                 ao_dma_mutex[index] = 0;
 135         }
 136
 137 }