add attribute to cause DRC to skip the outline layer

diff --git a/teleterra.pcb b/teleterra.pcb
index 05d5e475a34376d1ec7f60956b9261d554d41eb5..95a5410e774a820558665cb4b8466df19c5d6b19 100644 (file)
--- a/teleterra.pcb
+++ b/teleterra.pcb
@@ -2154,6 +2154,7 @@ Layer(2 "bottom")
 )
 Layer(3 "outline")
 (
+       Attribute("PCB::skip-drc" "1")
        Line[27550 0 342550 0 1000 2000 "lock"]
        Line[27550 175200 342550 175200 1000 2000 "lock"]
        Line[0 28550 0 146650 1000 2000 "lock"]