From c3b77606b34e985369af183187138b96482790ff Mon Sep 17 00:00:00 2001 From: Bdale Garbee Date: Sun, 11 Sep 2011 17:19:53 -0600 Subject: [PATCH] add attribute to cause DRC to skip the outline layer --- teleterra.pcb | 1 + 1 file changed, 1 insertion(+) diff --git a/teleterra.pcb b/teleterra.pcb index 05d5e47..95a5410 100644 --- a/teleterra.pcb +++ b/teleterra.pcb @@ -2154,6 +2154,7 @@ Layer(2 "bottom") ) Layer(3 "outline") ( + Attribute("PCB::skip-drc" "1") Line[27550 0 342550 0 1000 2000 "lock"] Line[27550 175200 342550 175200 1000 2000 "lock"] Line[0 28550 0 146650 1000 2000 "lock"] -- 2.30.2