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add outline layer
[hw/telenano]
/
telenano.pcb
2010-11-23
Bdale Garbee
add outline layer
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2010-11-18
Bdale Garbee
lose C9 since it's redundant on such a tight board
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2010-11-18
Bdale Garbee
update to reflect footprint name change
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2010-11-11
Bdale Garbee
fix mask clearance issue identified by freedfm
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2010-11-11
Bdale Garbee
update to reflect desired reset circuit component values
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2010-11-10
Bdale Garbee
reset circuit passive values changed to match TeleMetru...
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2010-11-10
Bdale Garbee
a couple more copper tweaks to clean up overlap "jaggies"
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2010-11-05
Bdale Garbee
lots of copper tweaking
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2010-11-05
Bdale Garbee
clean up ground plane a bit .. fewer thermals on vias...
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2010-11-05
Bdale Garbee
enabling outline layer causes bogus drc errors, so...
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2010-11-04
Bdale Garbee
add copyright symbol to font, update back side silk
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2010-11-03
Bdale Garbee
add an explicit outline layer
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2010-11-03
Bdale Garbee
no drc errors, refdes turned off in the silkscreen
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2010-11-03
Bdale Garbee
added mounting holes, cleaned up back-side silk (produc...
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2010-11-03
Bdale Garbee
down to desired board outline size
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2010-11-03
Bdale Garbee
bottom layer pulled back into new board boundary, silk...
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2010-11-03
Bdale Garbee
fully routed
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2010-11-03
Bdale Garbee
whoa! getting there!
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2010-11-03
Bdale Garbee
rename for consistency with tele* structure
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