add an explicit outline layer

diff --git a/telenano.pcb b/telenano.pcb
index bbd2a3655394ac376aa6e9c7224e90837685f470..f72573f6c3300f84aaa08650e792c95fd09c83bd 100644 (file)
--- a/telenano.pcb
+++ b/telenano.pcb
@@ -1,5 +1,5 @@
 # release: pcb 20091103
-# date:    Wed Nov  3 14:03:30 2010
+# date:    Wed Nov  3 14:09:47 2010
 # user:    bdale (Bdale Garbee,KB0G)
 # host:    rover
 
@@ -14,7 +14,7 @@ PolyArea[200000000.000000]
 Thermal[0.500000]
 DRC[600 1000 600 500 1500 700]
 Flags("nameonpcb,clearnew,snappin,liveroute,hidenames")
-Groups("1,c:2,s")
+Groups("1,c:2,s:3")
 Styles["Signal,1000,2900,1500,1000:Power,2500,6000,3500,1000:Fat,4000,6000,3500,1000:Skinny,600,2402,1181,600"]
 
 Symbol(' ' 18)
@@ -1492,13 +1492,20 @@ Layer(2 "bottom")
                [500 49500] [99500 49500] [99500 500] [500 500] 
        )
 )
-Layer(3 "silk")
+Layer(3 "outline")
+(
+       Line[0 0 100000 0 1000 2000 ""]
+       Line[100000 0 100000 50000 1000 2000 ""]
+       Line[100000 50000 0 50000 1000 2000 ""]
+       Line[0 50000 0 0 1000 2000 ""]
+)
+Layer(4 "silk")
 (
        Text[77215 35422 3 100 "(c) 2010" "auto"]
        Text[84093 42768 3 100 "TeleNano v0.1" "auto"]
        Text[71400 43400 3 100 "Bdale Garbee" "auto"]
 )
-Layer(4 "silk")
+Layer(5 "silk")
 (
 )
 NetList()