add pull-ups on swdio and swclk so Atmel SAMD21, et al, work better

diff --git a/swdadapter.sch b/swdadapter.sch
index 6c374e4940ff4f49f30470261ba68cda64b25f57..2e3c8928a067c24b4ede961f5cfdf9c108043203 100644 (file)
--- a/swdadapter.sch
+++ b/swdadapter.sch
@@ -1,5 +1,5 @@
-v 20130925 2
-C 40000 40000 0 0 0 title-C-bdale.sym
+v 20220529 2
+C 40000 40000 0 0 0 title-C.sym
 T 55700 40400 9 10 1 0 0 0 1
 swdadapter.sch
 T 57900 40400 9 10 1 0 0 0 1
@@ -7,20 +7,20 @@ T 57900 40400 9 10 1 0 0 0 1
 T 58600 40400 9 10 1 0 0 0 1
 1
 T 60300 40400 9 10 1 0 0 0 1
-2
+3
 T 56500 41800 9 30 1 0 0 0 1
 SWD Adapter
-C 45500 45000 1 0 1 conn-20.sym
+C 44500 45000 1 0 1 conn-20.sym
 {
-T 45245 52895 5 10 1 1 0 6 1
+T 44245 52895 5 10 1 1 0 6 1
 refdes=J1
-T 45500 45000 5 30 0 1 0 6 1
+T 44500 45000 5 30 0 1 0 6 1
 vendor=mouser
-T 45500 45000 5 30 0 1 0 6 1
+T 44500 45000 5 30 0 1 0 6 1
 vendor_part_number=649-87606-310LF
-T 45500 45000 5 30 0 1 0 6 1
+T 44500 45000 5 30 0 1 0 6 1
 footprint=100mil10x2
-T 45200 44800 5 10 1 1 0 6 1
+T 44200 44800 5 10 1 1 0 6 1
 value=JTAG
 }
 C 52400 46400 1 90 1 conn-4.sym
@@ -61,64 +61,64 @@ T 48100 51700 5 30 0 0 0 0 1
 footprint=OS102011
 }
 C 50100 52900 1 0 0 3.3V-plus.sym
-C 45800 44400 1 0 0 gnd.sym
-N 45500 52700 45900 52700 4
-N 45500 52300 48600 52300 4
+C 45700 44400 1 0 0 gnd.sym
+N 44500 52700 44900 52700 4
+N 44500 52300 48600 52300 4
 {
-T 45650 52350 5 10 1 1 0 0 1
+T 44650 52350 5 10 1 1 0 0 1
 netname=mcu vdd
 }
-N 45900 52300 45900 52700 4
+N 44900 52300 44900 52700 4
 N 49600 52600 50300 52600 4
 N 50300 50700 50300 52900 4
-N 45900 44700 45900 51500 4
-N 45900 45100 45500 45100 4
-N 45900 45900 45500 45900 4
-N 45900 46700 45500 46700 4
-N 45900 47500 45500 47500 4
-N 45900 48300 45500 48300 4
-N 45900 49100 45500 49100 4
-N 45900 49900 45500 49900 4
-N 45900 50700 45500 50700 4
-N 45900 51500 45500 51500 4
+N 45800 44700 45800 51500 4
+N 45800 45100 44500 45100 4
+N 45800 45900 44500 45900 4
+N 45800 46700 44500 46700 4
+N 45800 47500 44500 47500 4
+N 45800 48300 44500 48300 4
+N 45800 49100 44500 49100 4
+N 45800 49900 44500 49900 4
+N 45800 50700 44500 50700 4
+N 45800 51500 44500 51500 4
 N 49600 52000 51500 52000 4
 N 51500 52000 51500 49900 4
 N 52500 49900 51500 49900 4
-N 45500 49500 52500 49500 4
+N 44500 49500 52500 49500 4
 {
-T 45650 49550 5 10 1 1 0 0 1
+T 44650 49550 5 10 1 1 0 0 1
 netname=swclk
 }
-N 52500 49100 45900 49100 4
-N 45500 50300 49000 50300 4
+N 52500 49100 45800 49100 4
+N 44500 50300 49000 50300 4
 {
-T 45650 50350 5 10 1 1 0 0 1
+T 44650 50350 5 10 1 1 0 0 1
 netname=swdio
 }
 N 49000 50300 49000 48700 4
 N 49000 48700 52500 48700 4
-N 45500 47100 49000 47100 4
+N 44500 47100 49000 47100 4
 {
-T 45650 47150 5 10 1 1 0 0 1
+T 44650 47150 5 10 1 1 0 0 1
 netname=nrst
 }
 N 49000 47100 49000 48300 4
 N 49000 48300 52500 48300 4
-N 45500 47900 52500 47900 4
+N 44500 47900 52500 47900 4
 {
-T 45650 47950 5 10 1 1 0 0 1
+T 44650 47950 5 10 1 1 0 0 1
 netname=traceswo
 }
-N 45900 46500 51100 46500 4
+N 45800 46500 51100 46500 4
 N 51100 46500 51100 46400 4
 N 51500 46400 51500 48300 4
 N 51900 46400 51900 48700 4
 N 52300 46400 52300 49500 4
-T 48400 51400 9 10 1 0 0 0 1
+T 48400 51200 9 10 1 0 0 0 1
 Target VCC / 3.3V
-N 45500 45500 49400 45500 4
+N 44500 45500 49400 45500 4
 {
-T 45650 45550 5 10 1 1 0 0 1
+T 44650 45550 5 10 1 1 0 0 1
 netname=vdd
 }
 N 49400 45500 49400 50700 4
@@ -141,3 +141,62 @@ footprint=lph
 N 51100 47200 51500 47200 4
 N 50100 47200 50000 47200 4
 N 50000 47200 50000 46500 4
+C 46800 50900 1 90 0 resistor.sym
+{
+T 46400 51200 5 10 0 0 90 0 1
+device=RESISTOR
+T 46800 51400 5 10 1 1 0 0 1
+refdes=R1
+T 46800 51100 5 10 1 1 0 0 1
+value=100k
+T 46800 50900 5 10 0 1 0 0 1
+footprint=0402
+}
+C 47500 50900 1 90 0 resistor.sym
+{
+T 47100 51200 5 10 0 0 90 0 1
+device=RESISTOR
+T 47500 51400 5 10 1 1 0 0 1
+refdes=R2
+T 47500 51100 5 10 1 1 0 0 1
+value=100k
+T 47500 50900 5 10 0 1 0 0 1
+footprint=0402
+}
+N 46700 51800 46700 52300 4
+N 47400 51800 47400 52300 4
+N 47400 50900 47400 49500 4
+N 46700 50900 46700 50300 4
+T 54900 40800 9 10 1 0 0 0 2
+                    Copyright 2023 by Bdale Garbee <bdale@gag.com>
+Licensed under the TAPR Open Hardware License, http://www.tapr.org/OHL
+C 44500 51800 1 0 0 nc-right.sym
+{
+T 44600 52300 5 10 0 0 0 0 1
+value=NoConnection
+T 44600 52500 5 10 0 0 0 0 1
+device=DRC_Directive
+}
+C 44500 51000 1 0 0 nc-right.sym
+{
+T 44600 51500 5 10 0 0 0 0 1
+value=NoConnection
+T 44600 51700 5 10 0 0 0 0 1
+device=DRC_Directive
+}
+C 44500 48600 1 0 0 nc-right.sym
+{
+T 44600 49100 5 10 0 0 0 0 1
+value=NoConnection
+T 44600 49300 5 10 0 0 0 0 1
+device=DRC_Directive
+}
+C 44500 46200 1 0 0 nc-right.sym
+{
+T 44600 46700 5 10 0 0 0 0 1
+value=NoConnection
+T 44600 46900 5 10 0 0 0 0 1
+device=DRC_Directive
+}
+C 49000 51400 1 0 0 gnd.sym
+C 49200 53200 1 180 0 gnd.sym